[Intel-gfx] [ANNOUNCE] xf86-video-intel 2.19.0 [resend]

2012-05-01 Thread Chris Wilson
I sent this out over the weekend and never saw it arrive, so presuming the announcement was lost in transit... Release 2.19.0 (2012-04-29) === More stability fixes for UXA and support for another variant of IvyBridge. Given the severity of the stability fixes, I strongly

Re: [Intel-gfx] [PATCH] drm/i915: Only enable IPS polling for gen5

2012-05-01 Thread Jesse Barnes
On Mon, 30 Apr 2012 19:35:02 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: On SandyBridge IPS was entirely implemented in hardware and not reliant on the driver monitoring power consumption and feeding back desired run states, so the hardware is able to adapt quicker and more flexibly.

Re: [Intel-gfx] [PATCH 19/24] drm/i915: detect digital outputs on Haswell

2012-05-01 Thread Jesse Barnes
On Mon, 30 Apr 2012 21:33:42 -0300 Eugeni Dodonov eug...@dodonov.net wrote: On Mon, Apr 30, 2012 at 21:27, Jesse Barnes jbar...@virtuousgeek.orgwrote: We really really need to get the port detection working on HSW using the VBT. It is not that easy from what I've seen. VBT can give

Re: [Intel-gfx] [PATCH] drm/i915: Only enable IPS polling for gen5

2012-05-01 Thread Daniel Vetter
On Tue, May 01, 2012 at 07:58:27AM -0700, Jesse Barnes wrote: On Mon, 30 Apr 2012 19:35:02 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: On SandyBridge IPS was entirely implemented in hardware and not reliant on the driver monitoring power consumption and feeding back desired run

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Dynamic Parity Detection handling

2012-05-01 Thread Daniel Vetter
On Fri, Apr 27, 2012 at 05:40:18PM -0700, Ben Widawsky wrote: On IVB hardware we are given an interrupt whenever a L3 parity error occurs in the L3 cache. The L3 cache is used by internal GPU clients only. This is a very rare occurrence (in fact to test this I need to use specially

Re: [Intel-gfx] [PATCH 4/5] drm/i915: wait render timeout ioctl

2012-05-01 Thread Ben Widawsky
On Tue, 01 May 2012 10:19:53 -0700 Eric Anholt e...@anholt.net wrote: On Mon, 30 Apr 2012 18:41:08 -0700, Ben Widawsky b...@bwidawsk.net wrote: This helps implement GL_ARB_sync put stops short of allowing full blow but? blown?

Re: [Intel-gfx] [PATCH 5/5] drm/i915: l3 parity sysfs interface

2012-05-01 Thread Daniel Vetter
On Fri, Apr 27, 2012 at 05:40:21PM -0700, Ben Widawsky wrote: Dumb binary interfaces which allow root-only updates of the cache remapping registers. As mentioned in a previous patch, software using this interface needs to know about HW limits, and other programming considerations as the kernel

Re: [Intel-gfx] [PATCH 5/5] drm/i915: l3 parity sysfs interface

2012-05-01 Thread Ben Widawsky
On Tue, 1 May 2012 20:24:44 +0200 Daniel Vetter dan...@ffwll.ch wrote: On Fri, Apr 27, 2012 at 05:40:21PM -0700, Ben Widawsky wrote: Dumb binary interfaces which allow root-only updates of the cache remapping registers. As mentioned in a previous patch, software using this interface needs

Re: [Intel-gfx] [PATCH 19/24] drm/i915: detect digital outputs on Haswell

2012-05-01 Thread Keith Packard
On Tue, 1 May 2012 08:01:08 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: I had wanted to avoid every HSW system looking like it had a bunch of HDMI and DP ports, when it really only has one of each or something. Every DP port is also an HDMI port when a DP to HDMI converter is plugged