On Mon, Jul 30, 2012 at 01:51:38PM -0700, Stéphane Marchesin wrote:
This function isn't used outside of intel_panel.c, so make it static.
Signed-off-by: Stéphane Marchesin marc...@chromium.org
Picked up for -fixes, thanks for the patch.
-Daniel
--
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile:
On Wed, Aug 01, 2012 at 09:51:46AM +0800, Yi Sun wrote:
That option will save all the images which are created and intended to paint
on screen.
The images will be saved in folder saveimages with PNG format.
Signed-off-by: Yi Sun yi@intel.com
tbh I don't see the point of this. Care to
On Thu, Aug 02, 2012 at 01:37:05PM +1000, Francois Rigaut wrote:
Dave, Greg,
OK, the problem was indeed a connection issue. By using gfxcardstatus
within osx, I was able to force the HD4000 to connect to the display.
The xorg log now reports:
[ 8.226] (--) PCI:*(0:0:2:0)
On Thu, Aug 02, 2012 at 09:06:48AM -0700, Ben Widawsky wrote:
On 2012-08-02 05:07, Vijay Purushothaman wrote:
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and
write
registers residing in this space.
On Thu, 2 Aug 2012 09:06:48 -0700
Ben Widawsky b...@bwidawsk.net wrote:
On 2012-08-02 05:07, Vijay Purushothaman wrote:
In Valleyview the DPLL and lane control registers are accessible
only through side band fabric called DPIO. Added two tools to read
and write
registers residing in this
We want to use the option to save the images which are intended to be painted
on the screen.
The images will be save in the folder saveimages, and named like
1_1920x1...@60.png, 2_1920x1080@60 .
That would be help for our automatic display testing. If some mode can't be
lighten up in
Daniel,
my bad for the dmesg. It's there:
http://maumae.net/retina/intel_corrupted_drm_debug/dmesg_intel_corrupted_drm_debug
I took pictures with a camera, and uploaded them at
Small 800x600 versions:
http://maumae.net/retina/intel_corrupted_drm_debug/intel_corrupted_upper_left_small.jpg
On Mon, Aug 6, 2012 at 10:59 AM, Francois Rigaut frig...@gmail.com wrote:
Daniel,
my bad for the dmesg. It's there:
http://maumae.net/retina/intel_corrupted_drm_debug/dmesg_intel_corrupted_drm_debug
I took pictures with a camera, and uploaded them at
Small 800x600 versions:
Hey Daniel,
I had v3 patches under review and will send them out later.
dev_priv-pipe_to_crtc_mapping[pipe];
+ DRM_DEBUG_DRIVER(Enable transcoder %c\n,
pipe_name(pipe));
Do we really want this?
... and in kms code we use DRM_DEBUG_KMS.
I'd removed this debug message
This patch series enable HDMI audio on Haswell platform, not DP audio.
The DP enablement will come after the DP patches are upstream.
I tested this patch on Sharkbay machine and i could hear clear sound from
HDMI port.
V2 patches fixed one warning and some type errors.
V3 patches changes:
-
HDMI audio related registers will be configured in write_eld callback.
Signed-off-by: Wang Xingchao xingchao.w...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c
Configure the related HDMI audio register to generate an unsolicited
response to the audio controller driver to indicate that the controller
sequence should start.
Use pipe way to get correct register definitions for IBX/CPT/HSW.
Signed-off-by: Wang Xingchao xingchao.w...@intel.com
---
On Sun, Jul 01, 2012 at 09:50:34AM -0700, Ben Widawsky wrote:
On Sun, 1 Jul 2012 11:39:40 +0800
Hunt Xu mhun...@gmail.com wrote:
Commit 0136db586c028f71e7cc21cc183064ff0d5919c8 merges rc6 information
into the power group. However, when compiled with CONFIG_PM not set,
modprobing i915
Ben Widawsky b...@bwidawsk.net writes:
On 2012-08-02 11:29, Eric Anholt wrote:
Yikes, who spelled caching wrong?
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Yeah, would be nice to get that fixed in the kernel before we have to
cringe forever.
pgpR6HO5ph125.pgp
Description: PGP signature
On Mon, Aug 06, 2012 at 11:40:36PM +1000, Francois Rigaut wrote:
Daniel,
On Mon, Aug 6, 2012 at 7:17 PM, Daniel Vetter dan...@ffwll.ch
mailto:dan...@ffwll.ch wrote:
On Mon, Aug 6, 2012 at 10:59 AM, Francois Rigaut frig...@gmail.com
mailto:frig...@gmail.com wrote:
Daniel,
On 2012-08-06 00:16, Daniel Vetter wrote:
On Thu, Aug 02, 2012 at 09:06:48AM -0700, Ben Widawsky wrote:
On 2012-08-02 05:07, Vijay Purushothaman wrote:
In Valleyview the DPLL and lane control registers are accessible
only
through side band fabric called DPIO. Added two tools to read and
write
On Mon, 6 Aug 2012 13:10:33 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
On Thu, 2 Aug 2012 09:06:48 -0700
Ben Widawsky b...@bwidawsk.net wrote:
On 2012-08-02 05:07, Vijay Purushothaman wrote:
In Valleyview the DPLL and lane control registers are accessible
only
From: Paulo Zanoni paulo.r.zan...@intel.com
Also properly indent the HB IDs.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/char/agp/intel-agp.h| 39 +
drivers/char/agp/intel-gtt.c| 60 ++-
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
intel/intel_chipset.h | 68 ---
1 file changed, 65 insertions(+), 3 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
src/intel_driver.h | 37 +++
src/intel_module.c | 73 ++
2 files changed, 110 insertions(+)
diff --git
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
lib/intel_chipset.h | 68 ++---
1 file changed, 65 insertions(+), 3 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
2012/8/6 Paulo Zanoni przan...@gmail.com:
From: Paulo Zanoni paulo.r.zan...@intel.com
Also properly indent the HB IDs.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/char/agp/intel-agp.h| 39 +
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Mon, Aug 6, 2012 at 6:48 PM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
src/intel_driver.h | 37 +++
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Mon, Aug 6, 2012 at 6:49 PM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
lib/intel_chipset.h | 68
On 08/06/2012 02:50 PM, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Do you have push access? If not, I can commit this for you.
While trying to track down the power regression, I noticed that on my
SNB I had more severe problems, ie. forcewake seemed to never happen
once i915 was loaded. After a bit of bisection, I tracked the bad commit
to:
commit 7b0cfee1a24efdfe0235bac62e53f686fe8a8e24
Merge: 9756fe3 6b16351
Author:
As I read this new (to me) file I get the impression that it really
applies to haswell and not the earlier parts, is that correct?
thanks
ron
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