Hi Dave,
Last pile of stuff for 3.7, essentially just a bunch of bigger fixes and a
few less intrusive features:
- cpu freq interface in sysfs from Ben
- cpu edp fixes and some related cleanups
- write-combining ptes for pre-gen6 (Chris)
- basic CADL support (Peter Wu), this fixes quite a few
On Tue, Sep 25, 2012 at 10:16:12AM +0100, Chris Wilson wrote:
Finishes commit 02d719562ef40483648b2cc46899d4a2ff5953bb
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Thu Aug 9 16:44:54 2012 +0200
drm/i915: properly guard ilk ips state
The core functions were annotated with their
On Tue, Sep 25, 2012 at 09:55:35AM -0700, Ben Widawsky wrote:
On Tue, 25 Sep 2012 10:43:55 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, 25 Sep 2012 10:32:17 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Sat, Sep 22, 2012 at 2:01 AM, Ben Widawsky b...@bwidawsk.net wrote:
On Sat, Sep 22, 2012 at 01:58:37PM -0700, Ben Widawsky wrote:
On 2012-09-22 11:05, Daniel Vetter wrote:
And a quick comment on your approach here: I'm not too sure
whether the
file-base register block approach scales, respectively why exactly
this is
better than frobbing the reg_dumper tool.
On Mon, Sep 17, 2012 at 05:10:15PM -0700, Ben Widawsky wrote:
I do not currently have a VLV to test this on, but hopefully it only
removes information from debugfs, sysfs, and prevents enabling an
unsupported mode.
CC: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ben Widawsky
On Thu, Sep 20, 2012 at 03:28:45PM +0300, Jani Nikula wrote:
On Tue, 18 Sep 2012, Adam Jackson a...@redhat.com wrote:
v2: Fix parenthesis mismatch, spotted by Jani Nikula
Tested-by: Takashi Iwai ti...@suse.de
Signed-off-by: Adam Jackson a...@redhat.com
---
The intention was to allow the caller to avoid a failure to queue a
request having already written commands to the ring. However, this is a
moot point as the i915_add_request() can fail for other reasons than a
mere allocation failure and those failure cases are more likely than
ENOMEM. So the
On Wed, 26 Sep 2012 13:35:33 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
The intention was to allow the caller to avoid a failure to queue a
request having already written commands to the ring. However, this is a
moot point as the i915_add_request() can fail for other reasons than a
On Thu, Sep 20, 2012 at 06:45:29PM -0300, Paulo Zanoni wrote:
2012/9/20 Adam Jackson a...@redhat.com:
Signed-off-by: Adam Jackson a...@redhat.com
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Both patches merged to dinq (again with Dave's irc-ack for the common
stuff).
Thanks, Daniel
The intention was to allow the caller to avoid a failure to queue a
request having already written commands to the ring. However, this is a
moot point as the i915_add_request() can fail for other reasons than a
mere allocation failure and those failure cases are more likely than
ENOMEM. So the
On Tue, Sep 25, 2012 at 05:13:17PM +0800, Yi Sun wrote:
Each mode line has a number just like '[i]'. So we can only test the
specified mode with giving the number of mode to '-o' parameter.
Signed-off-by: Yi Sun yi@intel.com
Merged, thanks for the patch.
-Daniel
diff --git
The intention was to allow the caller to avoid a failure to queue a
request having already written commands to the ring. However, this is a
moot point as the i915_add_request() can fail for other reasons than a
mere allocation failure and those failure cases are more likely than
ENOMEM. So the
This patch set enables all supported display interfaces like HDMI, DisplayPort
and eDP for Valleyview. This also enables support for multi-display
configurations.
Jesse, Ben : Since this patch set was reviewed in internal mailing lists, could
you please add your reviewed-by tested-by tags?
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |8 +++-
Added DPIO data lane register definitions for Valleyview
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL sequence.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
Signed-off-by: Gajanan
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
From: Bhat, Gajanan gajanan.b...@intel.com
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, extended desktop) should work for VLV.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
On Wed, Sep 19, 2012 at 01:29:01PM -0700, Jesse Barnes wrote:
To match IVB.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL sequence.
Signed-off-by: Vijay Purushothaman
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use
On Wed, Sep 26, 2012 at 07:07:36PM +0530, Vijay Purushothaman wrote:
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
From: Bhat, Gajanan gajanan.b...@intel.com
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, extended desktop) should
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different
The dithering introduced in
commit 3b5c78a35cf7511c15e09a9b0ffab290a42d9bcf
Author: Adam Jackson a...@redhat.com
Date: Tue Dec 13 15:41:00 2011 -0800
drm/i915/dp: Dither down to 6bpc if it makes the mode fit
stores the INTEL_MODE_DP_FORCE_6BPC flag in the private_flags of the
adjusted
The dithering introduced in
commit 3b5c78a35cf7511c15e09a9b0ffab290a42d9bcf
Author: Adam Jackson a...@redhat.com
Date: Tue Dec 13 15:41:00 2011 -0800
drm/i915/dp: Dither down to 6bpc if it makes the mode fit
stores the INTEL_MODE_DP_FORCE_6BPC flag in the private_flags of the
adjusted
On Wed, 2012-09-26 at 18:43 +0300, Jani Nikula wrote:
The dithering introduced in
commit 3b5c78a35cf7511c15e09a9b0ffab290a42d9bcf
Author: Adam Jackson a...@redhat.com
Date: Tue Dec 13 15:41:00 2011 -0800
drm/i915/dp: Dither down to 6bpc if it makes the mode fit
stores the
In commit cdb0e95bf571dccc1f75fef9bdad21b167ef0b37
Author: Keith Packard kei...@keithp.com
Date: Tue Nov 1 20:00:06 2011 -0700
drm/i915: Try harder during dp pattern 1 link training
extra passes were made to retry the same voltage and then retry a full
clock reset. However, as coverity
Hi. I've got a Thinkpad X201 with Integrated Graphics Controller
(rev 02), Intel(R) Arrandale running Gentoo Linux. The documentation
mentions Option TripleBuffer boolean
but when I try to use this to control triple-buffering, the
Xorg.0.log shows
(WW) intel(0): Option TripleBuffer is
From: Damien Lespiau damien.lesp...@intel.com
Those infoframes are programmed when using stereo 3D modes.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
tools/intel_infoframes.c | 63 +-
1 files changed, 62 insertions(+), 1 deletions(-)
There is a special mechanism for communicating with the PCU already
being used for the ring frequency stuff. As we'll be needing this for
other commands, extract it now to make future code less error prone and
the current code more reusable.
I'm not entirely sure if this code matches 1:1 with the
BIOS should be setting the minimum voltage for rc6 to be 450mV. Old or
buggy BIOSen may not be doing this, so we correct it for them. Ideally
customers should update the BIOS as only it would know the optimal
values for the platform, so we leave that fact as a DRM_ERROR for the
user to see.
CC: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
On Wed, Sep 26, 2012 at 10:34 AM, Ben Widawsky b...@bwidawsk.net wrote:
BIOS should be setting the minimum voltage for rc6 to be 450mV. Old or
buggy BIOSen may not be doing this, so we correct it for them. Ideally
customers should update the BIOS as only it would know the optimal
values for
On Wed, 26 Sep 2012 13:51:01 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sat, Sep 22, 2012 at 01:58:37PM -0700, Ben Widawsky wrote:
On 2012-09-22 11:05, Daniel Vetter wrote:
And a quick comment on your approach here: I'm not too sure
whether the
file-base register block approach
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Wed, Sep 26, 2012 at 2:17 PM, Damien Lespiau
damien.lesp...@gmail.com wrote:
From: Damien Lespiau damien.lesp...@intel.com
Those infoframes are programmed when using stereo 3D modes.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
On the EINVAL case we don't release struct_mutex. It should be safe to
grab the lock after checking the parameters, which also resolves the
issues.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
The support for Main/High profile has been done in the staging branch.
We will merge the interfaces for Main/High profile back into the master
branch.
Thanks
Haihao
Hello my name is Charlie Good and I am the CTO of Wowza Media System.
We are the authors of Wowza Media Server. Our product
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