On Thu, Sep 27, 2012 at 06:32:06AM +, Wang, Xingchao wrote:
Hi Ben,
I have no idea about the resolution, maybe Paulo and Daniel know more details?
Oh, it's just an older assert for pre-hsw that we haven't properly
disabled yet. Since this code will change quite a bit with Paulo's new
way
On Wed, Sep 26, 2012 at 11:50:36AM -0400, Adam Jackson wrote:
On Wed, 2012-09-26 at 18:43 +0300, Jani Nikula wrote:
The dithering introduced in
commit 3b5c78a35cf7511c15e09a9b0ffab290a42d9bcf
Author: Adam Jackson a...@redhat.com
Date: Tue Dec 13 15:41:00 2011 -0800
On Wed, Sep 26, 2012 at 08:01:09PM -0300, Rodrigo Vivi wrote:
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Wed, Sep 26, 2012 at 2:17 PM, Damien Lespiau
damien.lesp...@gmail.com wrote:
From: Damien Lespiau damien.lesp...@intel.com
Those infoframes are programmed when using stereo
On Wed, Sep 26, 2012 at 04:15:20PM -0700, Ben Widawsky wrote:
On the EINVAL case we don't release struct_mutex. It should be safe to
grab the lock after checking the parameters, which also resolves the
issues.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Nice catch, thanks for the patch,
On Wed, 26 Sep 2012, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu/drm/i915/intel_display.c
On Wed, 26 Sep 2012, Chris Wilson ch...@chris-wilson.co.uk wrote:
The intention was to allow the caller to avoid a failure to queue a
request having already written commands to the ring. However, this is a
moot point as the i915_add_request() can fail for other reasons than a
mere allocation
As SandyBridge returns garbage when decoding certain addresses through
the GTT (all memory below 1MiB and a very small number of individual
pages) we need to prevent the GPU from utilizing those pages. The
ultimate goal would be to prevent our allocator from handing us those
pages, but that is a
This is great news. I will watch for the udpate.
Charlie
-Original Message-
From: Xiang, Haihao [mailto:haihao.xi...@intel.com]
Sent: Wednesday, September 26, 2012 9:17 PM
To: Charlie Good
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] Question regarding libva encoding
FWIW, I am able to get graphics on the screen now - Apparently only the
hdmi port works on HSW right now - which I was unaware of.
This stack was a red-herring to that problem.
Thanks for the response.
Ben
On Thu, Sep 27, 2012 at 2:34 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Sep 27,
On Thu, Sep 27, 2012 at 10:39:53AM +0300, Jani Nikula wrote:
On Wed, 26 Sep 2012, Chris Wilson ch...@chris-wilson.co.uk wrote:
The intention was to allow the caller to avoid a failure to queue a
request having already written commands to the ring. However, this is a
moot point as the
On Wed, Sep 26, 2012 at 11:40:26AM -0700, Ben Widawsky wrote:
On Wed, 26 Sep 2012 13:51:01 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sat, Sep 22, 2012 at 01:58:37PM -0700, Ben Widawsky wrote:
On 2012-09-22 11:05, Daniel Vetter wrote:
And a quick comment on your approach here: I'm
On Thu, Sep 27, 2012 at 09:27:57AM +0100, Chris Wilson wrote:
As SandyBridge returns garbage when decoding certain addresses through
the GTT (all memory below 1MiB and a very small number of individual
pages) we need to prevent the GPU from utilizing those pages. The
ultimate goal would be to
On Thu, Sep 27, 2012 at 02:14:22PM +0200, Daniel Vetter wrote:
On Thu, Sep 27, 2012 at 09:27:57AM +0100, Chris Wilson wrote:
As SandyBridge returns garbage when decoding certain addresses through
the GTT (all memory below 1MiB and a very small number of individual
pages) we need to prevent
On Thu, 27 Sep 2012 14:16:11 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Sep 27, 2012 at 02:14:22PM +0200, Daniel Vetter wrote:
On Thu, Sep 27, 2012 at 09:27:57AM +0100, Chris Wilson wrote:
As SandyBridge returns garbage when decoding certain addresses through
the GTT (all memory
On Thu, Sep 20, 2012 at 11:17:51AM +0200, Daniel Vetter wrote:
On Thu, Sep 20, 2012 at 10:56 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
We need to wait for pending operations on the CRTC to retire before we
can modify the CRTC. For example, if userspace has queued a batch that
uses
On 9/26/2012 7:54 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL
On 9/26/2012 8:08 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by:
On 9/26/2012 8:10 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
From: Bhat, Gajanan gajanan.b...@intel.com
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
On 9/26/2012 8:19 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in
On 9/27/2012 12:48 PM, Jani Nikula wrote:
On Wed, 26 Sep 2012, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
---
This patch set enables all supported display interfaces like HDMI, DisplayPort
and eDP for Valleyview. This also enables support for multi-display
configurations.
v2: Addressed review comments from Daniel and Jani Nikula.
Gajanan Bhat (1):
drm/i915: Add eDP support for Valleyview
Vijay
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |8 +++-
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
drivers/gpu/drm/i915/intel_dp.c
Added DPIO data lane register definitions for Valleyview
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as
separate
Temporary work around to avoid spurious crt hotplug interrupts.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
drivers/gpu/drm/i915/intel_crt.c |7 +++
1 file changed, 7 insertions(+)
diff --git
From: Gajanan Bhat gajanan.b...@intel.com
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
Fixed correct min, max vco limits and dip ctl reg
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
On Thu, Sep 27, 2012 at 07:08:41PM +0530, Vijay Purushothaman wrote:
On 9/26/2012 8:19 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived
On Thu, 27 Sep 2012 19:13:01 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
On Thu, 27 Sep 2012 19:13:02 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
On Thu, 27 Sep 2012 19:13:04 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Ben Widawsky
On Thu, 27 Sep 2012 19:13:05 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
Temporary work around to avoid spurious crt hotplug interrupts.
Signed-off-by: Vijay Purushothaman vijay.a.purushotha...@intel.com
Signed-off-by: Gajanan Bhat gajanan.b...@intel.com
---
On Thu, 27 Sep 2012 19:13:06 +0530
Vijay Purushothaman vijay.a.purushotha...@intel.com wrote:
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
On Thu, Sep 27, 2012 at 5:34 PM, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, 26 Sep 2012 14:06:36 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Sep 17, 2012 at 05:10:15PM -0700, Ben Widawsky wrote:
I do not currently have a VLV to test this on, but hopefully it only
removes
On Wed, 26 Sep 2012 10:34:00 -0700
Ben Widawsky b...@bwidawsk.net wrote:
There is a special mechanism for communicating with the PCU already
being used for the ring frequency stuff. As we'll be needing this for
other commands, extract it now to make future code less error prone and
the
On Wed, 26 Sep 2012 10:34:01 -0700
Ben Widawsky b...@bwidawsk.net wrote:
BIOS should be setting the minimum voltage for rc6 to be 450mV. Old or
buggy BIOSen may not be doing this, so we correct it for them. Ideally
customers should update the BIOS as only it would know the optimal
values for
On Wed, 26 Sep 2012 10:34:02 -0700
Ben Widawsky b...@bwidawsk.net wrote:
CC: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
This series is the second revison of:
http://lists.freedesktop.org/archives/intel-gfx/2012-September/020457.html
It changes the way 3d modes are exposed to user-space:
- An expose 3D modes property can be installed on connectors that support
stereo 3D
- User space can indicate through that
From: Damien Lespiau damien.lesp...@intel.com
The expose 3D modes property can be attached to connectors to allow
user space to indicate it can deal with 3D modes and that the drm driver
should expose those 3D modes.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
From: Damien Lespiau damien.lesp...@intel.com
When scanning out a 3D framebuffer, send the corresponding infoframe to
the HDMI sink.
See http://www.hdmi.org/manufacturer/specification.aspx for details.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h
From: Damien Lespiau damien.lesp...@intel.com
For now, let's just look at the 3D_present flag of the CEA HDMI vendor
block to detect if the sink supports a small list of then mandatory 3D
formats.
See the HDMI 1.4a 3D extraction for detail:
http://www.hdmi.org/manufacturer/specification.aspx
From: Damien Lespiau damien.lesp...@intel.com
When dumping the details of a mode, let's add the 3D formats the mode
supports.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/drmtest.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/lib/drmtest.c
This was meant to be the purpose of the
intel_crtc_wait_for_pending_flips() function which is called whilst
preparing the CRTC for a modeset or before disabling. However, as Ville
Syrjala pointed out, we set the pending flip notification on the old
framebuffer that is no longer attached to the
On Fri, Sep 28, 2012 at 4:05 AM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Wed, 26 Sep 2012 10:34:01 -0700
Ben Widawsky b...@bwidawsk.net wrote:
BIOS should be setting the minimum voltage for rc6 to be 450mV. Old or
buggy BIOSen may not be doing this, so we correct it for them. Ideally
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