Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly
different page table entry formats. Rather than polluting one function
with generation checks, simply use a function pointer and set up the
correct PTE encoding function at startup.
v2: Move the gen6_gtt_pte_t typedef to i915_drv.h
On Bay Trail, bit 1 means writeable by the GPU. Failing to set that
means basically anything using the GPU will cause hangs.
v2: Drop accidental inline keyword on byt_pte_encode.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jani Nikula jani.nik...@intel.com [v1]
Tested-by:
Now that we have function pointers, it's cleaner to just create a new
per-platform PTE encoding function.
This should be identical in behavior to the previous code.
v2: Drop accidental inline keyword on hsw_pte_encode.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Jani
On the series,
Reviewed-by: Jani Nikula jani.nik...@intel.com
On Mon, 22 Apr 2013, Kenneth Graunke kenn...@whitecape.org wrote:
Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly
different page table entry formats. Rather than polluting one function
with generation checks,
On Fri, 19 Apr 2013, Jesse Barnes jbar...@virtuousgeek.org wrote:
We already enable dithering above if needed, and we definitely shouldn't
be enabling the pipe at this point, so just drop this whole block.
This gets rid of the pipe enabled when expected off backtrace I kept
having.
Tested-by:
On Mon, Apr 22, 2013 at 11:13:18AM +0300, Jani Nikula wrote:
On the series,
Reviewed-by: Jani Nikula jani.nik...@intel.com
All merged, thanks for the patchesreview.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
On Fri, Apr 19, 2013 at 11:24:45AM +0200, Daniel Vetter wrote:
This nicely allows us to drop some hacks which have only been used
to work around modeset failures due to lack of fdi lanes.
v2: Implement proper checking for Haswell platforms - the fdi link to
the LPT PCH has only 2 lanes. Note
On Sat, Apr 20, 2013 at 05:19:46PM +0200, Daniel Vetter wrote:
This was somehow lost in the pipe_config-dpll introduction in
commit f47709a9502f3715cc488b788ca91cf0c142b1b1
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Thu Mar 28 10:42:02 2013 +0100
drm/i915: create
On Fri, Apr 19, 2013 at 05:26:27PM +0200, Daniel Vetter wrote:
Automatic color range selection was added in
commit 55bc60db5988c8366751d3d04dd690698a53412c
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Thu Jan 17 16:31:29 2013 +0200
drm/i915: Add Automatic mode for the
On Fri, Apr 19, 2013 at 10:22:45AM -0700, Jesse Barnes wrote:
On VLV, the Punit doesn't automatically drop the GPU to it's minimum
voltage level when entering RC6, so we arm a timer to do it for us from
the RPS interrupt handler. It'll generally only fire when we go idle
(or if for some
On Sun, Apr 21, 2013 at 04:01:19PM -0700, Ben Widawsky wrote:
I consistently forget how to decode the HEAD pointer. If we put it in
the error state, one doesn't need to look in docs to find the relevant
info.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Turn the offset into an address and
Ben Widawsky b...@bwidawsk.net writes:
On Sat, Apr 20, 2013 at 11:43:51AM -0700, Ben Widawsky wrote:
On Thu, Apr 04, 2013 at 06:32:37PM +0300, Mika Kuoppala wrote:
Instead of relying in acthd, track ring seqno progression
to detect if ring has hung.
v2: put hangcheck stuff inside
Those registers are not used, let's not keep them around for no reason.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
Hi Daniel/Paulo,
In order to verify an RFC patch to fix the power well issue, I'm trying to
reproduce it on my Haswell ULT C stepping board, with drm-intel-next branch,
the last commit is:
commit 80ad9206c0d863832bc5f6008c4d1868d1df8e70
Author: Ville Syrjälä ville.syrj...@linux.intel.com
From: Ville Syrjälä ville.syrj...@linux.intel.com
The BIOS uses power of two values for the data/link N value.
Follow suit to make the Zotac DP to dual-HDMI dongle work.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
On Mon, 22 Apr 2013 14:39:17 +0300
Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Fri, Apr 19, 2013 at 10:22:45AM -0700, Jesse Barnes wrote:
On VLV, the Punit doesn't automatically drop the GPU to it's minimum
voltage level when entering RC6, so we arm a timer to do it for us from
Automatic color range selection was added in
commit 55bc60db5988c8366751d3d04dd690698a53412c
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Thu Jan 17 16:31:29 2013 +0200
drm/i915: Add Automatic mode for the Broadcast RGB property
but that removed the check to avoid a full
Automatic color range selection was added in
commit 55bc60db5988c8366751d3d04dd690698a53412c
Author: Ville Syrjälä ville.syrj...@linux.intel.com
Date: Thu Jan 17 16:31:29 2013 +0200
drm/i915: Add Automatic mode for the Broadcast RGB property
but that removed the check to avoid a full
On Mon, Apr 22, 2013 at 02:13:44PM +0300, Ville Syrjälä wrote:
On Sat, Apr 20, 2013 at 05:19:46PM +0200, Daniel Vetter wrote:
This was somehow lost in the pipe_config-dpll introduction in
commit f47709a9502f3715cc488b788ca91cf0c142b1b1
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date:
This nicely allows us to drop some hacks which have only been used
to work around modeset failures due to lack of fdi lanes.
v2: Implement proper checking for Haswell platforms - the fdi link to
the LPT PCH has only 2 lanes. Note that we already filter out
impossible modes in
On Mon, Apr 22, 2013 at 02:16:34PM +0100, Chris Wilson wrote:
On Sun, Apr 21, 2013 at 04:01:19PM -0700, Ben Widawsky wrote:
I consistently forget how to decode the HEAD pointer. If we put it in
the error state, one doesn't need to look in docs to find the relevant
info.
Signed-off-by:
On Mon, Apr 22, 2013 at 05:23:50PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The BIOS uses power of two values for the data/link N value.
Follow suit to make the Zotac DP to dual-HDMI dongle work.
Bugzilla:
On Mon, Apr 22, 2013 at 05:23:50PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The BIOS uses power of two values for the data/link N value.
Follow suit to make the Zotac DP to dual-HDMI dongle work.
Bugzilla:
On Mon, Apr 22, 2013 at 05:17:41PM +0200, Daniel Vetter wrote:
On Mon, Apr 22, 2013 at 02:16:34PM +0100, Chris Wilson wrote:
On Sun, Apr 21, 2013 at 04:01:19PM -0700, Ben Widawsky wrote:
I consistently forget how to decode the HEAD pointer. If we put it in
the error state, one doesn't
On Mon, Apr 22, 2013 at 05:23:50PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The BIOS uses power of two values for the data/link N value.
Follow suit to make the Zotac DP to dual-HDMI dongle work.
Bugzilla:
Hi,
We had a few places (3) to update every time we wanted to add a device info
flag, somewhat error prone. With this series we just need to touch
DEV_INFO_FOR_EACH_FLAG() to add a flag (patches 1-3).
On top of that, I add two more flags, has_ddi (patch 4) and has_fpga_dbg
(patches 5/6), flags
DEV_INFO_FOR_FLAG() now takes 2 parameters:
• A function to apply to the flag
• A separator
This will allow us to use the macro twice in the DRM_DEBUG_DRIVER() call
of i915_dump_device_info().
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c |
This way, when adding a device flag we don't have to manually maintain
that list.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 31 +++
1 file changed, 7 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 725d53d..4239263 100644
---
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895..564d4c6
Let's introduce one more of those orthogonal feature macros. This should
hopefully make the code more readable and make things easier for new platform
enabling.
This time, HAS_FPGA_DBG_UNCLAIMED() is true for platforms that have bit
31 of FPGA_DBG able to signal unclaimed writes.
Signed-off-by:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 896b904..624cdfc
On VLV, the Punit doesn't automatically drop the GPU to it's minimum
voltage level when entering RC6, so we arm a timer to do it for us from
the RPS interrupt handler. It'll generally only fire when we go idle
(or if for some reason there's a long delay between RPS interrupts), but
won't be
On Mon, Apr 22, 2013 at 7:54 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2557926..4669d8c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2545,6 +2545,9 @@ static
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
tools/intel_error_decode.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index 96aaf72..d2e91e7 100644
--- a/tools/intel_error_decode.c
+++
Show the decoded HEAD value, as well as print the calculated head offset
per ringbuffer.
This will be superceded in the next commit, but I think more info is
better.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
tools/intel_error_decode.c | 22 --
1 file changed, 20
The rest of igt has moved to kernel coding style. People had already
been not conforming with the existing formatting in error decode, so we
may as well fix it.
This addresses two primary issues, tabbing (remove spaces), and space
after function in function call. I may have missed some of the
Easy to do with the stuff in place before this.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
tools/intel_error_decode.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index e29ee1e..96aaf72
On Mon, Apr 22, 2013 at 12:00:57PM -0700, Ben Widawsky wrote:
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Fold this into the earlier patch.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
On Mon, Apr 22, 2013 at 12:00:55PM -0700, Ben Widawsky wrote:
Show the decoded HEAD value, as well as print the calculated head offset
per ringbuffer.
Give us an example!
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx
On Mon, Apr 22, 2013 at 12:00:56PM -0700, Ben Widawsky wrote:
Easy to do with the stuff in place before this.
This looks like it will make me happier, thanks.
With just a couple of minor changes,
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
-Chris
--
Chris Wilson, Intel Open Source
On Mon, Apr 22, 2013 at 12:00:56PM -0700, Ben Widawsky wrote:
Easy to do with the stuff in place before this.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
My assumptions on ordering of the error dump were incorrect. Ie. this
patch is no good. Working on a fix when I have some time.
[snip]
Ouch good catch. I'll put the cancelation outside the scope of the lock.
--
Jesse Barnes, Intel Open Source Technology Center
Original message
From: Daniel Vetter dan...@ffwll.ch
Date: 04/22/2013 11:52 AM (GMT-08:00)
To: Jesse Barnes jbar...@virtuousgeek.org
Cc:
We need to hold the rps lock around punit access.
Reported-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_debugfs.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
On VLV, the Punit doesn't automatically drop the GPU to it's minimum
voltage level when entering RC6, so we arm a timer to do it for us from
the RPS interrupt handler. It'll generally only fire when we go idle
(or if for some reason there's a long delay between RPS interrupts), but
won't be
Show the decoded HEAD value, as well as print the calculated head offset
per ringbuffer.
This will be superceded in the next commit, but that patch is way more
complicated than this one (read: error prone), so I want this here.
Example:
ringbuffer (blitter ring) at 0x00044000; HEAD points to:
This patch is an enormous mess, and I'd be fine if people didn't want
it. However I have made the code do what we want at least on the two
error dumps I've tried.
The way that it works is it attempts to identify which ACTHD belongs to
the ring, or batch, and add the appropriate offset as
The rest of igt has moved to kernel coding style. People had already
been not conforming with the existing formatting in error decode, so we
may as well fix it.
This addresses two primary issues, tabbing (remove spaces), and space
after function in function call. I may have missed some of the
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