Display HDA need reqeust power well in case it's shut down by gfx.
Currently hda is the only user in audio side, even though the codecs
depends on same power well too, it's safe to share the same power well
with hda controller. If gfx power well could shut down only for codecs,
it can be added as
hda_i915 has dependency on i915 module, this patch check whether
symbol exist before calling API there. If i915 module not loaded it
will try to load before use.
Signed-off-by: Wang Xingchao xingchao.w...@linux.intel.com
---
sound/pci/hda/hda_i915.c | 42
I915 module maybe loaded after snd_hda_intel, the power-well
API doesnot exist in such case. This patch intended to avoid
loading dependency between snd-hda-intel and i915 module.
Signed-off-by: Wang Xingchao xingchao.w...@linux.intel.com
---
drivers/gpu/drm/i915/i915_dma.c |3 ++
On 05/13/2013 09:37 AM, Wang Xingchao wrote:
I915 module maybe loaded after snd_hda_intel, the power-well
API doesnot exist in such case. This patch intended to avoid
loading dependency between snd-hda-intel and i915 module.
Hi Xingchao and thanks for working on this.
This patch seems to
Hi David,
-Original Message-
From: alsa-devel-boun...@alsa-project.org
[mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of David Henningsson
Sent: Monday, May 13, 2013 4:29 PM
To: Wang Xingchao
Cc: alsa-de...@alsa-project.org; dan...@ffwll.ch; ti...@suse.de; Lin,
Mengdong;
Hi Jaroslav,
-Original Message-
From: alsa-devel-boun...@alsa-project.org
[mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of Jaroslav Kysela
Sent: Monday, May 13, 2013 4:56 PM
To: David Henningsson
Cc: alsa-de...@alsa-project.org; Girdwood, Liam R; ti...@suse.de; Lin,
On 05/13/2013 01:55 PM, Wang, Xingchao wrote:
Hi David,
-Original Message-
From: alsa-devel-boun...@alsa-project.org
[mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of David Henningsson
Sent: Monday, May 13, 2013 4:29 PM
To: Wang Xingchao
Cc: alsa-de...@alsa-project.org;
At Mon, 13 May 2013 11:55:14 +,
Wang, Xingchao wrote:
Hi David,
-Original Message-
From: alsa-devel-boun...@alsa-project.org
[mailto:alsa-devel-boun...@alsa-project.org] On Behalf Of David Henningsson
Sent: Monday, May 13, 2013 4:29 PM
To: Wang Xingchao
Cc:
At Mon, 13 May 2013 15:37:28 +0800,
Wang Xingchao wrote:
I915 module maybe loaded after snd_hda_intel, the power-well
API doesnot exist in such case. This patch intended to avoid
loading dependency between snd-hda-intel and i915 module.
Signed-off-by: Wang Xingchao
Chris Wilson ch...@chris-wilson.co.uk writes:
There is an unlikely corner case whereby a lockless wait may not notice
a GPU hang and reset, and so continue to wait for the device to advance
beyond the chosen seqno. This of course may never happen as the waiter
may be the only user. Instead,
Keep track of ring seqno progress and if there are no
progress detected, declare hang. Use actual head (acthd)
to distinguish between ring stuck and batchbuffer looping
situation. Stuck ring will be kicked to trigger progress.
v2: use atchd to detect stuck ring from loop (Ben Widawsky)
v3: Use
In preparation for next commit, pass seqno as a parameter
to i915_hangcheck_ring_idle as it will be used inside
i915_hangcheck_elapsed.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
Rework of per ring hangcheck made this obsolete.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_irq.c | 21 -
2 files changed, 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
In preparation to track per ring progress in hangcheck,
add i915_hangcheck_ring_hung.
v2: omit dev parameter (Ben Widawsky)
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 29 +
1 file changed, 17 insertions(+), 12
Instead of relying in acthd, track ring seqno progression
to detect if ring has hung.
v2: put hangcheck stuff inside struct (Chris Wilson)
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 --
drivers/gpu/drm/i915/i915_irq.c | 30
From: Paulo Zanoni paulo.r.zan...@intel.com
Intermediate Pixel Storage is a feature that should reduce the number
of times the display engine wakes up memory to read pixels, so it
should allow deeper PC states. IPS can only be enabled on ULT port A
with 8:8:8 pipe pixel formats.
With eDP
From: Paulo Zanoni paulo.r.zan...@intel.com
IPS is still enabled by default. Feature requested by the power
management team.
This should also help testing the feature on some early pre-production
hardware where there were relationship problems between IPS and PSR.
Requested-by: Kristen Accardi
From: Paulo Zanoni paulo.r.zan...@intel.com
It just prints whether it's supported/enabled/disabled. Feature
requested by the power management team.
Requested-by: Kristen Accardi kristen.c.acca...@intel.com
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
This patch also fix GT3 names. I'no not sending in separated patche because
names are only in few comments and not in variable names.
References:
When publishing first HSW ids we weren't allowed to use GT3 codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by:
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
intel/intel_chipset.h | 54
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
src/mesa/drivers/dri/intel/intel_chipset.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h
b/src/mesa/drivers/dri/intel/intel_chipset.h
index df025ac..ee735bb 100644
---
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
include/pci_ids/i965_pci_ids.h
As Chris mentioned there is a tendency we finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
I didn't have better names for this reserved ids and didn't want to use rsvd1
and rsvd2 groups, so I decided to use B and E that stands for the latest
id digit.
On Mon, May 13, 2013 at 05:56:29PM -0300, Rodrigo Vivi wrote:
When publishing first HSW ids we weren't allowed to use GT3 codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's
good question. I'm going to check that.
Please accept this add reserved ids patch for now. I send more
patches above this with market names if I find out the correct
association.
On Mon, May 13, 2013 at 6:39 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Mon, May 13, 2013 at 05:56:29PM
On 05/13/2013 01:53 PM, Rodrigo Vivi wrote:
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
References: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi
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