Hi,
I want to take this problem up again, because it's important we get this
right.
The HDA driver assumes that a codec pin widget node always refers to the
same physical output. With Haswell, it seems like this is not guaranteed
to be true. I would like to see this fixed on the graphics
Hi all,
This is V3 and some fixes after Takashi's review.
change between V2--V3:
- make SND_HDA_I915 selectable
- use snd_printdd to output message
- add return error code check
- use symbol_request to replace symbol_get
- release power_well at azx_free
- some typo fixes
Haswell Display audio depends on power well in graphic side, it should
request power well before use it and release power well after use.
I915 will not shutdown power well if it detects audio is using.
This patch protects display audio crash for Intel Haswell C3 stepping board.
Signed-off-by:
For Intel Haswell chip, HDA controller and codec have
power well dependency from GPU side. This patch added support
to request/release power well in audio driver. Power save
feature should be enabled to get runtime power saving.
Signed-off-by: Wang Xingchao xingchao.w...@linux.intel.com
---
This patch add dvo detection for the Chrontel 7010B on some old hardware.
References: https://bugzilla.kernel.org/show_bug.cgi?id=55101
Signed-off-by: Braggle braggle at free.fr
---
drivers/gpu/drm/i915/dvo_ch7xxx.c | 28 ++--
drivers/gpu/drm/i915/intel_dvo.c |7
is_cpu_edp() is equivalent with a port==PORT_A check. There are two
exceptions (see patch 1 and 2), where we can rewrite things to handle
ValleyView separately as it's done at other places. With these out of
the way we can replace is_cpu_edp() with a simpler port check and
remove is_cpu_edp().
I
On port A and for Valleyview on port C we can have only eDP and in both
cases it's a CPU port. So we can replace is_cpu_edp() with a port check
for these two cases. This allows us to remove is_cpu_edp() completely in
a later patch.
Signed-off-by: Imre Deak imre.d...@intel.com
---
On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we
can calculate for both the clock divider for the 2MHz target rate at the
same place. Afterwards we can also replace the is_cpu_edp() check with a
check for port A.
Signed-off-by: Imre Deak imre.d...@intel.com
---
The patch changes all remaining is_cpu_edp() check with a check for port
A. We can do this, since in all these cases ValleyView is handled
separately and port A is always a CPU side eDP port.
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 49
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1a4c103..0d326e2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++
Hi Daniel,
Do you have further comments on this patchset?
thanks
--xingchao
-Original Message-
From: Wang Xingchao [mailto:xingchao.w...@linux.intel.com]
Sent: Thursday, May 16, 2013 3:53 PM
To: ti...@suse.de; dan...@ffwll.ch; Girdwood, Liam R
Cc: david.hennings...@canonical.com;
On Wed, May 15, 2013 at 4:42 PM, Ben Guthro b...@guthro.net wrote:
On Tue, May 14, 2013 at 5:01 PM, Ben Guthro b...@guthro.net wrote:
I am attempting to debug an issue with some Haswell laptop systems
which do not restore their screen after resuming from S3 when running
on the stable 3.8
From: Paulo Zanoni paulo.r.zan...@intel.com
Intermediate Pixel Storage is a feature that should reduce the number
of times the display engine wakes up memory to read pixels, so it
should allow deeper PC states. IPS can only be enabled on ULT pipe A
with 8:8:8 pipe pixel formats.
With eDP
From: Paulo Zanoni paulo.r.zan...@intel.com
IPS is still enabled by default. Feature requested by the power
management team.
This should also help testing the feature on some early pre-production
hardware where there were relationship problems between IPS and PSR.
v2: Rebase on top of the
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