Here is a system for example:
Pentium M processor with 32bits address pins,
Intel 440FX chip,
A PCI device with 32bits address pins.
See the ascii picture below.
Assume that the pci device BAR0 is in memory space, 10Mb in size.
After initialization, BAR0 is assigned an address. I don't
Haswell Display audio depends on power well in graphic side, it should
request power well before use it and release power well after use.
I915 will not shutdown power well if it detects audio is using.
This patch protects display audio crash for Intel Haswell C3 stepping board.
Signed-off-by:
Hi Jesse,
-Original Message-
From: Barnes, Jesse
Sent: Friday, May 17, 2013 11:44 PM
To: Wang Xingchao
Cc: ti...@suse.de; dan...@ffwll.ch; Girdwood, Liam R;
david.hennings...@canonical.com; Lin, Mengdong; Li, Jocelyn;
alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.org;
On Fri, May 03, 2013 at 05:23:45PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
inside haswell_init_clock_gating and mentioned it is a workaround for
early silicon revisions and should be removed
On Fri, May 03, 2013 at 05:23:44PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the New WM0 at 63:56, so the Old WM0 could maybe be zero if
the new one is not zero.
Signed-off-by: Paulo
On Fri, May 03, 2013 at 05:23:37PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
So don't call intel_update_linetime_watermarks from
ironlake_crtc_mode_set. Only Haswell has these watermarks.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Reviewed-by: Ville
On Fri, May 03, 2013 at 05:23:39PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
... instead of mode-crtc_display. The spec says pipe horizontal
total number of pixels and the Haswell Watermark Calculator tool
uses the Pipe H Total instead of Pipe H Src as the value.
On Thu, May 09, 2013 at 04:55:50PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
The spec says the linetime watermarks must be programmed before
enabling any display low power watermarks, but we're currently
updating the linetime watermarks after we call
On Fri, May 03, 2013 at 05:23:40PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Move the *8 calculation to the left side so we don't propagate
rounding errors. Also use DIV_ROUND_CLOSEST because that's what the
spec says we need to do.
Signed-off-by: Paulo
On Fri, May 03, 2013 at 05:23:41PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we're using DP/eDP, adjusted_mode-clock may be just the port link
clock, but we also can't use mode-clock because it's wrong when we're
using the using panel fitter.
Signed-off-by:
On Fri, May 03, 2013 at 05:23:43PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Remove the placeholder comment and set the actual value described by
the specification. We still don't enable IPS, but it won't hurt to
already have the value set here.
While at it,
On Fri, May 03, 2013 at 05:23:42PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
With this, that 338 can finally become the correct 337500.
Due to the change we need to adjust the intel_dp_aux_ch function to
set the correct value, so adjust the division and also
Hi all,
New testing round with a bit fewer patches since I've been travelling
last week. Usual pace should pick up again ;-) Highlights:
- fbc support for Haswell (Rodrigo)
- streamlined workaround comments, including an igt tool to grep for
them (Damien)
- sdvo and TV out cleanups, including a
On Fri, 3 May 2013 19:44:07 +0200
Egbert Eich e...@suse.de wrote:
From: Imre Deak imre.d...@intel.com
Currently the driver's assumed behavior for a modeset with an attached
FB is that the corresponding connector will be switched to DPMS ON mode
if it happened to be in DPMS OFF (or another
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/intel_dp.c between commit 657445fe8660 (Revert
drm/i915: revert eDP bpp clamping code changes) from Linus' tree and
commits c6bb353815c3 (drm/i915: move dp clock computations to
encoder-compute_config),
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