At Thu, 23 May 2013 01:04:15 +0800,
Wang Xingchao wrote:
The device can support runtime PM no matter whether
it support signal wakeup or not. For some chips like Haswell
which doesnot support PME by default, this patch let haswell
Display HD-A controller enter runtime suspend, and bring more
On Wed, May 22, 2013 at 11:07:09PM +0200, Thomas Meyer wrote:
Signed-off-by: Thomas Meyer tho...@m3y3r.de
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
At Thu, 23 May 2013 01:04:16 +0800,
Wang Xingchao wrote:
There's deadlock when request_module(i915) in azx_probe.
It looks like:
device_lock(audio pci device) - azx_probe - module_request
(or symbol_request) - modprobe (userspace) - i915 init -
drm_pci_init - pci_register_driver -
At Thu, 23 May 2013 09:51:07 +0800,
Wang Xingchao wrote:
There's deadlock when request_module(i915) in azx_probe.
It looks like:
device_lock(audio pci device) - azx_probe - module_request
(or symbol_request) - modprobe (userspace) - i915 init -
drm_pci_init - pci_register_driver -
Hi Takashi,
-Original Message-
From: Takashi Iwai [mailto:ti...@suse.de]
Sent: Thursday, May 23, 2013 2:03 PM
To: Wang Xingchao
Cc: dan...@ffwll.ch; alsa-de...@alsa-project.org;
intel-gfx@lists.freedesktop.org; david.hennings...@canonical.com; Girdwood,
Liam R; Li, Jocelyn; Wang,
At Thu, 23 May 2013 07:53:00 +,
Wang, Xingchao wrote:
Hi Takashi,
-Original Message-
From: Takashi Iwai [mailto:ti...@suse.de]
Sent: Thursday, May 23, 2013 2:03 PM
To: Wang Xingchao
Cc: dan...@ffwll.ch; alsa-de...@alsa-project.org;
intel-gfx@lists.freedesktop.org;
On Wed, May 22, 2013 at 02:23:17PM -0300, Rodrigo Vivi wrote:
According BSPec: Workaround: Do not enable Render Command Streamer tracking
for FBC.
Instead insert a LRI to address 0x50380 with data 0x0004 after the
PIPE_CONTROL that
follows each render submission.
v2: Chris noticed
On Wed, May 08, 2013 at 05:16:45PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The 'struct' keyword was missing so struct drm_rect documentation never
ended up in the generated docs.
Also move the drm_rect documentations to a new section
Hi Takashi,
-Original Message-
From: Takashi Iwai [mailto:ti...@suse.de]
Sent: Thursday, May 23, 2013 2:49 PM
To: Wang Xingchao
Cc: alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.org;
david.hennings...@canonical.com; Girdwood, Liam R; Li, Jocelyn; Wang,
Xingchao; Lin,
-Original Message-
From: Takashi Iwai [mailto:ti...@suse.de]
Sent: Thursday, May 23, 2013 4:10 PM
To: Wang, Xingchao
Cc: dan...@ffwll.ch; alsa-de...@alsa-project.org;
intel-gfx@lists.freedesktop.org; david.hennings...@canonical.com; Girdwood,
Liam R; Li, Jocelyn; Wang Xingchao
At Thu, 23 May 2013 10:19:27 +,
Wang, Xingchao wrote:
Hi Takashi,
-Original Message-
From: Takashi Iwai [mailto:ti...@suse.de]
Sent: Thursday, May 23, 2013 2:49 PM
To: Wang Xingchao
Cc: alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.org;
On Wed, May 22, 2013 at 02:23:17PM -0300, Rodrigo Vivi wrote:
According BSPec: Workaround: Do not enable Render Command Streamer tracking
for FBC.
Instead insert a LRI to address 0x50380 with data 0x0004 after the
PIPE_CONTROL that
follows each render submission.
v2: Chris noticed
-Original Message-
From: Takashi Iwai [mailto:ti...@suse.de]
Sent: Thursday, May 23, 2013 6:27 PM
To: Wang, Xingchao
Cc: Wang Xingchao; alsa-de...@alsa-project.org;
intel-gfx@lists.freedesktop.org; david.hennings...@canonical.com; Girdwood,
Liam R; Li, Jocelyn; Lin, Mengdong
This is required for tracking render damage for use with FBC and will be
used in subsequent patches.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
I was thinking more along the lines of this patch for adding the flag
for when to flush. Then use
gen7_ring_fbc_flush() {
if
Imre Deak imre.d...@intel.com writes:
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f5addac..b311ccd 100644
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sadly the FBC_RT_BASE register is part of the hardware context. A
context switch can therefore restore a stale value to the register.
To fix things up, always add an LRI after MI_SET_CONTEXT to update
the register value.
There's still a problem
On Tue, 2013-05-21 at 13:29 +0300, Imre Deak wrote:
On Tue, 2013-05-21 at 11:15 +0200, Daniel Vetter wrote:
On Thu, May 16, 2013 at 02:40:34PM +0300, Imre Deak wrote:
On port A and for Valleyview on port C we can have only eDP and in both
cases it's a CPU port. So we can replace
On Tue, 2013-05-21 at 13:59 +0300, Imre Deak wrote:
On Tue, 2013-05-21 at 12:42 +0200, Daniel Vetter wrote:
On Tue, May 21, 2013 at 12:36 PM, Imre Deak imre.d...@intel.com wrote:
On Tue, 2013-05-21 at 11:12 +0200, Daniel Vetter wrote:
On Thu, May 16, 2013 at 02:40:35PM +0300, Imre Deak
At Thu, 23 May 2013 01:04:13 +0800,
Wang Xingchao wrote:
Haswell Display audio depends on power well in graphic side, it should
request power well before use it and release power well after use.
I915 will not shutdown power well if it detects audio is using.
This patch protects display audio
On Tue, May 14, 2013 at 05:08:27PM -0700, Jesse Barnes wrote:
We need this for comparing modes between configuration changes.
v2: try harder to calulate non-simple pixel clocks (Daniel)
call get_clock after getting the encoder config, needed for pixel multiply
(Jesse)
v3: drop
Signed-off-by: Thomas Meyer tho...@m3y3r.de
---
diff -u -p a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2282,11 +2282,10 @@ intel_dp_get_edid(struct drm_connector *
On Wed, 22 May 2013 15:36:20 +0300
Jani Nikula jani.nik...@intel.com wrote:
We never check the return values, and there's not much we could do on
errors anyway. Just simplify the signatures. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
On Wed, 22 May 2013 15:36:18 +0300
Jani Nikula jani.nik...@intel.com wrote:
The lower level sideband read/write functions already do this.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c |6 --
drivers/gpu/drm/i915/intel_hdmi.c |4
On Wed, 22 May 2013 15:36:19 +0300
Jani Nikula jani.nik...@intel.com wrote:
Rename all VLV IOSF sideband register accessor functions to
vlv_port_{read,write}. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 24
On Thu, May 23, 2013 at 6:10 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
- For the clock readout code I think we should be able to have pipe config
compare support (with adjusted_mode-clock), with a bit of fuzz at
least. Not on current dinq, but with my cleanup to give
Hi Haihao and rest of the list,
I've noticed that the g45 branch seems pretty dead and hasn't been synced
with the main tree since October 2012.
Are there any plans to continue further work in this branch and integrate
this into the main one? From my experiments, it seems that 720p plays well,
On Thu, May 23, 2013 at 11:06:46AM -0700, Jesse Barnes wrote:
On Wed, 22 May 2013 15:36:20 +0300
Jani Nikula jani.nik...@intel.com wrote:
We never check the return values, and there's not much we could do on
errors anyway. Just simplify the signatures. No functional changes.
From: Paulo Zanoni paulo.r.zan...@intel.com
Intermediate Pixel Storage is a feature that should reduce the number
of times the display engine wakes up memory to read pixels, so it
should allow deeper PC states. IPS can only be enabled on ULT pipe A
with 8:8:8 pipe pixel formats.
With eDP
On Thu, May 23, 2013 at 01:57:17PM +0100, Chris Wilson wrote:
If none of the CRTC parameters change along with the framebuffer, we can
forgo rewriting the register and waiting for a vblank. There are a few
calls made by the display managers as they start up which tend to end up
performing
From: Paulo Zanoni paulo.r.zan...@intel.com
But only the first 2048 lines will be compressed. No problem.
With this I can finally see FBC on my 2560x1440 DP monitor, which
gives me a boost on the PC7 residency.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
On Thu, May 23, 2013 at 11:30 PM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
But only the first 2048 lines will be compressed. No problem.
With this I can finally see FBC on my 2560x1440 DP monitor, which
gives me a boost on the PC7 residency.
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