Re: [Intel-gfx] [PULL] drm-intel-next

2014-05-07 Thread Jani Nikula
On Tue, 06 May 2014, Daniel Vetter dan...@ffwll.ch wrote: On Tue, May 06, 2014 at 10:04:17PM +0200, Knut Petersen wrote: On 06.05.2014 20:59, Daniel Vetter wrote: On Tue, May 06, 2014 at 04:30:45PM +0300, Jani Nikula wrote: On Tue, 06 May 2014, Knut Petersen knut_peter...@t-online.de wrote:

Re: [Intel-gfx] [PATCH] drm/i915/SDVO: For sysfs link put directory and target in correct order

2014-05-07 Thread Jani Nikula
On Tue, 15 Apr 2014, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Apr 11, 2014 at 08:26:25PM +0300, Imre Deak wrote: On Fri, 2014-04-11 at 19:07 +0200, Egbert Eich wrote: When linking the i2c sysfs file into the connector's directory pass directory and link target in the right order. This

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Extract node allocation from bind

2014-05-07 Thread Chris Wilson
On Tue, May 06, 2014 at 10:21:31PM -0700, Ben Widawsky wrote: The DRM node allocation code was already a bit of an ugly bit of code within a complex function. Removing it serves the purpose of cleaning the function up. More importantly, it provides a way to have a preallocated (address space)

Re: [Intel-gfx] [RFC] drm/i915: Scratch page optimization for blanking buffer

2014-05-07 Thread Daniel Vetter
On Wed, May 07, 2014 at 11:19:57AM +0530, Akash Goel wrote: On Mon, 2014-05-05 at 16:07 +0200, Daniel Vetter wrote: On Mon, May 05, 2014 at 05:13:18PM +0530, akash.g...@intel.com wrote: From: Akash Goel akash.g...@intel.com There is a use case, when user space (display compositor)

Re: [Intel-gfx] [PATCH] drm/i915/bdw: Only use 2g GGTT for 32b platforms

2014-05-07 Thread Daniel Vetter
On Tue, May 06, 2014 at 09:58:59PM -0700, Ben Widawsky wrote: From: Ben Widawsky benjamin.widaw...@linux.intel.com Daniel requested in the bug that I use a 3GB fallback size. Since this is not in the spec as a valid size, I decided against it. We could potentially add a patch to bump it to

Re: [Intel-gfx] [PATCH 1/9] drm/i915: Use topdown allocation for PPGTT PDEs on gen6/7

2014-05-07 Thread Daniel Vetter
On Tue, May 06, 2014 at 10:21:30PM -0700, Ben Widawsky wrote: It was always the intention to do the topdown allocation for context objects (Chris' idea originally). Unfortunately, I never managed to land the patch, but someone else did, so now we can use it. As a reminder, hardware contexts

Re: [Intel-gfx] [PATCH 4/9] drm/i915: Limit the number of node allocation retries

2014-05-07 Thread Daniel Vetter
On Tue, May 06, 2014 at 10:21:33PM -0700, Ben Widawsky wrote: AFAICT, it's impossible to actually infinitely retry the allocation in our current code. However, a small oversight on my part, slight bug, or future bug, could easily change that. To avoid a potential breakage, a simple retry

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Wrap VMA binding

2014-05-07 Thread Daniel Vetter
On Tue, May 06, 2014 at 10:21:35PM -0700, Ben Widawsky wrote: This will be useful for some upcoming patches which do more platform specific work. Having it in one central place just makes things a bit cleaner and easier. There is a small functional change here. There are more calls to the

Re: [Intel-gfx] [PATCH 7/9] drm/i915: Make aliasing a 2nd class VM

2014-05-07 Thread Daniel Vetter
On Tue, May 06, 2014 at 10:21:36PM -0700, Ben Widawsky wrote: There is a good debate to be had about how best to fit the aliasing PPGTT into the code. However, as it stands right now, getting aliasing PPGTT bindings is a hack, and done through implicit arguments. To make this absolutely clear,

Re: [Intel-gfx] [PATCH 9/9] drm/i915: Split out aliasing binds

2014-05-07 Thread Daniel Vetter
On Tue, May 06, 2014 at 10:21:38PM -0700, Ben Widawsky wrote: This patch finishes off actually separating the aliasing and global finds. Prior to this, all global binds would be aliased. Now if aliasing binds are required, they must be explicitly asked for. So far, we have no users of this

Re: [Intel-gfx] [RFC] drm/i915 : Reduce the shmem page allocation time by using blitter engines for clearing pages.

2014-05-07 Thread Gupta, Sourab
On Tue, 2014-05-06 at 13:12 +, Chris Wilson wrote: On Tue, May 06, 2014 at 12:59:37PM +, Gupta, Sourab wrote: On Tue, 2014-05-06 at 11:34 +, Chris Wilson wrote: On Tue, May 06, 2014 at 04:40:58PM +0530, sourab.gu...@intel.com wrote: From: Sourab Gupta sourab.gu...@intel.com

Re: [Intel-gfx] [RFC] drm/i915 : Reduce the shmem page allocation time by using blitter engines for clearing pages.

2014-05-07 Thread Gupta, Sourab
On Tue, 2014-05-06 at 17:56 +, Eric Anholt wrote: sourab.gu...@intel.com writes: From: Sourab Gupta sourab.gu...@intel.com This patch is in continuation of and is dependent on earlier patch series to 'reduce the time for which device mutex is kept locked'.

Re: [Intel-gfx] [RFC] libdrm_intel: Add support for userptr objects

2014-05-07 Thread Tvrtko Ursulin
On 05/02/2014 06:15 PM, Ben Widawsky wrote: On Fri, May 02, 2014 at 11:27:45AM +0100, Tvrtko Ursulin wrote: Some people expressed interest in tiling so I thought to preserve it in the API. Kernel even allows it, and it is just because Chris found bspec references saying it will break badly on

Re: [Intel-gfx] [RFC] drm/i915: Scratch page optimization for blanking buffer

2014-05-07 Thread Daniel Vetter
On Wed, May 7, 2014 at 9:39 AM, Daniel Vetter dan...@ffwll.ch wrote: Yes no real backing storage is needed, but still the object should be allowed to get mapped into the GGTT, using the scratch page (already zeroed out). Is there a patch for a new drm/i915 ioctl similar to fallocate, which

Re: [Intel-gfx] [PATCH 1/2] rendercopy/bdw: Enable hw-generated binding tables

2014-05-07 Thread Ville Syrjälä
I quickly cobbled together a hsw version of this and gave it a whirl on one machine. Seems to work just fine here, and no lockups when switching between hw and sw binding tables. Did you get the lockups on hsw even with rendercopy? Here's my hsw version: From

Re: [Intel-gfx] [PATCH 1/2] rendercopy/bdw: Enable hw-generated binding tables

2014-05-07 Thread Chris Wilson
On Wed, May 07, 2014 at 02:49:31PM +0300, Ville Syrjälä wrote: I quickly cobbled together a hsw version of this and gave it a whirl on one machine. Seems to work just fine here, and no lockups when switching between hw and sw binding tables. Did you get the lockups on hsw even with rendercopy?

Re: [Intel-gfx] [PATCH 00/66] runtime pm for DPMS

2014-05-07 Thread Imre Deak
On Fri, 2014-04-25 at 10:45 +0200, Daniel Vetter wrote: Ok, review assignements. Please complain if you don't have the bandwidth so that I can find someone else. On Thu, Apr 24, 2014 at 11:54 PM, Daniel Vetter daniel.vet...@ffwll.ch wrote: Daniel Vetter (66): drm/i915: Make

[Intel-gfx] [PATCH] tests/gem_flink_race, prime_self_import: fix object counts

2014-05-07 Thread Mika Kuoppala
We need to add one drm_open_any() before getting the object counts as first call to drm_open_any() allocates file descriptors for exit handlers and thus is not symmetrical Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77867 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77875

Re: [Intel-gfx] [PATCH 01/10] drm/i915/bdw: Implement a basic PM interrupt handler

2014-05-07 Thread Ville Syrjälä
On Mon, May 05, 2014 at 06:17:30PM +0530, deepa...@linux.intel.com wrote: From: Ben Widawsky benjamin.widaw...@intel.com Almost all of it is reusable from the existing code. The primary difference is we need to do even less in the interrupt handler, since interrupts are not shared in the

Re: [Intel-gfx] [PATCH 02/10] drm/i915: Enable PM Interrupts target via Display Interface.

2014-05-07 Thread Ville Syrjälä
On Mon, May 05, 2014 at 06:17:31PM +0530, deepa...@linux.intel.com wrote: From: Deepak S deepa...@linux.intel.com In BDW, Apart from unmasking up/down threshold interrupts. we need to umask bit 32 of PM_INTRMASK to route interrupts to target via Display Interface. v2: Add (131) mask

Re: [Intel-gfx] [PATCH] tests/gem_flink_race, prime_self_import: fix object counts

2014-05-07 Thread Daniel Vetter
On Wed, May 07, 2014 at 04:55:28PM +0300, Mika Kuoppala wrote: We need to add one drm_open_any() before getting the object counts as first call to drm_open_any() allocates file descriptors for exit handlers and thus is not symmetrical Bugzilla:

[Intel-gfx] Design review request: DRM color manager

2014-05-07 Thread Sharma, Shashank
Hello all, As per previous discussions, I am sending the drm-color-manager design for review, as inline text. Please have a look and let me know your feedback. (I tried hard to align the inline text diagram in mail, hope you can see the proper picture too) = DRM Color

Re: [Intel-gfx] [PATCH 10/10] drm/i915/chv: Freq(opcode) request for CHV.

2014-05-07 Thread Ville Syrjälä
On Mon, May 05, 2014 at 06:17:39PM +0530, deepa...@linux.intel.com wrote: From: Deepak S deepa...@linux.intel.com On CHV, All the freq request should be even. So, we need to make sure we request the opcode accordingly. Signed-off-by: Deepak S deepa...@linux.intel.com Reviewed-by: Ben

Re: [Intel-gfx] [PATCH 4/9] drm/i915: Limit the number of node allocation retries

2014-05-07 Thread Ben Widawsky
On Wed, May 07, 2014 at 09:49:57AM +0200, Daniel Vetter wrote: On Tue, May 06, 2014 at 10:21:33PM -0700, Ben Widawsky wrote: AFAICT, it's impossible to actually infinitely retry the allocation in our current code. However, a small oversight on my part, slight bug, or future bug, could

[Intel-gfx] [PATCH] UXA: Wait until a pageflip actually completes to report it.

2014-05-07 Thread Jamey Sharp
UXA was reporting page-flip completion as soon as the flip was scheduled with the kernel, instead of waiting for the kernel to indicate that the flip had actually completed. Moving the DRI2SwapComplete call to the right place fixes all of our Piglit tests for OML_sync_control when run on

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Extract node allocation from bind

2014-05-07 Thread Ben Widawsky
On Wed, May 07, 2014 at 08:02:38AM +0100, Chris Wilson wrote: On Tue, May 06, 2014 at 10:21:31PM -0700, Ben Widawsky wrote: The DRM node allocation code was already a bit of an ugly bit of code within a complex function. Removing it serves the purpose of cleaning the function up. More

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Extract node allocation from bind

2014-05-07 Thread Chris Wilson
On Wed, May 07, 2014 at 08:45:38AM -0700, Ben Widawsky wrote: On Wed, May 07, 2014 at 08:02:38AM +0100, Chris Wilson wrote: On Tue, May 06, 2014 at 10:21:31PM -0700, Ben Widawsky wrote: The DRM node allocation code was already a bit of an ugly bit of code within a complex function.

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Wrap VMA binding

2014-05-07 Thread Ben Widawsky
On Wed, May 07, 2014 at 09:55:49AM +0200, Daniel Vetter wrote: On Tue, May 06, 2014 at 10:21:35PM -0700, Ben Widawsky wrote: This will be useful for some upcoming patches which do more platform specific work. Having it in one central place just makes things a bit cleaner and easier.

Re: [Intel-gfx] [PATCH] UXA: Wait until a pageflip actually completes to report it.

2014-05-07 Thread Chris Wilson
On Mon, May 05, 2014 at 11:05:07PM -0700, Jamey Sharp wrote: UXA was reporting page-flip completion as soon as the flip was scheduled with the kernel, instead of waiting for the kernel to indicate that the flip had actually completed. Moving the DRI2SwapComplete call to the right place fixes

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Wrap VMA binding

2014-05-07 Thread Daniel Vetter
On Wed, May 07, 2014 at 08:54:56AM -0700, Ben Widawsky wrote: On Wed, May 07, 2014 at 09:55:49AM +0200, Daniel Vetter wrote: On Tue, May 06, 2014 at 10:21:35PM -0700, Ben Widawsky wrote: This will be useful for some upcoming patches which do more platform specific work. Having it in one

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Extract node allocation from bind

2014-05-07 Thread Ben Widawsky
On Wed, May 07, 2014 at 04:53:08PM +0100, Chris Wilson wrote: On Wed, May 07, 2014 at 08:45:38AM -0700, Ben Widawsky wrote: On Wed, May 07, 2014 at 08:02:38AM +0100, Chris Wilson wrote: On Tue, May 06, 2014 at 10:21:31PM -0700, Ben Widawsky wrote: The DRM node allocation code was already

Re: [Intel-gfx] [PATCH] drm/i915: Use hash tables for the command parser

2014-05-07 Thread Volkin, Bradley D
Could someone help to review this patch please? It provides a nice improvement to the command parser's performance, so I'd like to get this one in. Thanks, Brad On Mon, Apr 28, 2014 at 08:22:08AM -0700, Volkin, Bradley D wrote: From: Brad Volkin bradley.d.vol...@intel.com For clients that

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Extract node allocation from bind

2014-05-07 Thread Chris Wilson
On Wed, May 07, 2014 at 09:00:16AM -0700, Ben Widawsky wrote: On Wed, May 07, 2014 at 04:53:08PM +0100, Chris Wilson wrote: On Wed, May 07, 2014 at 08:45:38AM -0700, Ben Widawsky wrote: Hmm. I really don't see what's actually upsetting. Can you be a bit more explicit about what's so

[Intel-gfx] [PATCH v2] drm/i915: remove user GTT mappings early during runtime suspend

2014-05-07 Thread Imre Deak
Currently user space can access GEM buffers mapped to GTT through existing mappings concurrently while the platform specific suspend handlers are running. Since these handlers may change the HW state in a way that would break such accesses, remove the mappings before calling the handlers. Spotted

Re: [Intel-gfx] [PATCH 08/13] drm/i915: Implement MI decode for gen8

2014-05-07 Thread Ben Widawsky
On Wed, Apr 30, 2014 at 02:21:15PM +0300, Ville Syrjälä wrote: On Tue, Apr 29, 2014 at 02:52:35PM -0700, Ben Widawsky wrote: From: Ben Widawsky benjamin.widaw...@linux.intel.com This is needed to implement ipehr_is_semaphore_wait Signed-off-by: Ben Widawsky b...@bwidawsk.net ---

Re: [Intel-gfx] [PATCH 08/13] drm/i915: Implement MI decode for gen8

2014-05-07 Thread Ville Syrjälä
On Wed, May 07, 2014 at 09:59:14AM -0700, Ben Widawsky wrote: On Wed, Apr 30, 2014 at 02:21:15PM +0300, Ville Syrjälä wrote: On Tue, Apr 29, 2014 at 02:52:35PM -0700, Ben Widawsky wrote: From: Ben Widawsky benjamin.widaw...@linux.intel.com This is needed to implement

Re: [Intel-gfx] [PATCH v2] drm/i915: remove user GTT mappings early during runtime suspend

2014-05-07 Thread Imre Deak
On Wed, 2014-05-07 at 19:57 +0300, Imre Deak wrote: Currently user space can access GEM buffers mapped to GTT through existing mappings concurrently while the platform specific suspend handlers are running. Since these handlers may change the HW state in a way that would break such accesses,

[Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8

2014-05-07 Thread Ben Widawsky
From: Ben Widawsky benjamin.widaw...@linux.intel.com This is needed to implement ipehr_is_semaphore_wait Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_irq.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH 03/10] drm/i915/bdw: implement semaphore signal

2014-05-07 Thread Ben Widawsky
Semaphore signalling works similarly to previous GENs with the exception that the per ring mailboxes no longer exist. Instead you must define your own space, somewhere in the GTT. The comments in the code define the layout I've opted for, which should be fairly future proof. Ie. I tried to define

[Intel-gfx] [PATCH 06/10] drm/i915: Extract semaphore error collection

2014-05-07 Thread Ben Widawsky
Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/gpu/drm/i915/i915_gpu_error.c | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 2d81985..a7eaab2 100644

[Intel-gfx] [PATCH 09/10] drm/i915/bdw: poll semaphores

2014-05-07 Thread Ben Widawsky
As Ville points out, it's possible/probable we don't actually need this. Potentially, this validates the letter of the spec, and not the spirit. Ville: I discussed this on irc w/ Ben, and I was suggesting we don't need to poll. Polling apparently can be used as a workaround for certain

[Intel-gfx] [PATCH 08/10] drm/i915: semaphore debugfs

2014-05-07 Thread Ben Widawsky
Simple debugfs file to display the current state of semaphores. This is useful if you want to see the state without hanging the GPU. NOTE: This patch is optional to the series. NOTE2: Like the GPU error state collection, the reads are currently incoherent. Signed-off-by: Ben Widawsky

[Intel-gfx] [PATCH 00/10] Semaphores again. Needs shepherd.

2014-05-07 Thread Ben Widawsky
The series is mostly done, but it needs a few last tweaks to make it acceptable for merge. Chris noticed that the series doesn't properly work with the new VCS2 code that Daniel merged a couple of weeks ago. I too noticed this, but was remaining silent in the hopes that we could actually try to

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Extract node allocation from bind

2014-05-07 Thread Ben Widawsky
On Wed, May 07, 2014 at 05:55:00PM +0100, Chris Wilson wrote: On Wed, May 07, 2014 at 09:00:16AM -0700, Ben Widawsky wrote: On Wed, May 07, 2014 at 04:53:08PM +0100, Chris Wilson wrote: On Wed, May 07, 2014 at 08:45:38AM -0700, Ben Widawsky wrote: Hmm. I really don't see what's actually

[Intel-gfx] [PATCH 01/10] drm/i915: Make semaphore updates more precise

2014-05-07 Thread Ben Widawsky
With the ring mask we now have an easy way to know the number of rings in the system, and therefore can accurately predict the number of dwords to emit for semaphore signalling. This was not possible (easily) previously. There should be no functional impact, simply fewer instructions emitted.

Re: [Intel-gfx] [RFC] drm/i915 : Reduce the shmem page allocation time by using blitter engines for clearing pages.

2014-05-07 Thread Eric Anholt
Gupta, Sourab sourab.gu...@intel.com writes: On Tue, 2014-05-06 at 17:56 +, Eric Anholt wrote: sourab.gu...@intel.com writes: From: Sourab Gupta sourab.gu...@intel.com This patch is in continuation of and is dependent on earlier patch series to 'reduce the time for which device

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Improve fallback ring waiting

2014-05-07 Thread Volkin, Bradley D
On Mon, May 05, 2014 at 01:07:32AM -0700, Chris Wilson wrote: A few improvements to the fallback method for waiting upon ring space: 1. Fix the start/end wait tracepoints to always be paired. 2. Increase responsiveness of checking 3. Mark the process as waiting upon io 4. Check for signal

Re: [Intel-gfx] [PATCH 1/2] rendercopy/bdw: Enable hw-generated binding tables

2014-05-07 Thread Abdiel Janulgue
On Wednesday, May 07, 2014 02:49:31 PM Ville Syrjälä wrote: I quickly cobbled together a hsw version of this and gave it a whirl on one machine. Seems to work just fine here, and no lockups when switching between hw and sw binding tables. Did you get the lockups on hsw even with rendercopy?

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Flush request queue when waiting for ring space

2014-05-07 Thread Volkin, Bradley D
On Mon, May 05, 2014 at 01:07:33AM -0700, Chris Wilson wrote: During the review of commit 1f70999f9052f5a1b0ce1a55aff3808f2ec9fe42 Author: Chris Wilson ch...@chris-wilson.co.uk Date: Mon Jan 27 22:43:07 2014 + drm/i915: Prevent recursion by retiring requests when the ring is

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Improve fallback ring waiting

2014-05-07 Thread Daniel Vetter
On Mon, May 05, 2014 at 09:07:32AM +0100, Chris Wilson wrote: A few improvements to the fallback method for waiting upon ring space: 1. Fix the start/end wait tracepoints to always be paired. 2. Increase responsiveness of checking 3. Mark the process as waiting upon io 4. Check for signal

Re: [Intel-gfx] [PATCH] drm/i915/bdw: Only use 2g GGTT for 32b platforms

2014-05-07 Thread Ben Widawsky
On Wed, May 07, 2014 at 09:42:57AM +0200, Daniel Vetter wrote: On Tue, May 06, 2014 at 09:58:59PM -0700, Ben Widawsky wrote: From: Ben Widawsky benjamin.widaw...@linux.intel.com Daniel requested in the bug that I use a 3GB fallback size. Since this is not in the spec as a valid size, I

[Intel-gfx] [PATCH] [v3] drm/i915/bdw: Only use 2g GGTT for 32b platforms

2014-05-07 Thread Ben Widawsky
Daniel requested in the bug that I use a 3GB fallback size. Since this is not in the spec as a valid size, I decided against it. We could potentially add a patch to bump it to 3GB on top of this one. This probably should be CC: stable - but I'll let the powers that be decide that one. Regression

Re: [Intel-gfx] [PATCH] UXA: Wait until a pageflip actually completes to report it.

2014-05-07 Thread Jamey Sharp
On Wed, May 07, 2014 at 04:55:18PM +0100, Chris Wilson wrote: On Mon, May 05, 2014 at 11:05:07PM -0700, Jamey Sharp wrote: UXA was reporting page-flip completion as soon as the flip was scheduled with the kernel, instead of waiting for the kernel to indicate that the flip had actually