Re: [Intel-gfx] [PATCH v3] drm/i915: Added write-enable pte bit support

2014-06-01 Thread Akash Goel
On Mon, 2014-05-19 at 13:03 +0530, Akash Goel wrote: On Mon, 2014-05-19 at 08:56 +0200, Daniel Vetter wrote: On Sun, May 18, 2014 at 11:27:00AM +0530, Akash Goel wrote: On Wed, 2014-05-14 at 10:14 +0200, Daniel Vetter wrote: On Tue, May 13, 2014 at 03:43:12PM -0700, Jesse Barnes wrote:

Re: [Intel-gfx] [PATCH v4 2/4] drm/i915: New drm crtc property for varying the Pipe Src size

2014-06-01 Thread Akash Goel
Hi Ville, Please could you respond to my last mail. This will enable me to make further progress on this patch. Bes Regards Akash On Sun, 2014-05-04 at 15:51 +0530, Akash Goel wrote: On Tue, 2014-04-29 at 17:06 +0300, Ville Syrjälä wrote: On Sun, Apr 20, 2014 at 04:14:18PM +0530,

[Intel-gfx] [PATCH v10] drm/i915: Replaced Blitter ring based flips with MMIO flips

2014-06-01 Thread sourab . gupta
From: Sourab Gupta sourab.gu...@intel.com This patch enables the framework for using MMIO based flip calls, in contrast with the CS based flip calls which are being used currently. MMIO based flip calls can be enabled on architectures where Render and Blitter engines reside in different power

[Intel-gfx] [PATCH 2/3] drm/i915: Change Mipi register definitions

2014-06-01 Thread Shashank Sharma
Re-define MIPI register definitions in such a way that most of the existing DSI code can be re-used for future platforms. Register definitions are re-written using MMIO offset variable, so that without changing the existing sequence, same code can be generically applied. V4: Addressing review

[Intel-gfx] [PATCH 3/3] drm/i915: Use transcoder as index to MIPI regs

2014-06-01 Thread Shashank Sharma
Conceptually, the MIPI registers are addressed by the MIPI transcoder index, not the pipe. It doesn't matter right now, because there's a 1:1 relationship between pipes and MIPI transcoders, but that change allows us to break that link in the future V1: Created new patch to address Damien's