On 6/25/2014 11:27 AM, Chris Wilson wrote:
On Wed, Jun 25, 2014 at 11:24:27AM +0530, Jindal, Sonika wrote:
On 6/18/2014 5:09 PM, Chris Wilson wrote:
On Wed, Jun 18, 2014 at 12:32:00PM +0100, Damien Lespiau wrote:
On Wed, Jun 18, 2014 at 02:27:27PM +0530, sonika.jin...@intel.com wrote:
For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll
during the DSI enable sequence
Causing WARN dump otherwise in dpio_reads
v2: Add IS_CHERRYVIEW check as suggested by Ville
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Ville Syrjälä
On Tue, Jun 24, 2014 at 03:12:50PM -0700, Todd Previte wrote:
Several compliance tests require that follow-up AUX transactions (after a
failure or no response) are not resent sooner than 400us later. Add a 400us
delay to the response time of any failed transaction to account for this.
Il 22/06/2014 10:25, Chen, Tiejun ha scritto:
In qemu-upstream, as you commented we can't create this as a ISA class
type explicitly.
Note I didn't say that QEMU doesn't like having two ISA bridges.
I commented that the firmware will see two ISA bridges and will try to
initialize both of
On Wed, 25 Jun 2014, Todd Previte tprev...@gmail.com wrote:
Implements some of the basic EDID tests for Displayport compliance. These
tests
include reading the EDID, verifying the checksum and writing the test
responses
back to the sink device.
Signed-off-by: Todd Previte
On Wed, 25 Jun 2014, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Jun 24, 2014 at 05:05:02PM -0700, Matt Roper wrote:
crtc-primary-fb may be NULL upon entry to intel_pipe_set_base() if the
primary plane has previously been disabled via the universal plane
interface. We need to check
On Mon, Apr 28, 2014 at 04:01:29PM +0100, arun.siluv...@linux.intel.com wrote:
From: Siluvery, Arun arun.siluv...@intel.com
This patch adds support to have gem objects of variable size.
The size of the gem object obj-size is always constant and this fact
is tightly coupled in the driver;
On Tue, 24 Jun 2014, Aaron Lu aaron...@intel.com wrote:
Some Thinkpad laptops' firmware will initiate a backlight level change
request through operation region on the events of AC plug/unplug, but
since we are not using firmware's interface to do the backlight setting
on these affected
On Wed, Jun 25, 2014 at 11:51:33AM +0100, Damien Lespiau wrote:
(This is not necessarily things one would need to take into account for
this work, just a few thoughts).
One thing I'm wondering is how fitting the size parameter really is
when talking about inherently 2D buffers.
For
On 25/06/2014 12:14, Damien Lespiau wrote:
On Wed, Jun 25, 2014 at 11:51:33AM +0100, Damien Lespiau wrote:
(This is not necessarily things one would need to take into account for
this work, just a few thoughts).
One thing I'm wondering is how fitting the size parameter really is
when talking
On Mon, 31 Mar 2014, Jesse Barnes jbar...@virtuousgeek.org wrote:
With the new checks in place, we can see we're doing things backwards,
so fix them up per the spec.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_dp.c | 13 +++--
1 file changed,
On Wed, Jun 25, 2014 at 12:46:57PM +0100, Siluvery, Arun wrote:
On 25/06/2014 12:14, Damien Lespiau wrote:
On Wed, Jun 25, 2014 at 11:51:33AM +0100, Damien Lespiau wrote:
(This is not necessarily things one would need to take into account for
this work, just a few thoughts).
One thing I'm
On Wed, Jun 25, 2014 at 03:03:44PM +0200, Tom Van Braeckel wrote:
Hi,
There seems to be a regression in the upcoming Linux 3.16-rc2 release
candidate that I bisected down to this first bad commit:
[dbb42748ac4929987c1449ecb296b39ef8956b62] drm/i915: Move the C3 LP
write bit setup to
On 06/25/2014 01:57 PM, Damien Lespiau wrote:
On Wed, Jun 25, 2014 at 12:46:57PM +0100, Siluvery, Arun wrote:
On 25/06/2014 12:14, Damien Lespiau wrote:
On Wed, Jun 25, 2014 at 11:51:33AM +0100, Damien Lespiau wrote:
(This is not necessarily things one would need to take into account for
On Wed, Jun 25, 2014 at 02:26:52PM +0100, Tvrtko Ursulin wrote:
That's a good question to ask a GL team. In the light of sparse
textures I think the region idea would be better.
We would need to define what the coordinates mean, for instance:
- 2D view of the buffer, and the kernel takes
On Wed, Jun 25, 2014 at 02:06:55PM -0400, Alan Stern wrote:
Daniel:
I encountered a new problem in the i915 driver the first time I booted
a 3.16-rc kernel on this computer. When it switched over to the frame
buffer driver, the screen went blank and stayed that way.
3.15 works okay.
On Wed, Jun 25, 2014 at 08:24:29AM -0700, Jesse Barnes wrote:
Apparently we can't trust this field on other platforms and need to find
some other way.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Since it's a regression it
On Fri, 13 Jun 2014 13:37:47 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use kHz units in vlv cdclk code since that's more customary.
Also replace the precomputed 90% values with *9/10 computation
for extra clarity.
Signed-off-by: Ville
On Wed, 25 Jun 2014, Ville [iso-8859-1] Syrj�l� wrote:
On Wed, Jun 25, 2014 at 02:06:55PM -0400, Alan Stern wrote:
Daniel:
I encountered a new problem in the i915 driver the first time I booted
a 3.16-rc kernel on this computer. When it switched over to the frame
buffer driver, the
On Fri, 13 Jun 2014 13:37:50 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Depending on the HPLL frequency one of the supported cdclk frquencies is
either 320MHz or 333MHz. Figure out which one it is to accurately pick
the minimal required
From: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
From: Daniel Vetter daniel.vet...@ffwll.ch
This way only the dynamic WRPLL selection for hdmi ddi mode is
done in intel_ddi_pll_select.
v2: Don't clobber the precomputed values when selecting clocks fro
hdmi encoders.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
From: Daniel Vetter daniel.vet...@ffwll.ch
The call to intel_ddi_pll_enable in haswell_crtc_mode_set is the only
function that still touches the hardware state from the crtc mode_set
callback on hsw. Since the SPLL isn't ever shared we can easily take
it out into the hsw crt encoder functions.
From: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 ++
1 file changed, 26 insertions(+)
diff --git
From: Daniel Vetter daniel.vet...@ffwll.ch
This time around another cute hack to pre-fill the pll-hw_state with
the right values. And also remove a bunch of checks which will be
replaced by lots more checks in the common framework.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by:
This is needed by an upcoming patch that moves the PCH/CRT PLL disabling
into the post_disable hook, after which we want to keep the modeset
sequence at its current state. At this point this won't have an effect
since the PCH/CRT post_disable hook is atm a NOP.
Signed-off-by: Imre Deak
From: Daniel Vetter daniel.vet...@ffwll.ch
Just boring sed job for preparation.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Damien Lespiau damien.lesp...@intel.com
[imre: rebased on patchset version w/o pch/crt/fdi refactoring]
Signed-off-by: Imre Deak imre.d...@intel.com
From: Daniel Vetter daniel.vet...@ffwll.ch
Just filing in names and ids, but not yet officially registering them
so that the hw state cross checker doesn't completely freak out about
them. Still since we do already read out and cross check
config-shared_dpll the basics are now there to flesh out
From: Daniel Vetter daniel.vet...@ffwll.ch
Similar to how the -crtc_mode_set hook should touch the hardware to
enable anything the -crtc_off hook should disable anything in the
hardware. Otherwise runtime pm for dpms will not work.
Currently the only things left int the haswell_crtc_off hook is
From: Daniel Vetter daniel.vet...@ffwll.ch
SPLL would be a reference clock we could potentially share,
especially if we want to use the SSC mode. But currently we
don't, so let's rip out this complexity for a simpler conversion
to the new display pll framework.
Signed-off-by: Daniel Vetter
From: Daniel Vetter daniel.vet...@ffwll.ch
Currently still with a redudant WARN_ON in there, the common shared
dpll code will take care of this in the future.
Also we need to flip the switch for the transitional hack now to make
sure that we disable the right pll.
Signed-off-by: Daniel Vetter
From: Daniel Vetter daniel.vet...@ffwll.ch
To make things a bit more manageable extract a new function for
reading out common ddi port state. This means a bit of duplication
between encoders and the core since both look at the same registers,
but doesn't seem worth to make a fuzz about.
We can
From: Daniel Vetter daniel.vet...@ffwll.ch
To be able to do this we need to separately keep track of how many
crtcs need a given WRPLL and how many actually actively use it. The
common shared dpll framework already has all this, including massive
state readout and cross checking. Which allows us
On Wed, Jun 25, 2014 at 11:54:06AM -0700, Jesse Barnes wrote:
On Fri, 13 Jun 2014 13:37:51 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Drop the cdclk frequency to 200MHz on vlv when all pipes are off. In
theory we should be able to use
On Wed, Jun 25, 2014 at 11:55:58AM -0700, Jesse Barnes wrote:
On Fri, 13 Jun 2014 13:37:53 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
If someone is interested in the current cdclk frquency it should
be stable and not in process of
On Wed, Jun 25, 2014 at 12:03:01PM -0700, Jesse Barnes wrote:
On Fri, 13 Jun 2014 13:37:56 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Now that the CMNRESET deassert is part of the cmnlane power well,
intel_reset_dpio() is called too
On Fri, Jun 20, 2014 at 01:43:50PM +0200, Joerg Roedel wrote:
Change_pte is also called when the underlying page of an address
changes in the kernel which would matter for DMA. But that can only
happen in KSM and uprobes code which is probably not of interest for the
i915 driver.
The other
On Mon 2014-06-09 13:03:31, Jiri Kosina wrote:
On Mon, 9 Jun 2014, Pavel Machek wrote:
Strange. It seems 3.15 with the patch reverted only boots in 30% or so
cases... And I've seen resume failure, too, so maybe I was just lucky
that it worked for a while.
git bisect really
Apparently trinary logic is hard. We were falling through all the forced
cases and simply enabling aliasing PPGTT or not based on hardware,
rather than full PPGTT if available.
References: https://bugs.freedesktop.org/show_bug.cgi?id=80083
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
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