Hey,
On 31-07-14 20:58, Jesse Barnes wrote:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch at this point, no testing has been done.
There are a couple of goals here:
1) allow applications
From: Sagar Kamble sagar.a.kam...@intel.com
Sequence to get gfx clocks on/off, allow/disallow wake and save/restore of
gunit registers need to be followed in
PM suspend and resume path similar to runtime suspend and resume.
v2:
1. Keeping GT access, wake, gunit save/restore related helpers
Hi Jesse,
On 07/31/2014 07:58 PM, Jesse Barnes wrote:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch at this point, no testing has been done.
There are a couple of goals here:
1) allow
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of Ville Syrjälä
Sent: Thursday, July 31, 2014 5:16 PM
To: Daniel Vetter
Cc: Intel Graphics Development
Subject: Re: [Intel-gfx] [PATCH 5/7] drm/i915: Initialize the aliasing
ppgtt as
While cruising through the specs, I noticed that we were missing the BDW HDMI
DDI buffer tables.
Patch 1: re-factor how we handle the VBT entry as the parsing code made
HSW-specific assumptions about the level tables
Patch 2: The actual BDW tables
Pathes 3 4 are trivial clean ups on
Among the changes, the tables has only 10 entries instead of 12 on HSW
and the index the the 800mV/0dB entry has changed.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 28 +++-
1 file changed, 23 insertions(+), 5
We used to carry a default HDMI value in entry 9, but this entry got
removed for both HSW and BDW.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
The knowledge about the HDMI/DVI DDI translation table was scattered
around.
- info-hdmi_level_shift was initialized with 6, the index of the 800
mV, 0dB translation
- A check on the VBT value was done to ensure it wasn't overflowing
the translation table ( 0xC)
- The actual
We always write entries 0 to 8 from the DDI translation tables and then
entry 9 for HDMI/DVI with the help of the VBT. We then don't need the
failsafe HDMI entry in the DP/eDP/FDI tables.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 3 ---
1 file
On Thu, Jul 31, 2014 at 12:07:22PM -0700, Rodrigo Vivi wrote:
With this bit enabled, HW changes the color when compressing frames for
debug purposes.
ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the
On hsw/bdw VBT can signal no DP on a digital connector, so when we
get a hotplug irq in that situation, don't continue if we haven't
actually got a DP output register configured.
This fixes an oops where the aux mutex isn't initialised.
Bugzilla:
On Fri, Aug 01, 2014 at 08:47:13PM +1000, Dave Airlie wrote:
On hsw/bdw VBT can signal no DP on a digital connector, so when we
get a hotplug irq in that situation, don't continue if we haven't
actually got a DP output register configured.
This fixes an oops where the aux mutex isn't
On Thu, Jul 31, 2014 at 05:16:21PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add defines for all the watermark registers on modernish gmch platforms.
VLV has increased the number of bits
On Thu, Jul 31, 2014 at 05:57:33PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just that.
On Thu, Jul 31, 2014 at 08:59:08PM +1000, Dave Airlie wrote:
On 31 July 2014 17:37, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Jul 31, 2014 at 1:49 AM, Dave Airlie airl...@gmail.com wrote:
Daniel, the only way intel_dp-is_mst can get reset is inside this path.
Ok, so that one should be
On Thu, Jul 31, 2014 at 02:03:36PM +0300, Imre Deak wrote:
Just like during booting the BIOS can leave the VDD bit enabled after
system resume. So apply the same state sanitization there too. This
fixes a problem where after resume the port power domain refcount gets
unbalanced.
v2:
-
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add defines for all the watermark registers on modernish gmch platforms.
VLV has increased the number of bits available for certain watermaks so
expand the masks appropriately. Also vlv and chv have added some extra
FW registers.
Not sure what
On Thu, Jul 31, 2014 at 03:08:29PM -0300, Paulo Zanoni wrote:
2014-06-27 20:04 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The DDL registers can hold 7bit numbers. Make the most of those seven
bits by adjusting the threshold where we switch
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just that.
v2: Rebase on top of Imre's cxsr changes (Paulo)
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
Hi Randy,
On Thursday 31 July 2014 15:16:21 Randy Dunlap wrote:
On 05/12/14 11:04, Randy Dunlap wrote:
On 05/12/2014 08:54 AM, Daniel Vetter wrote:
On Mon, May 12, 2014 at 08:23:45AM -0700, Randy Dunlap wrote:
On 05/12/2014 01:58 AM, Daniel Vetter wrote:
On Mon, May 12, 2014 at
On Tue, Jul 29, 2014 at 09:57:09AM -0700, Jesse Barnes wrote:
On Sat, 28 Jun 2014 02:04:05 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Just an attempt to frob these bits. Apparently we should not need to
touch them (apart from maybe
On Thu, 2014-07-31 at 23:47 +0200, Ian Kumlien wrote:
On tor, 2014-07-31 at 14:39 +0300, Imre Deak wrote:
On Wed, 2014-07-30 at 22:52 +0200, Ian Kumlien wrote:
Sorry for the delay, it's been damned hot - vacation is over and
overtime has been all the rage at work...
No problem,
From: Ville Syrjälä ville.syrj...@linux.intel.com
Clear the override bits to make sure the hardware maanages
the TX FIFO reset master on its own.
v2: Squash with the earlier attempt at forcing the override bits
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
Note to maintainer:
On Fri, Aug 1, 2014 at 3:16 PM, Imre Deak imre.d...@intel.com wrote:
[--8--]
Ok, I see the trace of suspend/resume now, but the bug has vanished.. I
can't see the WARN backtrace in your original report, nor the debug
message from the above fix, that would indicate that it had fixed
anything
On Thu, Jul 24, 2014 at 05:04:20PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
This is mostly for correctness so that we know we are running the LR
context correctly (this is, the PDPs are contained inside the context
object).
v2: Move the check to inside the
On Thu, Jul 31, 2014 at 12:07:44PM -0700, Rodrigo Vivi wrote:
According to spec FBC on BDW and HSW are identical without any gaps.
So let's copy the nuke and let FBC really start compressing stuff.
Without this patch we can verify with false color that nothing is being
compressed. With the
2014-08-01 9:36 GMT-03:00 ville.syrj...@linux.intel.com:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just that.
v2: Rebase on top of Imre's cxsr changes (Paulo)
Reviewed-by:
On Thu, Jul 24, 2014 at 05:04:37PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
Each logical ring context has the tail pointer in the context object,
so update it before submission.
v2: New namespace.
I believe we could just leave the context object mapped for its
On Thu, Jul 24, 2014 at 05:04:42PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
If we reset a ring after a hang, we have to make sure that we clear
out all queued Execlists requests.
v2: The ring is, at this point, already being correctly re-programmed
for
On Thu, Jul 24, 2014 at 05:04:42PM +0100, Thomas Daniel wrote:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3188403..6e604c9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1587,6
On Thu, Jul 24, 2014 at 05:04:45PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
v2: Warn and return if LRCs are not enabled.
v3: Grab the Execlists spinlock (noticed by Daniel Vetter).
Signed-off-by: Oscar Mateo oscar.ma...@intel.com
This looks like it may be
2014-08-01 7:07 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
The knowledge about the HDMI/DVI DDI translation table was scattered
around.
- info-hdmi_level_shift was initialized with 6, the index of the 800
mV, 0dB translation
- A check on the VBT value was done to ensure it
2014-08-01 7:07 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
Among the changes, the tables has only 10 entries instead of 12 on HSW
and the index the the 800mV/0dB entry has changed.
And now your HDMI monitors on BDW will look better if you have eagle eyes.
Reviewed-by: Paulo Zanoni
2014-08-01 7:07 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
We always write entries 0 to 8 from the DDI translation tables and then
entry 9 for HDMI/DVI with the help of the VBT. We then don't need the
failsafe HDMI entry in the DP/eDP/FDI tables.
And it seems we were not even using
2014-08-01 7:07 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
We used to carry a default HDMI value in entry 9, but this entry got
removed for both HSW and BDW.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
On Thu, Jul 24, 2014 at 05:04:47PM +0100, Thomas Daniel wrote:
From: Ben Widawsky b...@bwidawsk.net
This has turned out to be really handy in debug so far.
Update:
Since writing this patch, I've gotten similar code upstream for error
state. I've used it quite a bit in debugfs however, and
On Fri, 01 Aug 2014 10:04:55 +0100
Tvrtko Ursulin tvrtko.ursu...@linux.intel.com wrote:
Hi Jesse,
On 07/31/2014 07:58 PM, Jesse Barnes wrote:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
With this bit enabled, HW changes the color when compressing frames for
debug purposes.
ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this
On Thu, Jul 24, 2014 at 05:04:08PM +0100, Thomas Daniel wrote:
All patches can have my r-b tag but patches 12, 34, 37, 39 which have
minor comments (in terms of code changes) to address. I did look more at
the low-level stuff (Vs the higher level abstractions).
At this point, I believe the way
GTIER and DEIER doesn't have same interface on HSW so this or operation
makes the information provided useless.
v2: since we have gtier variable already let's split for everybody
and avoid the strange | op.
Also avoid overriding the value that was set for vlv. In this case I
believe that
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also listing old
DEIER and GTIER that doesn't exist on BDW anymore. This was causing
unclaimed register messages:
On Fri, 1 Aug 2014 17:09:50 +0100
Damien Lespiau damien.lesp...@intel.com wrote:
On Thu, Jul 24, 2014 at 05:04:08PM +0100, Thomas Daniel wrote:
All patches can have my r-b tag but patches 12, 34, 37, 39 which have
minor comments (in terms of code changes) to address. I did look more at
the
On Thu, 31 Jul 2014 12:08:20 -0700
Rodrigo Vivi rodrigo.v...@intel.com wrote:
WA to skip the first page of stolen memory due to sporadic HW write on *CS
Idle
v2: Improve variable names and fix allocated size.
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi
Hi,
I've pushed these two patches to i-g-t, they definitely are an
improvement and look good to me.
Thanks!
--
Damien
On Wed, Jul 16, 2014 at 07:39:32PM +0530, Gaurav K Singh wrote:
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
---
tools/intel_bios.h| 132
To check that static workarounds are set and stay after init,
hang and suspend/restore. Checks are currently provided for ivb
and bdw only.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
lib/intel_chipset.h |4 +
lib/intel_workaround.h | 142 +++
Hi,
With ivb we currently drop 5 out of 11 static workarounds due to
hang/reset recovery.
With bdw we see that some workarounds wont stick even after init, due
to rc6 entry dropping some regs that are not part of power context?
Mika Kuoppala (1):
tests: Add drv_workarounds
2014-08-01 6:13 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
GTIER and DEIER doesn't have same interface on HSW so this or operation
makes the information provided useless.
v2: since we have gtier variable already let's split for everybody
and avoid the strange | op.
Also avoid
2014-08-01 6:14 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also listing
old
DEIER and GTIER that doesn't
We dont use this pre CTG and we will need it for gen8 golden state.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
lib/gen6_render.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/gen6_render.h b/lib/gen6_render.h
index dfee6e7..c3e85eb 100644
---
Instead of building batch directly to memory, build into cmd and
state arrays. This representation allows us more flexibility in batch
state expression and batch generation/relocation.
As a bonus, we can also attach the line information that produced the
batch data to help debugging.
There is no
as this was already changed in kernel.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/null_state_gen/intel_null_state_gen.c |1 +
1 file changed, 1 insertion(+)
diff --git a/tools/null_state_gen/intel_null_state_gen.c
b/tools/null_state_gen/intel_null_state_gen.c
index
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
lib/intel_reg.h |1 +
tests/gem_exec_parse.c |1 -
tests/gem_non_secure_batch.c |4 +---
tests/gen7_forcewake_mt.c|5 ++---
4 files changed, 4 insertions(+), 7 deletions(-)
diff --git
No functional changes
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
lib/gen6_render.h |2 +-
lib/rendercopy_gen8.c |2 +-
tools/null_state_gen/intel_renderstate_gen8.c |2 +-
3 files changed, 3 insertions(+), 3
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise we will hit lockdep_assert_held(dev-struct_mutex)
from intel_edp_psr_match_conditions(). This happens all the time on my
BDW machine: just boot it and you'll get it.
In this patch I just grab struct_mutex in the deepest possible place
(around
Fix signal_offset when recording semaphore state on BDW.
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Paulo Zanoni paulo.r.zan...@intel.com
cat i915_reg.h | sort | uniq -d | grep define
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Dave Airlie airl...@redhat.com
On HSW/BDW the VBT can tell us if we need to have DP support for a port,
if we don't have DP this caused an oops in the hpd handling.
Don't hook up the DP hpd handling if we don't have a DP port.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81856
From: Paulo Zanoni paulo.r.zan...@intel.com
The GEN6_PM* registers don't exist on BDW anymore, so when we read
this file we trigger unclaimed register errors. The equivalent BDW
register for PMs is GEN8_GT_I*R(2), so use it.
Testcase: igt/pm_rpm/debugfs-read
Signed-off-by: Paulo Zanoni
2014-08-01 17:47 GMT-03:00 Dave Airlie airl...@gmail.com:
From: Dave Airlie airl...@redhat.com
On HSW/BDW the VBT can tell us if we need to have DP support for a port,
if we don't have DP this caused an oops in the hpd handling.
Don't hook up the DP hpd handling if we don't have a DP port.
On 2 August 2014 07:38, Paulo Zanoni przan...@gmail.com wrote:
2014-08-01 17:47 GMT-03:00 Dave Airlie airl...@gmail.com:
From: Dave Airlie airl...@redhat.com
On HSW/BDW the VBT can tell us if we need to have DP support for a port,
if we don't have DP this caused an oops in the hpd handling.
On 08/01/14 05:58, Laurent Pinchart wrote:
Hi Randy,
On Thursday 31 July 2014 15:16:21 Randy Dunlap wrote:
On 05/12/14 11:04, Randy Dunlap wrote:
On 05/12/2014 08:54 AM, Daniel Vetter wrote:
On Mon, May 12, 2014 at 08:23:45AM -0700, Randy Dunlap wrote:
On 05/12/2014 01:58 AM, Daniel Vetter
GTIER and DEIER doesn't have same interface on HSW so this or operation
makes the information provided useless.
v2: since we have gtier variable already let's split for everybody
and avoid the strange | op.
Also avoid overriding the value that was set for vlv. In this case I
believe that
BDW has many other Display Engine interrupts and GT interrupts registers.
Collecting it properly on gpu_error_state.
On debugfs all was properly listed already but besides we were also listing old
DEIER and GTIER that doesn't exist on BDW anymore. This was causing
unclaimed register messages:
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