On Thu, Aug 14, 2014 at 11:52:47PM +, Wilde, Martin wrote:
Greetings,
I am submitting the below changes to i915 Gfx driver to support resume time
Responsiveness measurements. These changes parallel the work already done in
the IVB Windows Gfx driver. These changes in addition to
On Thu, Aug 14, 2014 at 05:45:59PM +0300, Ville Syrjälä wrote:
On Thu, Aug 14, 2014 at 04:23:16PM +0200, Daniel Vetter wrote:
On Thu, Aug 14, 2014 at 03:46:43PM +0300, Mika Kuoppala wrote:
We lost the software state tracking due to reset, so don't
complain if it doesn't match.
This
On Fri, Aug 15, 2014 at 01:21:52AM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Thomas asked me to repost my 830/ns2501 patches. So here they are. I added
a few more patches (trickle feed and unused ring init) to fix some post-resume
issues.
On Thu, Aug 14, 2014 at 12:06:02PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we're runtime suspended and try to use the plane interfaces, we
will get a lot of WARNs saying we did the wrong thing.
We need to get runtime PM references to pin the objects, and
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Thursday, August 14, 2014 9:00 PM
To: Daniel, Thomas
Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 27/43] drm/i915/bdw: Render state init
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Thursday, August 14, 2014 9:10 PM
To: Daniel, Thomas
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 30/43] drm/i915/bdw: Two-stage execlist
submit process
On Wed, 2014-08-13 at 19:33 +0300, Ville Syrjälä wrote:
The series seems fine to me.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
for the rest as well.
Thanks, I assume it's for v2. I'd say this is for -fixes. The problem
existed even in 3.16, but only the MST support made it
On Fri, Aug 15, 2014 at 08:51:22AM +, Daniel, Thomas wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Thursday, August 14, 2014 9:10 PM
To: Daniel, Thomas
Cc: intel-gfx@lists.freedesktop.org
Subject: Re:
On 14 August 2014 17:02, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Aug 14, 2014 at 04:33:18PM +0100, Thomas Wood wrote:
Make sure plane rotation is reset correctly when restoring the fbdev
configuration by using drm_mode_plane_set_obj_prop. This calls the
driver's set_property callback and
On 15 August 2014 10:42, Thomas Wood thomas.w...@intel.com wrote:
On 14 August 2014 17:02, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Aug 14, 2014 at 04:33:18PM +0100, Thomas Wood wrote:
Make sure plane rotation is reset correctly when restoring the fbdev
configuration by using
On Fri, 15 Aug 2014, Imre Deak imre.d...@intel.com wrote:
On Wed, 2014-08-13 at 19:33 +0300, Ville Syrjälä wrote:
The series seems fine to me.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
for the rest as well.
Thanks, I assume it's for v2. I'd say this is for -fixes. The
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Adding relevant mailing lists.
On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross jgr...@suse.com wrote:
I'm just about to create a patch for full PAT support in the Linux
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, August 11, 2014 3:30 PM
To: Daniel, Thomas
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 11/43] drm/i915/bdw: Render moot context
reset and switch
On Thu, Aug 14, 2014 at 05:55:11AM +0200, Juergen Gross wrote:
On 08/13/2014 05:07 PM, Jesse Barnes wrote:
On Fri, 8 Aug 2014 15:14:15 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Adding relevant mailing lists.
On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross jgr...@suse.com wrote:
On Fri, Aug 15, 2014 at 10:48:05AM +0100, Thomas Wood wrote:
On 15 August 2014 10:42, Thomas Wood thomas.w...@intel.com wrote:
On 14 August 2014 17:02, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Aug 14, 2014 at 04:33:18PM +0100, Thomas Wood wrote:
Make sure plane rotation is reset
From: Oscar Mateo oscar.ma...@intel.com
This is mostly for correctness so that we know we are running the LR
context correctly (this is, the PDPs are contained inside the context
object).
v2: Move the check to inside the enable PPGTT function. The switch
happens in two places: the legacy context
Chris Wilson ch...@chris-wilson.co.uk writes:
For stolen pages, since it is verboten to access them directly on many
architectures, we have to read them through the GTT aperture. If they
are not accessible through the aperture, then we have to abort.
This was complicated by
commit
On Fri, 2014-08-15 at 12:48 +0300, Jani Nikula wrote:
On Fri, 15 Aug 2014, Imre Deak imre.d...@intel.com wrote:
On Wed, 2014-08-13 at 19:33 +0300, Ville Syrjälä wrote:
The series seems fine to me.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
for the rest as well.
On Fri, 15 Aug 2014, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Backlight on delay uses PWM enable time to seperate PWM to
backlight enable assert. Previous time difference used timing
from VDD enable which occur several seconds before resulting
in PWM
On Thu, Jul 24, 2014 at 05:04:43PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
Since the ringbuffer does not belong per engine anymore, we have to
make sure that we are always recording the correct ringbuffer.
TODO: This is only a small fix to keep basic error
On Thu, Jul 24, 2014 at 05:04:48PM +0100, Thomas Daniel wrote:
+/**
+ * intel_lr_context_render_state_init() - render state init for Execlists
+ * @ring: Engine Command Streamer.
+ * @ctx: Context to initialize.
+ *
+ * A.K.A. null-context, A.K.A. golden-context. In a word, the render engine
On Thu, Jul 24, 2014 at 05:04:50PM +0100, Thomas Daniel wrote:
From: Oscar Mateo oscar.ma...@intel.com
Up until now, we have pinned every logical ring context backing object
during creation, and left it pinned until destruction. This made my life
easier, but it's a harmful thing to do,
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Looks perfectly fine to me.
Signed-off-by: Thomas Richter rich...@rus.uni-stuttgart.de
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Try to use the same programming sequence as used by the IEGD driver.
Also shovel the magic register values into a big static const array.
The register values are actually the based on
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In my earlier rewrite I missed a few important registers. Thomas Richter
noticed that they're needed to make his machine resume correctly.
Looks like IEGD does a one time init of these
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes,
60Hz and 56Hz. The magic register values we have correspond to the 60Hz
mode, and as I don't know how one would
On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The max watermark value for gen2 planes B and C is 0x1f, instead of
the 0x3f that plane A uses.
Also check against the max even if the pipe is disabled since the
FIFO size exceeds the
On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Just pass the intel_crtc around instead of dev_priv+pipe.
Also make intel_wait_for_pipe_off() static since it's only used in
intel_display.c.
Signed-off-by: Ville Syrjälä
On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Disable double wide even if the pipe quirk compels us to leave the
pipe running. Double wide has certain implications for the plane
assignments so best keep it off.
Also helps resuming
On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead
of DVOC.
FIXME: Maybe need to dig out the correct DVO port from VBT
Signed-off-by: Ville Syrjälä
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Calling the mode_set hook on DPMS changes doesn't seem to be necessary
for ns2501. Just drop it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Tested-by: Thomas Richter
On 15.08.2014 00:21, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
To more closely match the IEGD ns2501 driver behaviour, call the
mode_set hook while the DVO port is still disabled, then enable the DVO
port, and finally call the dpms hook.
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Thomas Richter rich...@rus.uni-stuttgart.de
---
drivers/gpu/drm/i915/dvo_ns2501.c | 17 -
1
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Try to use the same programming sequence as used by the IEGD driver.
Also shovel the magic register values into a big static const array.
The register values are actually the based on
Hi Mika / Daniel,
below is the basic code path of a reset which has been changed by my patch:
i915_reset()
{
i915_gem_reset() - This used to call i915_gem_context_reset(), which
has now been removed.
.
i915_gem_init_hw()
.
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes,
60Hz and 56Hz. The magic register values we have correspond to the 60Hz
mode, and as I don't know how one would
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The spec says:
For the correct operation of the muxed DVO pins (GDEVSELB/ I2Cdata,
GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, GTRDYB/DVI_Clk): Bit 31
(DPLL VCO Enable) and Bit 30 (2X Clock
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
830 really does want the pipe A quirk. The planes and ports don't
react to any register writes unless the pipe currently attached
to them is running, so it's impossible to move them to
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
830M has problems when some of the pipes are disabled. Namely if a
plane, DVO port etc. is currently assigned to a disabled pipe, it
can't moved to the other pipe until the current pipe
On 15.08.2014 00:22, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from
S3 unless VGACNTR has been restore to the original value. The BIOS
value in this case was 0x0124008E. Setting the VGA
On Thu, 14 Aug 2014, Bertrik Sikken bert...@sikken.nl wrote:
Hi Jani,
On 13-8-2014 3:43, Jani Nikula wrote:
On Wed, 23 Jul 2014, Hans de Goede hdego...@redhat.com wrote:
On 07/22/2014 08:52 AM, Daniel Vetter wrote:
On Tue, Jul 22, 2014 at 8:42 AM, Hans de Goede hdego...@redhat.com wrote:
On 15 August 2014 11:22, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Aug 15, 2014 at 10:48:05AM +0100, Thomas Wood wrote:
On 15 August 2014 10:42, Thomas Wood thomas.w...@intel.com wrote:
On 14 August 2014 17:02, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Aug 14, 2014 at 04:33:18PM +0100,
On Fri, Aug 15, 2014 at 10:22:01AM +, Daniel, Thomas wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, August 11, 2014 3:30 PM
To: Daniel, Thomas
Cc: intel-gfx@lists.freedesktop.org
Subject: Re:
On Fri, Aug 15, 2014 at 3:33 PM, Mcaulay, Alistair
alistair.mcau...@intel.com wrote:
below is the basic code path of a reset which has been changed by my patch:
i915_reset()
{
i915_gem_reset() - This used to call i915_gem_context_reset(), which
has now been removed.
We still have a few missing bits and pieces to have execlists enabled by
default eg. the error capture or the render state initialization and so
it wouldn't be wise to enable it by default on BDW just yet.
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Thomas Daniel thomas.dan...@intel.com
Summary
We covered the platform: Broadwell, Baytrail-M, Haswell (mobile, desktop and
ULT), Ivybridge, SandyBridge, IronLake.
In this circle, 3 new bugs are filed.
Bug 82611https://bugs.freedesktop.org/show_bug.cgi?id=82611 - [BDW
Regression ]HDMI hot plug case ERROR.
Bug
2014-08-15 5:39 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Thu, Aug 14, 2014 at 12:06:02PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we're runtime suspended and try to use the plane interfaces, we
will get a lot of WARNs saying we did the wrong
On Fri, Aug 1, 2014 at 2:14 PM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
The GEN6_PM* registers don't exist on BDW anymore, so when we read
this file we trigger unclaimed register errors. The equivalent BDW
register for PMs is GEN8_GT_I*R(2), so use
On Fri, Aug 15, 2014 at 01:47:18PM -0300, Paulo Zanoni wrote:
2014-08-15 5:39 GMT-03:00 Ville Syrjälä ville.syrj...@linux.intel.com:
On Thu, Aug 14, 2014 at 12:06:02PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we're runtime suspended and try to use the
Mcaulay, Alistair alistair.mcau...@intel.com writes:
Hi Mika / Daniel,
below is the basic code path of a reset which has been changed by my patch:
i915_reset()
{
i915_gem_reset() - This used to call i915_gem_context_reset(), which
has now been removed.
.
2014-08-15 13:50 GMT-03:00 Rodrigo Vivi rodrigo.v...@gmail.com:
On Fri, Aug 1, 2014 at 2:14 PM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
The GEN6_PM* registers don't exist on BDW anymore, so when we read
this file we trigger unclaimed register
On Aug-07-2014 7:27 PM, Daniel Vetter wrote:
Hi Vandana,
I think we need to start over from a freshclean slate with this part
- too much changed and all the differen revisions of this patch don't
provide that much information.
Also as Chris says this introduces yet another idleness
Chris has decided that enough is enough. It's time to fixup dev Vs
dev_priv and the, oh so awful, INTEL_INFO(). This is a modest
contribution to the crusade.
Suggested-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
From: McAulay, Alistair alistair.mcau...@intel.com
This patch is to address Daniels concerns over different code during reset:
http://lists.freedesktop.org/archives/intel-gfx/2014-June/047758.html
The reason for aiming as hard as possible to use the exact same code for
driver load, gpu reset
Hi Dave,
So you made noises that you wanted to open drm-next right after -rc1, so
I've figured I'll test this ;-)
drm-intel-next-2014-08-08:
- Setting dp M2/N2 values plus state checker support (Vandana Kannan)
- chv power well support (Ville)
- DP training pattern 3 support for chv (Ville)
-
Hi Dave,
So small drm stuff all over for 3.18. Biggest one is the cmdline parsing
from Chris with a few fixes from me to make it work for stupid kernel
configs.
Plus the atomic prep series.
Tested for more than a week in -nightly and Ville/Imre indeed discovered
some fun which is now fixed (and
Mika Kuoppala mika.kuopp...@linux.intel.com writes:
Chris Wilson ch...@chris-wilson.co.uk writes:
For stolen pages, since it is verboten to access them directly on many
architectures, we have to read them through the GTT aperture. If they
are not accessible through the aperture, then we have
Chris Wilson ch...@chris-wilson.co.uk writes:
For cleanliness, i915_error_object_create() was written to handle the
NULL pointer in a central location. The macro that wrapped it and passed
it a num_pages to use, was not safe. As we now never limit the num_pages
to use (we did so at one point
Chris Wilson ch...@chris-wilson.co.uk writes:
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
On Fri, Aug 15, 2014 at 06:34:06PM +0100, Damien Lespiau wrote:
-#define for_each_pipe(p) for ((p) = 0; (p) INTEL_INFO(dev)-num_pipes;
(p)++)
+#define for_each_pipe(dev, p) for ((p) = 0; (p) (dev)-info.num_pipes;
(p)++)
#define for_each_sprite(p, s) for ((s) = 0; (s)
From: Paulo Zanoni paulo.r.zan...@intel.com
If we're runtime suspended and try to use the plane interfaces, we
will get a lot of WARNs saying we did the wrong thing.
We need to get runtime PM references to pin the objects, and to
change the fences. The pin functions are the ideal places for
This patch just adds kms_flip_event_leak to tests/.gitignore.
Signed-off-by: Mike Mason michael.w.ma...@intel.com
---
tests/.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/.gitignore b/tests/.gitignore index d14d87b..3da061e 100644
--- a/tests/.gitignore
+++
Piglit allows multiple -t and -x regular expressions to be
given on the command line. This patch enables run-tests.sh to
support that as well.
Signed-off-by: Mike Mason michael.w.ma...@intel.com
---
scripts/run-tests.sh | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Mike Mason michael.w.ma...@intel.com
gem_mmap seg faults when all tests are run together. This occurs because
the new-object subtest closes the gem object, but short-mmap assumes
it still exists. Thus gem_mmap__cpu() returns nil for addr and memset()
seg faults. This patch makes new-object
On 08/14/2014 09:51 AM, arun.siluv...@linux.intel.com wrote:
From: Arun Siluvery arun.siluv...@linux.intel.com
The workarounds at the moment are initialized in init_clock_gating() but
they are lost during reset, suspend/resume; this patch moves workarounds
that are part of register state
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