On Tue, Sep 23, 2014 at 03:50:25PM -0700, Joe Konno wrote:
From: Joe Konno joe.ko...@intel.com
Improper integer division-- truncated rather than rounded-- in the
That's confusing. It reads that you are converting to using truncated,
rather than to rounding.
scale() function causes
On Tue, 23 Sep 2014, Michel Thierry michel.thie...@intel.com wrote:
On 9/23/2014 2:21 PM, Jani Nikula wrote:
On Wed, 17 Sep 2014, Michel Thierry michel.thie...@intel.com wrote:
On 9/17/2014 11:20 AM, Jani Nikula wrote:
FYI, Mika has posted the fix:
On Tue, 23 Sep 2014, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need
Hi,
On 09/23/2014 10:44 PM, Pali Rohár wrote:
On Tuesday 23 September 2014 22:31:31 you wrote:
Hi,
On 09/23/2014 10:06 PM, Pali Rohár wrote:
Hello,
after big changes in acpi video/i915 code I cannot change
display brightness on my Dell Latitude E6440 with kernel
3.17-rc6. With kernel
On Tue, Sep 23, 2014 at 06:05:21PM -0300, Paulo Zanoni wrote:
2014-09-16 20:19 GMT-03:00 Rodrigo Vivi rodrigo.v...@gmail.com:
We don't need to setup everything else if it doesn't match all conditions.
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
Merged the first two patches to dinq.
On Tue, Sep 23, 2014 at 02:48:47PM +0300, Jani Nikula wrote:
On Tue, 23 Sep 2014, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Sep 19, 2014 at 08:49:06PM +0300, Ville Syrjälä wrote:
On Fri, Sep 19, 2014 at 08:05:26PM +0300, Mika Kuoppala wrote:
as these have been fixed in production hw and
On Tue, Sep 23, 2014 at 08:51:09PM +, Vivi, Rodrigo wrote:
I had tried options but didn't liked because I was unable to list subtests...
so I gave back to env var...
But now I see that I was probably forgetting igt_subtest_init_parse_opts()
Please poke me next time around you want to do
On Wed, Sep 24, 2014 at 11:19:17AM +0300, Jani Nikula wrote:
On Tue, 23 Sep 2014, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.
Regards
Gaurav
Gaurav K Singh (9):
drm/i915: New functions added for enabling disabling MIPI
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 74 --
1 file changed, 48 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h|4
drivers/gpu/drm/i915/intel_bios.h |3 ++-
drivers/gpu/drm/i915/intel_dsi.c |8
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_cmd.c |9 +++--
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |3 +++
3 files changed,
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 35 ++
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 276 ++
1 file changed, 161 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c
This patch is in preparation for the dual link port enable and disable related
changes.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 43 --
1 file changed,
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_dsi.c | 53 ++--
drivers/gpu/drm/i915/intel_dsi.h |1 +
On Tue, Sep 23, 2014 at 11:06:56AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel
On Wed, Sep 24, 2014 at 02:16:49PM +0530, Gaurav K Singh wrote:
Hi,
These set of patches build on top of the existing DSI Video mode support to
enable dual link MIPI panels with high resolutions. These patches have been
tested on a 25x16 panel and works well.
Except for the first patch
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h|4
drivers/gpu/drm/i915/intel_bios.h |3 ++-
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_dsi.c | 53
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_cmd.c | 35
++
1 file changed, 23
On Wed, 24 Sep 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
Hi Dave,
Just noticed that you've picked up the header rework stuff already, so
I've rebased that out again. Otherwise just two stragglers from the vblank
rework and the universal cursor planes locking fix. Plus sprinkling
container_of all over fbdev emulation from Fabian.
Aside: I only have
Hi Jesse,
Mind looking at those review comments?
--
Damien
On Tue, Sep 23, 2014 at 05:50:29PM -0300, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
From: Jesse Barnes jbar...@virtuousgeek.org
This moved around on SKL, so we need to make sure we
Following the legacy ring submission example, update the
ring-init_context() hook to support the execlist submission mode.
Workarounds are defined in bdw_emit_workarounds(), but the emit
now depends on the ring submission mode.
v2: Updated after Cleanup pre prod workarounds
For: VIZ-4092
Also enable the ring-init_context() hook for chv in execlist submission
mode.
For: VIZ-4092
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c| 37 ++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 39
Hi,
On 09/24/2014 11:14 AM, Pali Rohár wrote:
On Wednesday 24 September 2014 10:59:41 Pali Rohár wrote:
On Wednesday 24 September 2014 10:19:38 Hans de Goede wrote:
Hi,
On 09/23/2014 10:44 PM, Pali Rohár wrote:
On Tuesday 23 September 2014 22:31:31 you wrote:
Hi,
On 09/23/2014 10:06 PM,
Hi Daniel Chris,
Thank you very much for your comments, And sorry for my late reply.:)
I was focusing on other tasks previously.
See my questions below:
On 9/23/2014 7:25 PM, Daniel Vetter wrote:
On Tue, Sep 23, 2014 at 10:19:02AM +0100, Chris Wilson wrote:
On Tue, Sep 23, 2014 at
From: Armin Reese armin.c.re...@intel.com
Modifications to 'null_state_gen' so it can generate GEN9
golden context batch buffer source for SKL.
v2: - rebased on top of gen8 changes (Mika)
- fixed state base address command size (Mika)
- base address size macro as pages (Mika)
In null/golden context there are multiple state commands where
the actual state is always zero. For more compact batch representation
add a macro which just emits command and the rest of the state as zero.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
Previously we didn't have a clear understanding what is necessary
for a pipeline state to be properly initialized. So we had to improvise
and use a stripped out render copy.
Now we have a more clear understanding so switch out render copy based
frankenstate to state we can call golden state.
---
https://github.com/UmbraMalison/qemu-igdvfio
Hi all,
I am publishing my work on IGD Direct Assignment in a semi-working state as
I need some help from the community to finish these. It may also be a good
time to take in comments from the community.
There has been an increased interest in IGD DA
hw/isa/lpc_ich9.c
this patch adds:
* debug output, if enabled
* enforces correct intel config, if enabled. (unsure if this is needed)
* redirects some PCI Config to host
* uses hosts LPC device id
patch
-
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index
hw/misc/vfio.c
this patch adds:
* memory map intel opregion
* mirroring of bdsm to guest's device 0 not hosts.
patch
-
diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c
index e88b610..54e549b 100644
--- a/hw/misc/vfio.c
+++ b/hw/misc/vfio.c
@@ -5,6 +5,7 @@
*
* Authors:
*
hw/pci-host/q35.c
this patch adds:
* redirect some PCI config reads/writes to host
* memory map BSDM, BGSM, TSEG
patch
-
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index a0a3068..05348ac 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -6,6 +6,7 @@
*
include/hw/pci/pci_ids.h
A very last minute realisation is that this is not needed. Its purpose is
to make sure anything else that references LPC device ID is given the
hacked-in host's ID. but in verifying the patch validity it appears this
not referenced anywhere, other than where its taken
include/hw/pci-host/q35.h
this patch adds:
* #defines for q35 pci config. not all are used, added for completeness
patch
-
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index d9ee978..abb795e 100644
--- a/include/hw/pci-host/q35.h
+++
Seabios patch
This patch covers all the changes to seabios. The intentions are to make
seabios behave like the hosts BIOS. and like the hosts BIOS, configure the
Q35 chipset more thoroughly.
This patch configures TOM, TOUUD, TOLUD, BDSM, BGSM, TSEG, IGD-OPREGION.
by writing new base addresses,
hw/pci/pci.c
this patch adds:
* read / write host PCI config space
patch
-
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 42995e6..041f6f1 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2,6 +2,8 @@
* QEMU PCI bus manager
*
* Copyright (c) 2004 Fabrice Bellard
+ *
include/hw/pci/pci.h
patch
-
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index c352c7b..d3bc224 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -338,6 +338,9 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque,
int pin);
#define PCI_BUS(obj)
On Wed, Sep 24, 2014 at 08:35:50PM +0800, Zhang, Yu wrote:
Hi Daniel Chris,
Thank you very much for your comments, And sorry for my late
reply.:) I was focusing on other tasks previously.
See my questions below:
On 9/23/2014 7:25 PM, Daniel Vetter wrote:
On Tue, Sep 23, 2014 at
On Wed, Sep 24, 2014 at 08:35:50PM +0800, Zhang, Yu wrote:
Hi Daniel Chris,
Thank you very much for your comments, And sorry for my late reply.:) I
was focusing on other tasks previously.
See my questions below:
On 9/23/2014 7:25 PM, Daniel Vetter wrote:
On Tue, Sep 23, 2014 at
Damien Lespiau damien.lesp...@intel.com writes:
From: Zhe Wang zhe1.w...@intel.com
For MMIO registers which are shadowed, force wake is not needed to
write to these registers.
v2: Rebase on top of nightly (Damien)
Signed-off-by: Zhe Wang zhe1.w...@intel.com
Signed-off-by: Damien Lespiau
Reading timestamp register using I915_READ64 returns incorrect value.
Unfortunately, that's how I915_REG_READ ioctl is handling it on x86_64,
resulting in different counter size (we can only get 32 usable bits on
x86_64 vs 36 bits on x86).
Propose new sysfs interface for accessing full 36 bits of
2014-09-16 20:19 GMT-03:00 Rodrigo Vivi rodrigo.v...@gmail.com:
The panel has to be reconfigured only when it really loose the power.
The traditional enable/disable sequence already take care of this so we can
minimize the time spend on every re-enable.
Reviewed-by: Paulo Zanoni
On Fri, Sep 19, 2014 at 01:05:02PM +0300, Ville Syrjälä wrote:
If we're going to be paranoid I think we should disable all higher WM
levels whose latency is lower than any of the lower levels. And I
think we'll want something like dev_priv-wm.max_wm_level instead of
relying on the zero
Hi,
On 09/24/2014 02:53 PM, Pali Rohár wrote:
On Wednesday 24 September 2014 14:04:36 Hans de Goede wrote:
Hi,
On 09/24/2014 11:14 AM, Pali Rohár wrote:
On Wednesday 24 September 2014 10:59:41 Pali Rohár wrote:
On Wednesday 24 September 2014 10:19:38 Hans de Goede wrote:
Hi,
On
[meta-comment]
On 09/24/2014 07:20 AM, Andrew Barnes wrote:
hw/isa/lpc_ich9.c
Your patches came through unthreaded (mail 1 through 8 are all lacking
In-Reply-To the message id of 0/8,
CAKJ_wKTVEzT3HeFHJg=pd6qbnrnrquwbeirvmykqsqnrpzr...@mail.gmail.com).
This makes it harder to review. You may
On Wed, Sep 24, 2014 at 03:41:08PM +0200, Michał Winiarski wrote:
Reading timestamp register using I915_READ64 returns incorrect value.
Unfortunately, that's how I915_REG_READ ioctl is handling it on x86_64,
resulting in different counter size (we can only get 32 usable bits on
x86_64 vs 36
2014-09-23 Ville Syrjälä ville.syrj...@linux.intel.com:
On Mon, Sep 22, 2014 at 07:23:10PM -0300, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Move checks inside intel_crtc_cursor_set_obj() to
intel_check_cursor_plane(), we only use they there so move
On Tuesday 23 September 2014 22:31:31 you wrote:
Hi,
On 09/23/2014 10:06 PM, Pali Rohár wrote:
Hello,
after big changes in acpi video/i915 code I cannot change
display brightness on my Dell Latitude E6440 with kernel
3.17-rc6. With kernel 3.13 everything worked fine.
More
On Wednesday 24 September 2014 10:19:38 Hans de Goede wrote:
Hi,
On 09/23/2014 10:44 PM, Pali Rohár wrote:
On Tuesday 23 September 2014 22:31:31 you wrote:
Hi,
On 09/23/2014 10:06 PM, Pali Rohár wrote:
Hello,
after big changes in acpi video/i915 code I cannot change
display
On Wednesday 24 September 2014 10:59:41 Pali Rohár wrote:
On Wednesday 24 September 2014 10:19:38 Hans de Goede wrote:
Hi,
On 09/23/2014 10:44 PM, Pali Rohár wrote:
On Tuesday 23 September 2014 22:31:31 you wrote:
Hi,
On 09/23/2014 10:06 PM, Pali Rohár wrote:
Hello,
Hello,
after big changes in acpi video/i915 code I cannot change display
brightness on my Dell Latitude E6440 with kernel 3.17-rc6. With
kernel 3.13 everything worked fine.
More information about this problem:
For configuring brightness on Dell laptops there are 4 ways:
1) via acpi video
On Wednesday 24 September 2014 14:04:36 Hans de Goede wrote:
Hi,
On 09/24/2014 11:14 AM, Pali Rohár wrote:
On Wednesday 24 September 2014 10:59:41 Pali Rohár wrote:
On Wednesday 24 September 2014 10:19:38 Hans de Goede wrote:
Hi,
On 09/23/2014 10:44 PM, Pali Rohár wrote:
On
2014-09-17 14:23 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
Let's make sure PSR is propperly disabled before to re-enabled it.
According to Spec, after disabled PSR CTL, the Idle state might occur
up to 24ms, that is one full frame time (1/refresh rate),
plus SRD exit training time (max
Many thanks, Chris. I'll incorporate your feedback into v2.
On 09/23/2014 11:04 PM, Chris Wilson wrote:
On Tue, Sep 23, 2014 at 03:50:25PM -0700, Joe Konno wrote:
From: Joe Konno joe.ko...@intel.com
Improper integer division-- truncated rather than rounded-- in the
That's confusing. It reads
From: Joe Konno joe.ko...@intel.com
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
sufficient for a majority of use-cases, but it is by no means a complete
solution.
TODO: Determine how best to scale user
On 09/24/2014 01:51 AM, Daniel Vetter wrote:
On Tue, Sep 23, 2014 at 11:06:56AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition
Hi,
On 09/24/2014 05:54 PM, Joe Konno wrote:
From: Joe Konno joe.ko...@intel.com
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
sufficient for a majority of use-cases, but it is by no means a complete
On Wed, Sep 24, 2014 at 6:24 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Hi Dave,
Just noticed that you've picked up the header rework stuff already, so
I've rebased that out again. Otherwise just two stragglers from the vblank
rework and the universal cursor planes locking fix. Plus
On 09/24/2014 07:20 AM, Andrew Barnes wrote:
hw/isa/lpc_ich9.c
this patch adds:
* debug output, if enabled
* enforces correct intel config, if enabled. (unsure if this is needed)
* redirects some PCI Config to host
* uses hosts LPC device id
patch
-
Stylistic
Use the new pm_runtime_last_busy_and_autosuspend helper instead of open
coding the same code
Signed-off-by: Vinod Koul vinod.k...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
This patch series adds a simple macro pm_runtime_last_busy_and_autosuspend()
which invokes pm_runtime_mark_last_busy() and pm_runtime_put_autosuspend()
sequentially. Then we do a tree wide update of current patterns which are
present. As evident from log below this pattern is frequent in the
Hi Dave, a couple of small fixes for 3.17 still.
BR,
Jani.
The following changes since commit 0f33be009b89d2268e94194dc4fd01a7851b6d51:
Linux 3.17-rc6 (2014-09-21 15:43:02 -0700)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel
On Wed, 24 Sep 2014, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 09/24/2014 05:54 PM, Joe Konno wrote:
From: Joe Konno joe.ko...@intel.com
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Move check inside intel_crtc_cursor_set_obj() to
intel_check_cursor_plane(), we only use it there so move them out to
make the merge of intel_crtc_cursor_set_obj() into
intel_check_cursor_plane() easier.
This is another step toward the atomic
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Merge it into the plane update_plane() callback and make other
users use the update_plane() functions instead.
The fb != crtc-cursor-fb was already inside intel_crtc_cursor_set_obj()
so we fold intel_crtc_cursor_set_obj() inside
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Even if the fb is the same we should still check if the sizes are
valid to be set.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/i915/intel_display.c | 61
1 file
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
We need to get hdisplay and vdisplay in a few places so create a
helper to make our job easier.
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Use the macros makes the code cleaner and it also checks for a NULL fb.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/i915/intel_sprite.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Now that universal planes are in place we don't need this plane unref on
failures.
Suggested-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
Reviewed-by: Ville Syrjälä
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Fold intel_pipe_set_base() in the update primary plane path merging
pieces of code that are common to both paths.
Basically the the pin/unpin procedures are the same for both paths
and some checks can also be shared (some of the were moved to
From: Daniel Stone dani...@collabora.com
Start the work of splitting the intel_crtc_page_flip() for later use
by the atomic modesetting API.
Signed-off-by: Daniel Stone dani...@collabora.com
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/i915/intel_display.c
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
After some refactor intel_primary_plane_setplane() does the same
as intel_pipe_set_base() so we can get rid of it and replace the calls
with intel_primary_plane_setplane().
v2: take Ville's comments:
- get the right arguments for
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
take out pin_fb code so the commit phase can't fail anymore.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/i915/intel_sprite.c | 63 +++--
1 file changed, 40 insertions(+),
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Take out the pin_fb code so commit phase can't fail anymore.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/i915/intel_display.c | 35 ++-
1 file changed, 26 insertions(+),
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Jani Nikula
Sent: Wednesday, September 24, 2014 10:08 AM
To: Hans de Goede; Joe Konno; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: intel_backlight scale()
Oh just noticed we duplicated effort on this.. [5/5] drm/i915/bdw: Remove
BDW preproduction W/As until C stepping.
After this land -nightly I rebase my series on top.
On Wed, Sep 24, 2014 at 1:41 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Sep 23, 2014 at 02:48:47PM +0300, Jani Nikula
On Wed, Sep 24, 2014 at 6:24 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Wed, Sep 24, 2014 at 6:24 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Hi Dave,
Just noticed that you've picked up the header rework stuff already, so
I've rebased that out again. Otherwise just two stragglers from
On Wednesday 24 September 2014 16:34:21 Hans de Goede wrote:
Hi,
On 09/24/2014 02:53 PM, Pali Rohár wrote:
On Wednesday 24 September 2014 14:04:36 Hans de Goede wrote:
Hi,
On 09/24/2014 11:14 AM, Pali Rohár wrote:
On Wednesday 24 September 2014 10:59:41 Pali Rohár wrote:
On
On Wed, Sep 24, 2014 at 09:44:54PM +0530, Vinod Koul wrote:
Use the new pm_runtime_last_busy_and_autosuspend helper instead of open
coding the same code
Signed-off-by: Vinod Koul vinod.k...@intel.com
Ack to merge through whatever tree is appropriate for this. Or tell me
when I should pick
On Wed, 2014-09-24 at 14:20 +0100, Andrew Barnes wrote:
hw/isa/lpc_ich9.c
this patch adds:
* debug output, if enabled
* enforces correct intel config, if enabled. (unsure if this is needed)
* redirects some PCI Config to host
* uses hosts LPC device id
patch
-
On Wed, Sep 24, 2014 at 12:40:20PM -0300, Paulo Zanoni wrote:
2014-09-17 14:23 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
Let's make sure PSR is propperly disabled before to re-enabled it.
According to Spec, after disabled PSR CTL, the Idle state might occur
up to 24ms, that is one
On Wed, Sep 24, 2014 at 05:50:30AM -0700, Mika Kuoppala wrote:
In null/golden context there are multiple state commands where
the actual state is always zero. For more compact batch representation
add a macro which just emits command and the rest of the state as zero.
Signed-off-by: Mika
On Wed, 2014-09-24 at 14:20 +0100, Andrew Barnes wrote:
hw/misc/vfio.c
this patch adds:
* memory map intel opregion
* mirroring of bdsm to guest's device 0 not hosts.
patch
-
diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c
index e88b610..54e549b 100644
---
On Wed, Sep 24, 2014 at 08:44:42AM -0700, Clint Taylor wrote:
On 09/24/2014 01:51 AM, Daniel Vetter wrote:
On Tue, Sep 23, 2014 at 11:06:56AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication
On Wed, Sep 24, 2014 at 12:24:53PM +0200, Daniel Vetter wrote:
Hi Dave,
Just noticed that you've picked up the header rework stuff already, so
I've rebased that out again. Otherwise just two stragglers from the vblank
rework and the universal cursor planes locking fix. Plus sprinkling
On Wed, 2014-09-24 at 14:20 +0100, Andrew Barnes wrote:
hw/pci-host/q35.c
this patch adds:
* redirect some PCI config reads/writes to host
* memory map BSDM, BGSM, TSEG
patch
-
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index a0a3068..05348ac 100644
---
On Wed, 2014-09-24 at 14:20 +0100, Andrew Barnes wrote:
hw/pci/pci.c
this patch adds:
* read / write host PCI config space
patch
-
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 42995e6..041f6f1 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2,6 +2,8 @@
*
Paulo Zanoni reported a lockdep splat with a locking inversion between
fpriv-fbs_lock and the modeset locks. This issue was introduced in
commit f2b50c1161590c3bcdbf3455fe4c575f1c1bd293
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Fri Sep 12 17:07:32 2014 +0200
drm: Fixup locking for
On Wednesday, September 24, 2014 09:44:50 PM Vinod Koul wrote:
This patch series adds a simple macro pm_runtime_last_busy_and_autosuspend()
which invokes pm_runtime_mark_last_busy() and pm_runtime_put_autosuspend()
sequentially. Then we do a tree wide update of current patterns which are
On Wednesday, September 24, 2014 03:15:58 PM Felipe Balbi wrote:
On Wed, Sep 24, 2014 at 10:28:07PM +0200, Rafael J. Wysocki wrote:
On Wednesday, September 24, 2014 09:44:50 PM Vinod Koul wrote:
This patch series adds a simple macro
pm_runtime_last_busy_and_autosuspend()
which invokes
2014-09-24 16:55 GMT-03:00 Daniel Vetter daniel.vet...@ffwll.ch:
Paulo Zanoni reported a lockdep splat with a locking inversion between
fpriv-fbs_lock and the modeset locks. This issue was introduced in
commit f2b50c1161590c3bcdbf3455fe4c575f1c1bd293
Author: Daniel Vetter
Il 24/09/2014 21:47, Alex Williamson ha scritto:
So the opregion is mapped by a config write on the IGD device itself and
the other 3 regions, that we know about so far, are mapped via writes to
the host bridge.
AFAIU the opregion is mapped by the (host) BIOS, that writes the address
to a
On Wed, 2014-09-24 at 22:31 +0200, Paolo Bonzini wrote:
Il 24/09/2014 21:47, Alex Williamson ha scritto:
So the opregion is mapped by a config write on the IGD device itself and
the other 3 regions, that we know about so far, are mapped via writes to
the host bridge.
AFAIU the opregion
I went through and compared this against both the spec (the state commands
listed in 3D-Media-GPGPU chapter 3D Pipeline Stages section) and the other
information I've seen on recommended setup, and as far as I can tell this
looks good. It still might be worth getting another set of eyes on this,
On 25 September 2014 03:59, Daniel Vetter daniel.vet...@ffwll.ch wrote:
On Wed, Sep 24, 2014 at 6:24 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Wed, Sep 24, 2014 at 6:24 AM, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
Hi Dave,
Just noticed that you've picked up the header rework stuff
1 - 100 of 116 matches
Mail list logo
