Re: [Intel-gfx] i915 and 1440p display w/ corrupt EDID

On Wed, 24 Sep 2014, Mathias Burén mathias.bu...@gmail.com wrote: I've a 1440p display with a non-sufficient/corrupt EDID. Just to double check, you mean the display really is broken in this regard, *not* that the driver is unable to read the EDID? Does your monitor have other connections than

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

Hi Chris Daniel, Thanks for your comments. Following are my understandings about the changes needed for this patch: 1 We do not need the guard page anymore between different VMs. For the very last physical GTT entry, let's keep it pointing to a guard page. 2 To reserve the GMs in our

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

On Fri, Sep 26, 2014 at 04:26:20PM +0800, Zhang, Yu wrote: Hi Chris Daniel, Thanks for your comments. Following are my understandings about the changes needed for this patch: 1 We do not need the guard page anymore between different VMs. For the very last physical GTT entry, let's keep

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Adds graphic address space ballooning logic

On 9/26/2014 4:48 PM, Chris Wilson wrote: On Fri, Sep 26, 2014 at 04:26:20PM +0800, Zhang, Yu wrote: Hi Chris Daniel, Thanks for your comments. Following are my understandings about the changes needed for this patch: 1 We do not need the guard page anymore between different VMs. For the

[Intel-gfx] [PATCH 1/2] lib/igt_core: make single/simple tests use igt_exit

From: Tim Gore tim.g...@intel.com Currently tests that use igt_simple_main will simply call exit() if they pass, making it difficult to ensure that any required cleanup is done. At present this is not an issue, but it will be when I submit a patch to turn off the lowmemorykiller for all tests.

[Intel-gfx] [PATCH 0/2] Disable Android low memory killer

From: Tim Gore tim.g...@intel.com For some tests that put pressure on memory, the Android lowmemorykiller needs to be disabled for the test to run to completion. The first patch is a simple bit of preparation to ensure that all (well written) simple tests exit via a call to igt_exit, in the same

[Intel-gfx] [PATCH] drm/i915: Do not store the error pointer for a failed userptr registration

If we fail to create our mmu notification, we report the error back and currently store the error inside the i915_mm_struct. This not only causes subsequent registerations of the same mm to fail (an issue if the first was interrupted by a signal and needed to be restarted) but also causes us to

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:27:22AM +0100, tim.g...@intel.com wrote: From: Tim Gore tim.g...@intel.com For some tests that put pressure on memory, the Android lowmemorykiller needs to be disabled for the test to run to completion. The first patch is a simple bit of preparation to ensure that

Re: [Intel-gfx] [PATCH] drm/i915: Do not store the error pointer for a failed userptr registration

On 09/26/2014 10:31 AM, Chris Wilson wrote: If we fail to create our mmu notification, we report the error back and currently store the error inside the i915_mm_struct. This not only causes subsequent registerations of the same mm to fail (an issue if the first was interrupted by a signal and

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

-Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, September 26, 2014 10:50 AM To: Gore, Tim Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer On Fri, Sep 26, 2014 at 10:27:22AM +0100,

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:08:54AM +, Gore, Tim wrote: -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, September 26, 2014 10:50 AM To: Gore, Tim Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 0/2] Disable

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:08:54AM +, Gore, Tim wrote: I don't think so. This is really just about the Android low memory killer having Different goals to kswapd. Kswapd tries to keep a certain amount of free memory so that the kernel can run smoothly. On Android the lowmemorykiller

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

-Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, September 26, 2014 11:30 AM To: Gore, Tim Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer On Fri, Sep 26, 2014 at 10:08:54AM +,

Re: [Intel-gfx] [PATCH 0/2] Disable Android low memory killer

On Fri, Sep 26, 2014 at 10:46:48AM +, Gore, Tim wrote: -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, September 26, 2014 11:30 AM To: Gore, Tim Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 0/2] Disable

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default

Rodrigo Vivi rodrigo.v...@intel.com writes: Program the default initial value of the L3SqcReg1 on BDW for performance Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 3 +++ 2 files changed, 6 insertions(+)

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

Rodrigo Vivi rodrigo.v...@intel.com writes: This helps when including or removing cs workarounds. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

On Fri, 26 Sep 2014, Mika Kuoppala mika.kuopp...@linux.intel.com wrote: Rodrigo Vivi rodrigo.v...@intel.com writes: This helps when including or removing cs workarounds. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/intel_ringbuffer.c | 16 1

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

On Fri, Sep 26, 2014 at 03:56:02PM +0300, Jani Nikula wrote: On Fri, 26 Sep 2014, Mika Kuoppala mika.kuopp...@linux.intel.com wrote: Rodrigo Vivi rodrigo.v...@intel.com writes: This helps when including or removing cs workarounds. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com ---

[Intel-gfx] [PATCH libdrm 2/3] intel/skl: Add gen9 to the buffer manager init

Signed-off-by: Damien Lespiau damien.lesp...@intel.com Reviewed-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- intel/intel_bufmgr_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index

[Intel-gfx] [PATCH libdrm 1/3] intel/skl: Add SKL PCI ids

v2: Add more PCI IDs (Michael H. Nguyen) v3: Synchronize one more with the kernel PCI IDs (Damien) Signed-off-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Michael H. Nguyen michael.h.ngu...@intel.com --- intel/intel_chipset.h

[Intel-gfx] [PATCH i-g-t 07/26] rendercopy/skl: Update 3DSTATE_SBE

SBE has now to be explicitely told which channels of which components are used by the pixel shader. Signed-off-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com --- lib/gen9_render.h | 5 + lib/rendercopy_gen9.c | 4 +++- 2 files changed,

[Intel-gfx] [PATCH i-g-t 14/26] rendercopy/skl: Follow the spec to add the Pipeline selection mask

From: Zhao Yakui yakui.z...@intel.com Reviewed-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- lib/gen9_render.h | 2 ++

[Intel-gfx] [PATCH i-g-t 01/26] skl: Add SKL PCI ids

v2: Update to the latest PCI ids Signed-off-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com --- lib/intel_chipset.h | 58 +++-- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git

[Intel-gfx] [PATCH i-g-t 08/26] rendercopy/skl: Pass the context to rendercopy function on SKL

From: Zhao Yakui yakui.z...@intel.com Reviewed-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com --- lib/rendercopy.h | 1 + lib/rendercopy_gen9.c | 12 +++-

[Intel-gfx] [PATCH i-g-t 03/26] skl: initialize instdone bits for gen9

gen9 uses the same bits as gen8. Signed-off-by: Damien Lespiau damien.lesp...@intel.com Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- lib/instdone.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/lib/instdone.c

[Intel-gfx] [PATCH i-g-t 15/26] rendercopy/skl: Set the URB VS start address to 4

From: Xiang, Haihao haihao.xi...@intel.com A value less than 4 might result in GPU hang on simulation Signed-off-by: Xiang, Haihao haihao.xi...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@linux.intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com ---

[Intel-gfx] [PATCH i-g-t 02/26] skl: Add gen9 to intel_gen()

Signed-off-by: Damien Lespiau damien.lesp...@intel.com Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- lib/intel_chipset.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c index 0828e44..fafd232

[Intel-gfx] [PATCH i-g-t 04/26] list-workarounds/skl: Add Skylake to the list of valid platorms

Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- scripts/list-workarounds | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/list-workarounds b/scripts/list-workarounds index 5a84ee8..620d02f 100755 --- a/scripts/list-workarounds +++ b/scripts/list-workarounds

[Intel-gfx] [PATCH i-g-t 09/26] rendercopy/skl: update instruction length

From: Zhao Yakui yakui.z...@intel.com This is ported from that on BDW. v2: Only bump the prefix when we need to program the instruction differently with the previous generations. Reviewed-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by:

[Intel-gfx] [PATCH i-g-t 16/26] assembler/skl: Add gen 9 to the -g option

Signed-off-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Ben Widawsky b...@bwidawsk.net Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- assembler/disasm-main.c | 4 ++-- assembler/main.c| 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH i-g-t 12/26] rendercopy/skl: Fix the 3DSTATE_DS instruction length

From: Zhao Yakui yakui.z...@intel.com Reviewed-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- lib/rendercopy_gen9.c | 8 +--- 1 file

[Intel-gfx] [PATCH i-g-t 13/26] rendercopy/skl: Emit 3DSTATE_WM_HZ_OP

From: Zhao Yakui yakui.z...@intel.com This is from that on BDW. Without it, the pixel pipeline can't work well. Reviewed-by: Damien Lespiau damien.lesp...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien

[Intel-gfx] [PATCH i-g-t 23/26] mediafill/skl: Follow the spec to add pipeline_select mask

From: Zhao Yakui yakui.z...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- lib/gen8_media.h | 3 +++ lib/media_fill_gen9.c | 3 ++- 2 files changed, 5 insertions(+),

[Intel-gfx] [PATCH i-g-t 17/26] assembler/skl: Redefine the cache agent type for some fixed functions

From: Zhao Yakui yakui.z...@intel.com The different cache agent type is defined for SKL although it still uses the same function ID as the previous generations. Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau

[Intel-gfx] [PATCH i-g-t 19/26] assembler/skl: Add more cache agent for write(...)

From: Zhao Yakui yakui.z...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- assembler/gram.y | 40 ++-- 1 file changed, 30

[Intel-gfx] [PATCH i-g-t 20/26] assembler/skl: update the extdesc field for SEND instruction

From: Zhao Yakui yakui.z...@intel.com The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate for the extended message descriptors. And some bits of SEND instruction are defined as the extdesc field. Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben

[Intel-gfx] [PATCH i-g-t 24/26] mediafill/skl: Follow spec to configure FORCE_MEDIA_AWAKE in PIPELINE_SELECTION

From: Zhao Yakui yakui.z...@intel.com The FORCE_MEDIA_AWAKE bit is added for the PIPELINE_SELECTION command and some instructions requires that the media enginee is awake. Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien

[Intel-gfx] [PATCH i-g-t 22/26] mediafill/skl: follow the spec to update STATE_BASE_ADDRESS command

From: Zhao Yakui yakui.z...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- lib/media_fill_gen9.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff

[Intel-gfx] [PATCH i-g-t 25/26] mediafill/skl: Follow spec to configure media sampler DOP clock gating in PIPELINE_SELECTION

From: Zhao Yakui yakui.z...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- lib/gen8_media.h | 4 lib/media_fill_gen9.c | 4 2 files changed, 8 insertions(+)

[Intel-gfx] [PATCH i-g-t 21/26] mediafill/skl: Start the gen9 media_fill from the gen8 version

From: Zhao Yakui yakui.z...@intel.com Signed-off-by: Zhao Yakui yakui.z...@intel.com Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- lib/Makefile.sources | 1 + lib/media_fill.c | 16 +++ lib/media_fill.h | 7 +

[Intel-gfx] [PATCH i-g-t 26/26] lib/skl: Return the render copy and media fill functions

From: Xiang, Haihao haihao.xi...@intel.com Signed-off-by: Xiang, Haihao haihao.xi...@intel.com [Ben: Reordered if tree] Signed-off-by: Ben Widawsky benjamin.widaw...@linux.intel.com Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- lib/intel_batchbuffer.c | 6 +- 1 file changed, 5

[Intel-gfx] [PATCH i-g-t 18/26] assembler/skl: update read(...)

From: Zhao Yakui yakui.z...@intel.com READ(...) is used for Render Target read and Media Block read. But there is no sampler cache agent on gen9. At the same time two message types don't share the same cache agent any more. So a parameter is needed for cache agent. The 2th parameter of read(...)

[Intel-gfx] [PATCH] drm/i915: Do not leak pages when freeing userptr objects

From: Tvrtko Ursulin tvrtko.ursu...@intel.com sg_alloc_table_from_pages() can build us a table with coalesced ranges which means we need to iterate over pages and not sg table entries when releasing page references. Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com Cc: Chris Wilson

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

Jani Nikula jani.nik...@linux.intel.com writes: On Fri, 26 Sep 2014, Mika Kuoppala mika.kuopp...@linux.intel.com wrote: Rodrigo Vivi rodrigo.v...@intel.com writes: This helps when including or removing cs workarounds. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com ---

Re: [Intel-gfx] [PATCH] drm/i915: Do not leak pages when freeing userptr objects

-Original Message- From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] Sent: Friday, September 26, 2014 3:05 PM To: Intel-gfx@lists.freedesktop.org Cc: Ursulin, Tvrtko; Chris Wilson; Barbalho, Rafael Subject: [PATCH] drm/i915: Do not leak pages when freeing userptr objects

[Intel-gfx] [QA 09/26 ww39] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platform: BSW, Broadwell, Baytrail-M, Haswell, Ivybridge, SandyBridge, IronLake. We involved BSW first time. Basically HDMI/DP works, and eDP doesn't works for a regression issue. In this circle, 5 new bugs are filed. Bug

Re: [Intel-gfx] [PATCH 84/89] drm/i915/skl: add turbo support

Damien Lespiau damien.lesp...@intel.com writes: From: Jesse Barnes jbar...@virtuousgeek.org Per latest PM programming guide. v2: the wrong flavour of the function updating the ring frequency was called, leading to dead locks (Tvrtko) Signed-off-by: Jesse Barnes

Re: [Intel-gfx] [PATCH] drm/i915: Do not leak pages when freeing userptr objects

On Fri, Sep 26, 2014 at 03:05:22PM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin tvrtko.ursu...@intel.com sg_alloc_table_from_pages() can build us a table with coalesced ranges which means we need to iterate over pages and not sg table entries when releasing page references.

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Let number of workarounds more clear

On Fri, Sep 26, 2014 at 05:16:57PM +0300, Mika Kuoppala wrote: Jani Nikula jani.nik...@linux.intel.com writes: On Fri, 26 Sep 2014, Mika Kuoppala mika.kuopp...@linux.intel.com wrote: Rodrigo Vivi rodrigo.v...@intel.com writes: This helps when including or removing cs workarounds.

Re: [Intel-gfx] [PATCH 85/89] drm/i915/skl: Retrieve the frequency limits

Damien Lespiau damien.lesp...@intel.com writes: Signed-off-by: Damien Lespiau damien.lesp...@intel.com Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c

Re: [Intel-gfx] [PATCH 87/89] drm/i915/skl: AUX irqs have moved

Damien Lespiau damien.lesp...@intel.com writes: From: Jesse Barnes jbar...@virtuousgeek.org Use the new AUX port irq bits where needed. v2: Rebase on top of upstream changes v3: Rebase on top of Oscar change to write IIR as soon as possible (Damien) v4: Rebase on top of the for_each_pipe()

Re: [Intel-gfx] [PATCH 89/89] drm/i915/skl: Disable contexts if execlists aren't enabled

Damien Lespiau damien.lesp...@intel.com writes: We were hiting a BUG() in get_context_size() with execlist disabled. legacy contexts are not supported on gen9 so we don't have a gen9 specific size to add in there. Instead, let's disable legacy contexts altogether on gen9, whether we're

Re: [Intel-gfx] [PATCH 89/89] drm/i915/skl: Disable contexts if execlists aren't enabled

On Fri, Sep 26, 2014 at 06:28:53PM +0300, Mika Kuoppala wrote: Damien Lespiau damien.lesp...@intel.com writes: We were hiting a BUG() in get_context_size() with execlist disabled. legacy contexts are not supported on gen9 so we don't have a gen9 specific size to add in there. Instead,

[Intel-gfx] [PATCH i-g-t] kms_cursor_crc: Remove two unused local variables

Signed-off-by: Damien Lespiau damien.lesp...@intel.com --- tests/kms_cursor_crc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index 718699d..c348d7a 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -79,7 +79,6 @@ static

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel clock. port_clock was set to 27.026

Re: [Intel-gfx] [PATCH v2] drm/i915: Audio N value computed for pixel doubled modes

On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com HDMI audio clock config was incorrectly choosing the default for pixel doubled interlaced modes. The table was missing pixel clock values 13.500 (27.000) and 13.513

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On 09/26/2014 08:58 AM, Ville Syrjälä wrote: On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel

Re: [Intel-gfx] [PATCH] drm/i915/hdmi: Compute port_clock for 27.027 pixel replicated modes

On 09/26/2014 08:58 AM, Ville Syrjälä wrote: On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com port_clock was being incorrectly computed and WRPLL was incorrectly programmed for pixel doubled modes using a 27.027MHz pixel

[Intel-gfx] [PATCH] drm/edid: Add missing interlaced flag to 576i@100 modes.

From: Clint Taylor clinton.a.tay...@intel.com CEA VICs 44 and 45 were missing DRM_MODE_FLAG_INTERLACE. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com --- drivers/gpu/drm/drm_edid.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c

Re: [Intel-gfx] [PATCH] drm/i915: intel_backlight scale() math WA v2

-Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Joe Konno Sent: Wednesday, September 24, 2014 8:55 AM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH] drm/i915: intel_backlight scale() math WA v2 From: Joe Konno

[Intel-gfx] [PATCH] drm/i915: Organize HSW and BDW Forcewake MT Ack.

0x130040 is actually a LCPLL_CTL and never was a Forcewake MT Ack. The fixed value was introduced but the wrong one was never removed. So let's clean the code and definitions a bit. Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +--

Re: [Intel-gfx] [PATCH] drm/edid: Add missing interlaced flag to 576i@100 modes.

On Fri, Sep 26, 2014 at 09:55:24AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com CEA VICs 44 and 45 were missing DRM_MODE_FLAG_INTERLACE. Signed-off-by: Clint Taylor clinton.a.tay...@intel.com Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com

Re: [Intel-gfx] [PATCH] drm/i915: Organize HSW and BDW Forcewake MT Ack.

On Fri, Sep 26, 2014 at 01:15:26PM -0400, Rodrigo Vivi wrote: 0x130040 is actually a LCPLL_CTL and never was a Forcewake MT Ack. The fixed value was introduced but the wrong one was never removed. So let's clean the code and definitions a bit. NAK. 0x130040 is the forcewake MT ack on IVB.

Re: [Intel-gfx] [PATCH] drm/i915: Organize HSW and BDW Forcewake MT Ack.

oh true. Please just ignore it... On Fri, Sep 26, 2014 at 11:12 AM, Ville Syrjälä ville.syrj...@linux.intel.com wrote: On Fri, Sep 26, 2014 at 01:15:26PM -0400, Rodrigo Vivi wrote: 0x130040 is actually a LCPLL_CTL and never was a Forcewake MT Ack. The fixed value was introduced but the

Re: [Intel-gfx] [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default

On Fri, Sep 26, 2014 at 03:03:19PM +0300, Mika Kuoppala wrote: Rodrigo Vivi rodrigo.v...@intel.com writes: Program the default initial value of the L3SqcReg1 on BDW for performance Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++

Re: [Intel-gfx] [PATCH] ACPI / i915: Update the condition to ignore firmware backlight change request

On Friday, September 26, 2014 10:30:08 AM Aaron Lu wrote: Some of the Thinkpads' firmware will issue a backlight change request through i915 operation region unconditionally on AC plug/unplug, the backlight level used is arbitrary and thus should be ignored. This is handled by commit

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW.

On 09/26/2014 09:38 AM, Ville Syrjälä wrote: On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor clinton.a.tay...@intel.com Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition