On Mon, Sep 29, 2014 at 03:39:06PM -0700, Todd Previte wrote:
Hi Rodrigo,
Looks good. Only thing that needs to be removed is that extra blank line
between the last part of the function and the return statement. Otherwise...
Looking around in our driver the return statement at the end of the
On Mon, Sep 29, 2014 at 03:49:32PM -0700, U. Artie Eoff wrote:
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
sufficient for a majority of use-cases, but it is by no means a complete
solution.
TODO:
Hi all,
So I've decided that it's really time to (slowly) crawl through i915 and
document everything. It's going to take years, but here's a start at least.
I realize that this has good chances to create a constant stream of little
conflicts all over. Well, so be it, I really think we need this.
Another layer of indirection for just an lpt-only w/a is a bit
excessive. Reduce it.
This was added in
commit 7d708ee40a6b9ca1112a322e554c887df105b025
Author: Imre Deak imre.d...@intel.com
Date: Wed Apr 17 14:04:50 2013 +0300
drm/i915: HSW: allow PCH clock gating for suspend
Cc: Imre
I've decided to not move intel_display_port_power_domain because
that's just a hack in our design ...
---
drivers/gpu/drm/i915/intel_display.c| 14 --
drivers/gpu/drm/i915/intel_drv.h| 3 ++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 14 ++
3 files changed, 16
Allows us to mark it static and so forgoe the kerneldoc for it.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_dma.c | 4 +---
drivers/gpu/drm/i915/intel_drv.h| 1 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 34
Geez is the audio hack ugly.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/i915/Makefile |4 +-
drivers/gpu/drm/i915/intel_drv.h| 39 +-
drivers/gpu/drm/i915/intel_pm.c | 1158 --
This simplifies the code in the vlv irq handler. Also this now
means that we correctly filter underruns on gen2-4.
And as the real upshot I need to document one less function for
the fifo underrun code.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_irq.c
Just start with the basics for now.
Since there's a lot of different functionality in i915_irq.c I've
decided to split it into different sections and pull in just the
relevant functions. Splitting into different files looks like a lot
more work since the interrupt handlers do an awful lot of
Prep work for some nice documentation. Requires that we export the
display irq enable/disable functions on ilk/ibx. But we already export
them for vlv/i915. So not more inconsistency.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/i915/Makefile | 1 +
I've decided not to document the functions exported to the audio
driver since really, they shouldn't exist ...
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
Documentation/DocBook/drm.tmpl | 12 +++
drivers/gpu/drm/i915/intel_runtime_pm.c | 163 +++-
It's the new world order!
Not going full monty on these here and rolling this out throughout the
subsequent call chains since this is just for the kerneldoc. Later on
we can go more crazy, especially once we've embedded drm_device
correctly.
v2: Also frob the runtime_pm functions ...
- fini goes with init, so call it intel_power_domains_fini. While
at it shovel some of the fini code that leaked out of it back in.
- give power_enabled functions the verb _is_ to make the meaning clearer.
Also use a __ prefix instead of _unlocked to really discourage users.
- rename
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
Documentation/DocBook/drm.tmpl | 5 ++
drivers/gpu/drm/i915/intel_fifo_underrun.c | 82 +++---
2 files changed, 70 insertions(+), 17 deletions(-)
diff --git a/Documentation/DocBook/drm.tmpl
It's the new rule!
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_irq.c| 35 +++---
drivers/gpu/drm/i915/intel_display.c | 35 +-
drivers/gpu/drm/i915/intel_drv.h | 8 +++
Way too much copypasta all over. And this also clarifies a bit what's
going on since it separates the do we have an underrun irq from the
should we report the underrun check.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c| 69
Double negations just parse harder. Also this allows us to ditch some
init code since clearing to 0 dtrt. Also ditch the assignment in
intel_pm_setup, that's not redundant since we do the assignement now
while setting up interrupts.
While at it do engage in a bit of OCD and wrap up the few lines
This patch introduces the skeleton of vgt, an i915 add-on
for controlling physical GPU resources and sharing among VMs.
Signed-off-by: Jike Song jike.s...@intel.com
---
drivers/gpu/drm/i915/Kconfig| 18 ++
drivers/gpu/drm/i915/Makefile | 4
vgt mediates GPU operations from host i915, in the same way as
mediating GPU operations from normal VMs. This way vgt can
have centralized management about sharing among host and other
VMs. To achieve that, we add a hook in critical wrapper interfaces
(MMIO/GTT).
This patch only adds the MMIO/GTT
This patch convert necessary GTT read/write calls, e.g. iowrite32() and
readl() et al, to an encapsulated series: GTT_READ32, GTT_WRITE32,
GTT_READ64 and GTT_WRITE64.
This patch doesn't change the behaviors of i915 GTT access.
Signed-off-by: Jike Song jike.s...@intel.com
---
All of interfaces between vgt and host i915(MMIO, GTT, irq mediation)
are ready, it's safe to enable it if specified in modparam.
Signed-off-by: Jike Song jike.s...@intel.com
---
drivers/gpu/drm/i915/vgt/vgt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Intel GVT-g (previously known as XenGT), is a complete GPU
virtualization solution with mediated pass-through for 4th
generation Intel Core processors - Haswell platform. This
technology presents a virtual full-fledged GPU to each Virtual
Machine (VM). VMs can directly access performance-critical
Signed-off-by: Jike Song jike.s...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 41 ++---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 051442e..742fe8a 100644
---
vgt owns the hardware interrupt of the GPU, to satisfy the
interrupt requirement from both host side and guest side
(e.g. host may have MI_USER_INTERRUPT disabled, while a VM
may have it enabled). Sometimes vgt may also need to emulate
a virtual interrupt to the host, w/o a hardware interrupt
To provide Intel GPU virtualization, the host i915
driver needs to support vgt - an in-kernel device
model of Intel GPU.
Signed-off-by: Jike Song jike.s...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_params.c | 4
2 files changed, 5 insertions(+)
diff
Signed-off-by: Jike Song jike.s...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 147 +---
drivers/gpu/drm/i915/intel_uncore.c | 3 +
2 files changed, 138 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
On 26 September 2014 14:19, Damien Lespiau damien.lesp...@intel.com wrote:
v2: Add more PCI IDs (Michael H. Nguyen)
v3: Synchronize one more with the kernel PCI IDs (Damien)
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
On 09/29/2014 09:27 PM, Daniel Vetter wrote:
Well, can you still please intrigue me with why you have to change our
interrupt handling from hardirq to work item? It sounds like there's some
crucial issue of the overall design hidden in there.
Hi Daniel,
I just sent out the patch series named
On Tue, Sep 30, 2014 at 06:05:37PM +0800, Jike Song wrote:
vgt owns the hardware interrupt of the GPU, to satisfy the
interrupt requirement from both host side and guest side
(e.g. host may have MI_USER_INTERRUPT disabled, while a VM
may have it enabled). Sometimes vgt may also need to emulate
Hi Daniel,
On Mon, Sep 29, 2014 at 02:30:09PM +0200, Daniel Vetter wrote:
On Mon, Sep 29, 2014 at 02:31:17PM +0800, Zhiyuan Lv wrote:
Hi Daniel,
On Fri, Sep 19, 2014 at 06:09:37PM +0200, Daniel Vetter wrote:
On Sat, Sep 20, 2014 at 02:47:05AM +0800, Jike Song wrote:
From: Yu Zhang
On Tue, Sep 30, 2014 at 06:25:26PM +0800, Zhiyuan Lv wrote:
On Mon, Sep 29, 2014 at 02:30:09PM +0200, Daniel Vetter wrote:
I guess the question is what exactly you want to signal to the hyporvisor
with this. I guess I need to dig a bit into the sourcecode for the
hyperviros part, and you
On Tue, Sep 30, 2014 at 11:19:37AM +0100, Thomas Wood wrote:
On 26 September 2014 14:19, Damien Lespiau damien.lesp...@intel.com wrote:
v2: Add more PCI IDs (Michael H. Nguyen)
v3: Synchronize one more with the kernel PCI IDs (Damien)
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
On Fri, Sep 26, 2014 at 03:02:59PM +0100, Damien Lespiau wrote:
v2: Update to the latest PCI ids
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Ben Widawsky benjamin.widaw...@intel.com
---
Pushed the whole series to i-g-t.
--
Damien
Hi,
On 06/08/14 15:52, Daniel Vetter wrote:
In drm/i915 we want to get at the video= cmdline modes even when we
don't have fbdev support enabled, so that users can always override
the kernel's initial mode selection.
But that gives us a direct depency upon the parsing code in the fbdev
On Tue, Sep 30, 2014 at 1:40 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
On 06/08/14 15:52, Daniel Vetter wrote:
In drm/i915 we want to get at the video= cmdline modes even when we
don't have fbdev support enabled, so that users can always override
the kernel's initial mode selection.
On Thu, Sep 25, 2014 at 10:03:53AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel
On Tue, Sep 30, 2014 at 09:08:35AM -0300, Paulo Zanoni wrote:
+static int intel_gen9_queue_flip(struct drm_device *dev,
+struct drm_crtc *crtc,
+struct drm_framebuffer *fb,
+struct
On Tue, 2014-09-30 at 10:56 +0200, Daniel Vetter wrote:
Geez is the audio hack ugly.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
Looks ok, but needs to be rebased on
commit 08524a9ffa396c56ff3fbec9cfd80edd3fa6a058
Author: Satheeshakrishna M satheeshakrishn...@intel.com
Date: Tue
On Fri, Sep 26, 2014 at 09:28:50AM -0700, Clint Taylor wrote:
On 09/26/2014 08:58 AM, Ville Syrjälä wrote:
On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
port_clock was being incorrectly computed and WRPLL was
On Tue, 2014-09-30 at 10:56 +0200, Daniel Vetter wrote:
Allows us to mark it static and so forgoe the kerneldoc for it.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_dma.c | 4 +---
drivers/gpu/drm/i915/intel_drv.h| 1 -
On Mon, Sep 15, 2014 at 11:17:11AM +0200, Daniel Vetter wrote:
On Fri, Sep 12, 2014 at 09:38:13PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Allow tests to specify the plane size instead of assuming that the
entire FB will be scanned
On Tue, 2014-09-30 at 10:56 +0200, Daniel Vetter wrote:
I've decided not to document the functions exported to the audio
driver since really, they shouldn't exist ...
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
Documentation/DocBook/drm.tmpl | 12 +++
On Tue, 2014-09-30 at 10:56 +0200, Daniel Vetter wrote:
Hi all,
So I've decided that it's really time to (slowly) crawl through i915 and
document everything. It's going to take years, but here's a start at least.
I realize that this has good chances to create a constant stream of little
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, September 29, 2014 3:55 PM
To: Gore, Tim
Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 0/2] Disable Android low memory killer
On Tue, Sep 30, 2014 at 01:17:55PM +, Gore, Tim wrote:
So should I re-submit v1 of my second patch, to disable the
lowmemorykiller by default?
Yeah, but using the exit handler support from igt and adding a big comment
that we just hack around issues with that and that in theory i915
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes bad. Same
force wake is attempted to be taken twice which leads to at least time outs.
NOTE: Depending on
On Tue, Sep 30, 2014 at 03:08:02PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes bad. Same
force wake is attempted to be
On Tue, Sep 30, 2014 at 03:08:02PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes bad. Same
force wake is attempted to be
On Tue, 2014-09-30 at 10:04 +0200, Daniel Vetter wrote:
On Mon, Sep 29, 2014 at 03:49:32PM -0700, U. Artie Eoff wrote:
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
sufficient for a majority of
Daniel Vetter dan...@ffwll.ch writes:
On Mon, Sep 29, 2014 at 2:32 PM, Daniel Vetter dan...@ffwll.ch wrote:
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Queued for -next, thanks for the patch.
Well doesn't compile too well without
Move the duplicated DIV_ROUND_CLOSEST_ULL macro into the intel_drv.h
header file so that it can be shared between intel_display.c
and intel_panel.c.
OTC-Jira: VIZ-4395
v2: Add reference to issue report in commit message.
Signed-off-by: U. Artie Eoff ullysses.a.e...@intel.com
---
Ah snap... I forgot the v4 in the subject line :-/
Nonetheless, this is it.
On Tue, 2014-09-30 at 08:14 -0700, U. Artie Eoff wrote:
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
sufficient for a
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This (partial) work-around should be
sufficient for a majority of use-cases, but it is by no means a complete
solution.
TODO: Determine how best to scale user values to hw values, and
vice-versa,
On 09/30/2014 03:57 PM, Chris Wilson wrote:
On Tue, Sep 30, 2014 at 03:08:02PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use counters
and unless that is matched here force wake use counting goes
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt_aux.c | 15 +++
lib/igt_aux.h | 1 +
tests/kms_cursor_crc.c | 3 ++-
tests/kms_fence_pin_leak.c | 4 ++--
tests/kms_flip.c | 2 +-
5 files changed, 21 insertions(+), 4 deletions(-)
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, September 30, 2014 3:30 AM
On Tue, Sep 30, 2014 at 06:05:37PM +0800, Jike Song wrote:
vgt owns the hardware interrupt of the GPU, to satisfy the
interrupt requirement from both host side and
On Tue, Sep 30, 2014 at 06:02:07PM +0300, Mika Kuoppala wrote:
Daniel Vetter dan...@ffwll.ch writes:
On Mon, Sep 29, 2014 at 2:32 PM, Daniel Vetter dan...@ffwll.ch wrote:
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Queued
On Tue, Sep 30, 2014 at 04:58:54PM +0100, Tvrtko Ursulin wrote:
On 09/30/2014 03:57 PM, Chris Wilson wrote:
On Tue, Sep 30, 2014 at 03:08:02PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Write and reads following the block changed use engine specific use
On Tue, Sep 30, 2014 at 02:58:54PM +, Eoff, Ullysses A wrote:
On Tue, 2014-09-30 at 10:04 +0200, Daniel Vetter wrote:
On Mon, Sep 29, 2014 at 03:49:32PM -0700, U. Artie Eoff wrote:
Improper truncated integer division in the scale() function causes
actual_brightness != brightness. This
From: Song, Jike
Sent: Tuesday, September 30, 2014 3:06 AM
vgt mediates GPU operations from host i915, in the same way as
mediating GPU operations from normal VMs. This way vgt can
have centralized management about sharing among host and other
VMs. To achieve that, we add a hook in
With the structured logging it makes more sense to tune this down a
bit. Also, this way it is consistent with Thomas Wood's new activity
indicator helper.
Spotted while discussing Thomas' patch with him.
Cc: Thomas Wood thomas.w...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, September 30, 2014 9:32 AM
To: Eoff, Ullysses A
Cc: dan...@ffwll.ch; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2 v3] drm/i915: intel_backlight
On Tue, Sep 30, 2014 at 04:52:43PM +, Eoff, Ullysses A wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Tuesday, September 30, 2014 9:32 AM
To: Eoff, Ullysses A
Cc: dan...@ffwll.ch;
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel clock double, we also need to write
to the TRANS_MULT_n (0x6002c) register to double
On Tue, Sep 30, 2014 at 10:30:22AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
Haswell and later silicon has added a new pixel replication register
to the pipe timings for each transcoder. Now in addition to the
DPLL_A_MD register for the pixel
On Tue, Sep 30, 2014 at 06:45:52PM +0200, Daniel Vetter wrote:
With the structured logging it makes more sense to tune this down a
bit. Also, this way it is consistent with Thomas Wood's new activity
indicator helper.
Tune it down? It was on stderr to segregate it from stdout. So either
the
Oh well.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_frontbuffer.c | 13 ++---
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h
So I think I've spotted a small gap in the frontbuffer tracking
while discussing the logic with Paulo on irc:
1. Userspace schedules gpu rendering to the current frontbuffer.
This gets tracked in dev_priv-fb_tracking.busy_bits.
2. We pageflip a fully rendered buffer before the frontbuffer
2014-09-30 17:10 GMT-03:00 Daniel Vetter daniel.vet...@ffwll.ch:
So I think I've spotted a small gap in the frontbuffer tracking
while discussing the logic with Paulo on irc:
1. Userspace schedules gpu rendering to the current frontbuffer.
This gets tracked in dev_priv-fb_tracking.busy_bits.
2014-09-30 17:10 GMT-03:00 Daniel Vetter daniel.vet...@ffwll.ch:
Oh well.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_frontbuffer.c | 13 ++---
2 files changed, 7 insertions(+), 8 deletions(-)
On Mon, Sep 29, 2014 at 06:29:52PM -0400, Rodrigo Vivi wrote:
Sink crc was implemented based on dp 1.1 spec that had all TEST_SINK bits
reserved reading all 0s. But when reviewing my latest changes on sink crc
Todd warned me that on new specs we have other valid bits on this reg that we
might
Please don't forget the drm/i915: Fix Sink CRC
That is the important one that fix crc calculation and will allow me
to remove the extra wait for vblanks on tests besides making tests
more stable.
On Tue, Sep 30, 2014 at 1:36 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Sep 29, 2014 at
On Tue, Sep 30, 2014 at 08:58:14PM +0100, Chris Wilson wrote:
On Tue, Sep 30, 2014 at 06:45:52PM +0200, Daniel Vetter wrote:
With the structured logging it makes more sense to tune this down a
bit. Also, this way it is consistent with Thomas Wood's new activity
indicator helper.
Tune it
Avoid to expose RC6 and RC6pp to the platforms that doesn't support it.
Although this doesn't really change powertop behaviour as described on the
request.
References: https://bugs.freedesktop.org/show_bug.cgi?id=84524
Cc: Josh Triplett josh.tripl...@intel.com
Signed-off-by: Rodrigo Vivi
Program the default initial value of the L3SqcReg1 on BDW for performance
v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
Cc: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
so please, just ignore this patch anyway.
On Fri, Sep 26, 2014 at 7:56 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Fri, Sep 26, 2014 at 05:16:57PM +0300, Mika Kuoppala wrote:
Jani Nikula jani.nik...@linux.intel.com writes:
On Fri, 26 Sep 2014, Mika Kuoppala
This seems to have been accidentally lost in
commit be62acb4cce1389a28296852737e3917d9cc5b25
Author: Mika Kuoppala mika.kuopp...@linux.intel.com
Date: Fri Aug 30 16:19:28 2013 +0300
drm/i915: ban badly behaving contexts
Without this real gpu hangs only log output at info level, which gets
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