On Mon, Oct 06, 2014 at 04:17:55PM -0700, Clint Taylor wrote:
On 09/30/2014 05:46 AM, Ville Syrjälä wrote:
On Fri, Sep 26, 2014 at 09:28:50AM -0700, Clint Taylor wrote:
On 09/26/2014 08:58 AM, Ville Syrjälä wrote:
On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.tay...@intel.com
Hi,
Did anybody get a chance to look at this patch?
Thanks,
Sonika
-Original Message-
From: Jindal, Sonika
Sent: Monday, September 15, 2014 1:14 PM
To: intel-gfx@lists.freedesktop.org
Cc: Ville Syrjälä; Kamble, Sagar A; Jindal, Sonika
Subject: [PATCH] drm/i915: Add rotation support for
On Mon, Oct 06, 2014 at 03:01:46PM -0700, Clint Taylor wrote:
On 09/26/2014 09:28 AM, Ville Syrjälä wrote:
On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor clinton.a.tay...@intel.com
HDMI audio clock config was incorrectly choosing the default
On Mon, Oct 06, 2014 at 05:00:24PM +0100, Damien Lespiau wrote:
Because quick-dump was only selecting a few files in lib/ and we move
stuff around and/or add new dependencies we were failing to provide the
necessary symbols to the shim library providing python bindings. And so
we had a
On Mon, Oct 06, 2014 at 06:56:43PM +0100, Damien Lespiau wrote:
SKL will have a whole separate display regs file, so merge
base_display.txt into each platform file.
Please drop it from vlv/chv. It's not appropriate for those platforms.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
On 10/07/2014 11:22 AM, Ville Syrjälä wrote:
On Mon, Oct 06, 2014 at 05:11:57PM +0100, Tvrtko Ursulin wrote:
Hi all,
We need to refactor the current code a bit to allow parameters like
plane rotation and framebuffer tiling mode be taken into account when
calculating display watermarks.
I
From: Ville Syrjälä ville.syrj...@linux.intel.com
When the video timings are suitably aligned so that all different
periods start at phase 0 (ie. none of the periods start mid-pixel)
we can inform the sink about this. Supposedly the sink can then
optimize certain things. Obviously this is only
From: Ville Syrjälä ville.syrj...@linux.intel.com
GCP infoframes are required to inform the HDMI sink about the color
depth.
Send the GCP infoframe whenever the sink supports any deep color modes
since such sinks must anyway be capable of receiving them. For sinks
that don't support deep color
From: Ville Syrjälä ville.syrj...@linux.intel.com
CPT/PPT require a specific procedure for enabling 12bpc HDMI. Implement
it, and to keep things neat pull the code into a function.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
From: Ville Syrjälä ville.syrj...@linux.intel.com
We were missing all kinds of important stuff for HDMI 12bpc support.
No idea how it could have worked for anyone when we didn't even send
the GCP infoframes. This series fixes things enough to make it work
on my IVB machine.
I was too lazy to
On Thu, Oct 02, 2014 at 08:56:54PM +1000, Dave Airlie wrote:
On 2 October 2014 18:40, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Thu, Oct 02, 2014 at 10:00:50AM +0200, Daniel Vetter wrote:
On Thu, Oct 02, 2014 at 01:30:48PM +1000, Dave Airlie wrote:
Hey guys,
so I have a
The implmentation is simple in the extreme: we only want to wait for
events if the device was opened in blocking mode, otherwise we grab what
is available and report an error if there was none.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: dri-de...@lists.freedesktop.org
---
As per latest pm guide, we need to do this also on
past hsw.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Cc: Chris Wilson ch...@chris-wilson.co.uk
Cc: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
After reset or suspend, the hardware render context state
has been cleared to default values. If this is a first
switch after such event, we need to restore the state
to get back to pre reset state.
As the render context state contains the wa
registers, on bdw, this also effectively restores the
If we build the workaround list in ring initialization
and decouple it from the actual writing of values, we
gain the ability to decide where and how we want to apply
the values.
The advantage of this will become more clear when
we need to initialize workarounds on older gens where
it is not
We have lost render context state on suspend. This is
identical how we lose the state on reset. So mark the
context as reset so that we restore from pre suspend
state.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1 insertion(+)
As the workaround list has the value as initialization time
constant, we can do the simple checking on the go without
negleting igt.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
From: Ville Syrjälä ville.syrj...@linux.intel.com
We need the HPLL frequency when calculating cdclk. Currently we read
that out from the hardware every single time, which isn't going to fly
very well if the device is runtime suspended. So cache the HPLL
frequency in dev_priv and use the cached
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
On Wed, Sep 24, 2014 at 02:20:25PM -0300, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Move check inside intel_crtc_cursor_set_obj() to
intel_check_cursor_plane(), we only use it there so move them out to
make the merge of intel_crtc_cursor_set_obj() into
Actually set values into PPS related registers. This implementation is
equivalent to intel_dp_panel_power_sequencer_registers where the values
saved intially are written into registers.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c| 4 +-
Defining functions equivalent to intel_dp_panel_power_sequencer.
In the setup part, the differnce between vlv and other platforms is only
w.r.t registers. Other parts like reading VBT are common.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |
Since panel power sequencing is a feature common to all internal displays,
moving relevant code to intel_panel.c. This patch series contains changes
to setup PPS data and program register values as required.
The implementation follows the model used for backlight funcs
(as suggested by Daniel)
Creating generic functions and data related to panel power sequencing in
intel_panel. The functions have been added equivalent to
intel_dp_panel_power_sequencer() and intel_dp_panel_power_sequencer_registers()
These changes have been made to move PPS related data from intel_dp or
other panel
Replacing intel_dp PPS delays with intel_panel PPS delays.
This is part of removing all refs to PPS in intel_dp and moving it to
PPS in intel_panel.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 22 +++---
1 file changed, 15
intel_dp_panel_power_sequencer and intel_dp_panel_power_sequence_registers
have been replaced by equivalent code in intel_panel.c
Making changes to remove these functions and refs to it.
vlv_power_sequencer_pipe() should return only pipe. panel power
sequencer functions need not be called from
Volkin, Bradley D bradley.d.vol...@intel.com writes:
Hi Bradley,
[snip]
On Thu, Sep 18, 2014 at 07:58:30AM -0700, Mika Kuoppala wrote:
@@ -577,7 +596,7 @@ static int do_switch(struct intel_engine_cs *ring,
vma-bind_vma(vma, to-legacy_hw_ctx.rcs_state-cache_level,
Moving timestamp values to intel_panel as part of moving all refs of PPS to
intel_panel.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c| 31 ---
drivers/gpu/drm/i915/intel_drv.h | 12
On Wed, Sep 24, 2014 at 02:20:26PM -0300, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Merge it into the plane update_plane() callback and make other
users use the update_plane() functions instead.
The fb != crtc-cursor-fb was already inside
On Tue, Oct 07, 2014 at 05:47:52PM +0300, Ville Syrjälä wrote:
On Wed, Sep 24, 2014 at 02:20:25PM -0300, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Move check inside intel_crtc_cursor_set_obj() to
intel_check_cursor_plane(), we only use it there so move
On Tue, Oct 07, 2014 at 05:21:25PM +0300, Mika Kuoppala wrote:
We have lost render context state on suspend. This is
identical how we lose the state on reset. So mark the
context as reset so that we restore from pre suspend
state.
You are on the right track. With a little more effort you can
commit b680c37a4d145cf4d8f2b24e46b1163e5ceb1d35
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Fri Sep 19 18:27:27 2014 +0200
drm/i915: DocBook integration for frontbuffer tracking
Moved the code to intel_frontbuffer.c but this bit
got stranded.
Signed-off-by: Mika Kuoppala
Chris Wilson ch...@chris-wilson.co.uk writes:
When run as a timer, i915_hangcheck_elapsed() must adhere to all the
rules of running in a softirq context. This is advantageous to us as we
want to minimise the risk that a driver bug will prevent us from
detecting a hung GPU. However, that is
On Wed, Sep 24, 2014 at 02:20:27PM -0300, Gustavo Padovan wrote:
From: Daniel Stone dani...@collabora.com
Start the work of splitting the intel_crtc_page_flip() for later use
by the atomic modesetting API.
At this time this doesn't really do anything so I don't see much point
in applying it,
On Wed, Sep 24, 2014 at 02:20:30PM -0300, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
take out pin_fb code so the commit phase can't fail anymore.
Yeah making commit() void is a good step. For patches 8 and 9:
Reviewed-by: Ville Syrjälä
On Wed, Sep 24, 2014 at 02:20:31PM -0300, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Use the macros makes the code cleaner and it also checks for a NULL fb.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
Reviewed-by: Ville Syrjälä
On Wed, Sep 24, 2014 at 02:20:32PM -0300, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
After some refactor intel_primary_plane_setplane() does the same
as intel_pipe_set_base() so we can get rid of it and replace the calls
with intel_primary_plane_setplane().
From: John Harrison john.c.harri...@intel.com
For: VIZ-4377
Signed-off-by: john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 34 ---
drivers/gpu/drm/i915/i915_gem.c | 21 +++
drivers/gpu/drm/i915/intel_lrc.c|
From: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++
2 files
From: Ben Widawsky benjamin.widaw...@intel.com
Now that we don't need to trace num_pd_pages, we may as well kill all
need for the PPGTT structure in the alloc_pagedirs. This is very useful
for when we move to 48b addressing, and the PDP isn't the root of the
page table structure.
The param is
From: Ben Widawsky benjamin.widaw...@intel.com
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
TODO: this probably needs to be earlier in the series
Signed-off-by: Ben Widawsky b...@bwidawsk.net
From: Ben Widawsky benjamin.widaw...@intel.com
These page table helpers make the code much cleaner. There is some
room to use the arch/x86 header files. The reason I've opted not to is
in several cases, the definitions are dictated by the CONFIG_ options
which do not always indicate the
From: Ben Widawsky benjamin.widaw...@intel.com
It's useful to have it not as a macro for some upcoming work. Generally
since we try to avoid macros anyway, I think it doesn't hurt to put this
as its own patch.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry
From: Ben Widawsky benjamin.widaw...@intel.com
This patch finishes off actually separating the aliasing and global
finds. Prior to this, all global binds would be aliased. Now if aliasing
binds are required, they must be explicitly asked for. So far, we have
no users of this outside of execbuf -
From: Ben Widawsky benjamin.widaw...@intel.com
There is never a case where we don't want to do it. Since we've broken
up the allocations into nice clean helper functions, it's both easy and
obvious to do the dma mapping at the same time.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
From: Ben Widawsky benjamin.widaw...@intel.com
One important part of this patch is we now write a scratch page
directory into any unused PDP descriptors. This matters for 2 reasons,
first, it's not clear we're allowed to just use 0, or an invalid
pointer, and second, we must wipe out any previous
From: Ben Widawsky benjamin.widaw...@intel.com
The actual correct way to think about this with the new style of page
table data structures is as the actual entry that is being indexed into
the array. pd, and pt aren't representative of what the operation is
doing.
The clarity here will improve
From: Ben Widawsky benjamin.widaw...@intel.com
Map and unmap are common operations across all generations for
pagetables. With a simple helper, we can get a nice net code reduction
as well as simplified complexity.
There is some room for optimization here, for instance with the multiple
page
From: Ben Widawsky benjamin.widaw...@intel.com
As we move toward dynamic page table allocation, it becomes much easier
to manage our data structures if break do things less coarsely by
breaking up all of our actions into individual tasks. This makes the
code easier to write, read, and verify.
From: Ben Widawsky benjamin.widaw...@intel.com
The driver currently lets callers pin global, and then tries to do
things correctly inside the function. Doing so has two downsides:
1. It's not possible to exclusively pin to a global, or an aliasing
address space.
2. It's difficult to read, and
From: Ben Widawsky benjamin.widaw...@intel.com
Split out single mappings which will help with upcoming work. Also while
here, rename the function because it is a better description - but this
function is going away soon.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry
From: Ben Widawsky benjamin.widaw...@intel.com
With a little bit of macro magic, and the fact that every page
table/dir/etc. we wish to map will have a page, and daddr member, we can
greatly simplify and reduce code.
The patch introduces an i915_dma_map/unmap which has the same semantics
as
Logic ring contexts need to know the PDPs when they are populated. With
dynamic page table allocations, these PDPs may not exist yet.
Check if PDPs have been allocated and use the scratch page if they do
not exist yet.
Before submission, update the PDPs in the logic ring context as PDPs
have
From: Ben Widawsky benjamin.widaw...@intel.com
Similar to the patch a few back in the series, we can always map and
unmap page directories when we do their allocation and teardown. Page
directory pages only exist on gen8+, so this should only effect behavior
on those platforms.
Signed-off-by:
From: Ben Widawsky benjamin.widaw...@intel.com
trivial.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Ben Widawsky benjamin.widaw...@intel.com
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs within a
page table are currently being used
From: Ben Widawsky benjamin.widaw...@intel.com
Move the remaining members over to the new page table structures.
This can be squashed with the previous commit if desire. The reasoning
is the same as that patch. I simply felt it is easier to review if split.
v2: In lrc:
From: Ben Widawsky benjamin.widaw...@intel.com
Having a more general way of doing mappings will allow the ability to
easy map and unmap a specific page table. Specifically in this case, we
pass down the page directory + entry, and the page table to map. This
works similarly to the x86 code.
The
From: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_evict.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
From: Ben Widawsky benjamin.widaw...@intel.com
When we do dynamic page table allocations for gen8, we'll need to have
more control over how and when we map page tables, similar to gen6.
This patch adds the functionality and calls it at init, which should
have no functional change.
The PDPEs are
From: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_trace.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
From: Ben Widawsky benjamin.widaw...@intel.com
This finishes off the dynamic page tables allocations, in the legacy 3
level style that already exists. Most everything has already been setup
to this point, the patch finishes off the enabling by setting the
appropriate function pointers.
Zombie
From: Ben Widawsky benjamin.widaw...@intel.com
This patch continues on the idea from the previous patch. From here on,
in the steady state, PDEs are all pointing to the scratch page table (as
recommended in the spec). When an object is allocated in the VA range,
the code will determine if we need
From: Ben Widawsky benjamin.widaw...@intel.com
Thus far we've opted to make complex code requiring difficult review. In
the future, the code is only going to become more complex, and as such
we'll take the hit now and start to encapsulate things.
To help transition the code nicely there is some
From: Ben Widawsky benjamin.widaw...@intel.com
We have some fanciness coming up. This patch just breaks out the logic.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c | 10 ++
1 file
From: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++---
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git
From: Ben Widawsky benjamin.widaw...@intel.com
This will be useful for some upcoming patches which do more platform
specific work. Having it in one central place just makes things a bit
cleaner and easier.
NOTE: I didn't actually end up using this patch for the intended
purpose, but I thought it
From: Ben Widawsky benjamin.widaw...@intel.com
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
v2: Match
From: Ben Widawsky benjamin.widaw...@intel.com
The problem is we're going to switch to a new context, which could be
the default context. The plan was to use restore inhibit, which would be
fine, except if we are using dynamic page tables (which we will). If we
use dynamic page tables and we
From: Ben Widawsky benjamin.widaw...@intel.com
Upcoming patches will use the terms map and unmap in references to the
page table entries. Having this distinction will really help with code
clarity at that point.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry
This is based on the first 55 patches of Ben's 48b addressing work, taking
into consideration the latest changes in (mainly aliasing) ppgtt rules.
Because of these changes in the tree, the first 17 patches of the original
series are no longer needed, and some patches required more rework than
From: Ben Widawsky benjamin.widaw...@intel.com
There often is not enough memory to dump the full contents of the PPGTT.
As a temporary bandage, to continue getting valuable basic PPGTT info,
wrap the dangerous, memory hungry part inside of a new verbose version
of the debugfs file.
Also while
From: Ben Widawsky benjamin.widaw...@intel.com
This patch was formerly known as, Force pd restore when PDEs change,
gen6-7. I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new object is mapped
into the current address space. The GPU
From: Ben Widawsky benjamin.widaw...@intel.com
The current code will both potentially print a WARN, and setup part of
the PPGTT structure. Neither of these harm the current code, it is
simply for clarity, and to perhaps prevent later bugs, or weird
debug messages.
Signed-off-by: Ben Widawsky
From: Ben Widawsky benjamin.widaw...@intel.com
Like with gen6/7, we can enable bitmap tracking with all the
preallocations to make sure things actually don't blow up.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
Hi Rodrigo/Damien,
Could you please help me in getting this patch reviewed.
Thanks and Regards,
Gagan
On 9/13/2014 1:26 AM, Gagandeep S Arora wrote:
From: gsaroragagandeep.s.ar...@intel.com
Extended intel_sprite_on functionality to display all the
available sprite planes on a particular
From: Paulo Zanoni paulo.r.zan...@intel.com
We were missing the pipe B/C vblank bits! Take a look at
gen8_de_irq_postinstall for a comparison.
This should fix a bunch of IGT tests.
There are a few more things we could improve on this code, but this
should be the minimal fix to unblock us.
On Tue, 7 Oct 2014 14:13:51 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
The implmentation is simple in the extreme: we only want to wait for
events if the device was opened in blocking mode, otherwise we grab
what is available and report an error if there was none.
Signed-off-by:
On Tue, Oct 07, 2014 at 04:11:10PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We were missing the pipe B/C vblank bits! Take a look at
gen8_de_irq_postinstall for a comparison.
This should fix a bunch of IGT tests.
There are a few more things we could improve
On Tue, Oct 07, 2014 at 04:11:11PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Only run it after we actually enable the power well. When we're
booting the machine there are cases where we run
hsw_power_well_post_enable without really needing, and even though
this
Gets the detect code (which may take awhile) out of the resume path,
speeding things up a bit.
v2: use a delayed work queue instead (Daniel)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_dma.c | 10 ++
drivers/gpu/drm/i915/i915_drv.c | 8 ++--
Avoid to expose RC6 and RC6pp to the platforms that doesn't support it.
So powertop can be changed to show RC6p and RC6pp only on the platforms
they are available.
v2: Simplify by merging RC6p and RC6pp groups and respect the spec that
mentions deep and deepest RC6 until BDW although they keep
2014-10-07 10:36 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
Avoid to expose RC6 and RC6pp to the platforms that doesn't support it.
So powertop can be changed to show RC6p and RC6pp only on the platforms
they are available.
v2: Simplify by merging RC6p and RC6pp groups and respect the
From: Paulo Zanoni paulo.r.zan...@intel.com
We were missing the pipe B/C vblank bits! Take a look at
gen8_de_irq_postinstall for a comparison.
This should fix a bunch of IGT tests.
There are a few more things we could improve on this code, but this
should be the minimal fix to unblock us.
v2:
Avoid to expose RC6 and RC6pp to the platforms that doesn't support it.
So powertop can be changed to show RC6p and RC6pp only on the platforms
they are available.
v2: Simplify by merging RC6p and RC6pp groups and respect the spec that
mentions deep and deepest RC6 on SNB and IVB although they
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