The function was removed in:
commit 0e32b39ceed665bfa4a77a4bc307b6652b991632
Author: Dave Airlie
Date: Fri May 2 14:02:48 2014 +1000
drm/i915: add DP 1.2 MST support (v0.7)
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_drv.h | 1 -
1 file changed, 1 deletion(-)
d
The function was removed in:
commit 037bde19a43e299d30f0490bba9be32ab355975c
Author: Chris Wilson
Date: Thu Mar 27 08:24:19 2014 +
Revert "drm/i915: Disable/Enable PM Intrrupts based on the current freq."
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.h | 2
Thanks for the review, Ander.
Daniel, in case you're tempted to merge this, don't just yet. Shaung's
test bot found an issue with the refactoring patch I'm still tracking
down. I'll post a v3 with the fix in reply to this...
Thanks,
Jesse
On Thu, 30 Oct 2014 11:53:59 -0700
Jesse Barnes wrote:
On Fri, Oct 31, 2014 at 5:27 AM, Rodrigo Vivi
wrote:
>
> Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
> So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
>
> MOCS can still be used though. But if userspace is trusting PTE for
> cache selection t
Please ignore my command and this revert. It seems original version
that is currently applied is a needed Workaround.
On Fri, Oct 31, 2014 at 12:45 PM, Rodrigo Vivi wrote:
> I'm wondering how many hangs we could have fixed with this patch.
>
> Althougth it can end up in worst RC6 residency this i
I'm wondering how many hangs we could have fixed with this patch.
Althougth it can end up in worst RC6 residency this is what spec shows.
From our experience with SNB it is always better to stay with spec, mainly
on threshold values.
So,
Reviewed-by: Rodrigo Vivi
On Thu, Aug 21, 2014 at 8:11
Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
MOCS can still be used though. But if userspace is trusting PTE for
cache selection the safest thing to do is to let caches disabled.
BSpec: "For GGT
On Fri, Oct 31, 2014 at 02:39:11PM +, Damien Lespiau wrote:
> Cc: Chandra Konduru
> Cc: Daniel Vetter
> Signed-off-by: Damien Lespiau
On the entire series:
Reviewed-by: Daniel Vetter
Merged into topic/core-stuff for shepherding until it lands in drm-next.
-Daniel
> ---
> drivers/gpu/dr
On Fri, Oct 31, 2014 at 07:25:08AM -0400, Sean Paul wrote:
> On Wed, Oct 29, 2014 at 5:12 AM, Daniel Vetter wrote:
> > While writing atomic docs I've noticed that I don't get any errors
> > for my screw-ups in drm_crtc.h. Fix this immediately.
> >
> > This just does the bare minimum to get starts,
On Thu, Oct 30, 2014 at 04:03:23PM -0700, armin.c.re...@intel.com wrote:
> From: Armin Reese
>
> The new 'i915_context_dump' file generates a hex dump of the
> entire logical context DRM object. It is useful for
> validating the contents of the default context set up by
> the golden state batch
On Fri, Oct 31, 2014 at 02:52:40PM +, Damien Lespiau wrote:
> On Fri, Oct 31, 2014 at 12:00:26PM +, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > If a ring failed to initialise for any reason then the error path would try
> > to
> > clean up all rings including those t
On Wed, Oct 29, 2014 at 02:42:29PM +0100, Thierry Reding wrote:
> On Wed, Oct 22, 2014 at 11:45:23AM +0530, sonika.jin...@intel.com wrote:
> > From: Sonika Jindal
> >
> > v2: Reading DP_EDP_REV, only when DISPLAY_CONTROL_CAPABLE field is set
> > (Satheesh)
> >
> > v3: Moving the utility functio
to move the interface to the ppgtt era.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gpu_error.c | 49 +++
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
On Fri, Oct 31, 2014 at 12:00:26PM +, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> If a ring failed to initialise for any reason then the error path would try to
> clean up all rings including those that had not yet been allocated. The ring
> clean up code did a check that the r
When drm properties are created, they are added to mode_config.property_list,
which is then used in drm_mode_config_cleanup() to destroy every single
property created by the driver.
Cc: Chandra Konduru
Cc: Daniel Vetter
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_sdvo.c | 47 -
When drm properties are created, they are added to mode_config.property_list
which is then used in drm_mode_config_cleanup() to destroy every single
property created by the driver.
Cc: Patrik Jakobsson
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/gma500/psb_intel_sdvo.c | 49 --
Cc: Chandra Konduru
Cc: Daniel Vetter
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/drm_crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 4081d7a..0f3c24c 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm
We use the obj->map_and_fenceable hint for when we already have a
valid mapping of this object in the aperture. This hint can only apply
to the GGTT and not to the aliasing-ppGTT. One user of the hint is
execbuffer relocation, which began to fail when it tried to follow the
hint and perform the rel
Always require PIN_GLOBAL when we want a mappable offset (PIN_MAPPABLE).
This causes the pin to fixup the global binding in cases were the vma
was already bound (and due to the proceeding bug, we considered it to be
already mappable).
References: https://bugs.freedesktop.org/show_bug.cgi?id=85671
From: John Harrison
If a ring failed to initialise for any reason then the error path would try to
clean up all rings including those that had not yet been allocated. The ring
clean up code did a check that the ring was valid before starting its work.
Unfortunately, that was after it had already
This is an old version. I have a new and improved patch that also fixes
the legacy ring buffer case (which was equally broken). Will post shortly...
On 30/10/2014 15:30, Dave Gordon wrote:
From: John Harrison
Check whether each engine exists before trying to clean up the
corresponding logical
On 10/29/2014 05:22 PM, Damien Lespiau wrote:
Universal planes have changed a bit the register organization.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 108 ---
1 file changed, 101 insertions(+), 7 deletions(-)
diff --git a/driv
When we capture the GPU error state, we allocate large amounts of memory
to preserve copies of the active objects on the GPU. We can compress the
copy in memory, and use an asci85 encoding when printing them out (to
avoid presenting binary data to unsuspecting catting of debugfs/procfs).
v2: Trail
Recent kernels compress the active objects using zlib + ascii85
encoding. This adapts the tool to decompress those inplace.
Signed-off-by: Chris Wilson
---
tools/Makefile.sources | 1 +
tools/intel_error_decode.c | 93 ++
2 files changed, 94 inser
On Wed, Oct 29, 2014 at 5:12 AM, Daniel Vetter wrote:
> I've tried to cc all the people who have recently added new stuff
> but forgotten to update documentation.
>
> I've also decided not to bother documenting the massive property list
> in struct drm_mode_config. If that beast keeps on growing w
On Wed, Oct 29, 2014 at 5:12 AM, Daniel Vetter wrote:
> While writing atomic docs I've noticed that I don't get any errors
> for my screw-ups in drm_crtc.h. Fix this immediately.
>
> This just does the bare minimum to get starts, lots of stuff isn't
> properly documented yet unfortunately.
>
> Sig
On Fri, Oct 31, 2014 at 12:14:25PM +0200, Ville Syrjälä wrote:
> On Fri, Oct 31, 2014 at 07:44:34AM +, Chris Wilson wrote:
> > On Thu, Oct 30, 2014 at 09:18:18AM -0700, Rodrigo Vivi wrote:
> > > Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
> > > So the only way to a
On Fri, Oct 31, 2014 at 07:44:34AM +, Chris Wilson wrote:
> On Thu, Oct 30, 2014 at 09:18:18AM -0700, Rodrigo Vivi wrote:
> > Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
> > So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
> >
> > MOCS can
On Thu, Oct 30, 2014 at 06:41:11PM -0200, Paulo Zanoni wrote:
> 2014-10-30 15:43 GMT-02:00 :
> > From: Ville Syrjälä
> >
> > Throw away the hand rolled display irq setup code on chv, and instead
> > just call vlv_display_irq_postinstall() and vlv_display_irq_uninstall().
> >
> > Signed-off-by: Vi
From: Ville Syrjälä
There are two leftover GTIIR writes in valleyview_irq_preinstall().
Looks like the were originally left behind by:
commit d18ea1b58a5003eb6fca03aff03c4c01321e6cb1
Author: Daniel Vetter
Date: Fri Jul 12 22:43:25 2013 +0200
drm/i915: unify PM interrupt preinstall seq
On Fri, Oct 31, 2014 at 11:35:52AM +0200, Ville Syrjälä wrote:
> On Thu, Oct 30, 2014 at 05:51:49PM -0200, Paulo Zanoni wrote:
> > 2014-10-30 15:42 GMT-02:00 :
> > > From: Ville Syrjälä
> > >
> > > Looks like we forgot to call gen5_gt_irq_reset() for vlv in the
> > > uninstall phase. Do so.
> >
On Thu, Oct 30, 2014 at 06:37:46PM -0200, Paulo Zanoni wrote:
> 2014-10-30 18:22 GMT-02:00 Paulo Zanoni :
> > 2014-10-30 15:42 GMT-02:00 :
> >> From: Ville Syrjälä
> >>
> >> Pull the vlv display irq uninstall code into a separate function, for
> >> eventual sharing with chv.
> >>
> >> Signed-off-
[off-topic]
On Fri, 31 Oct 2014, Ville Syrjälä wrote:
> On Thu, Oct 30, 2014 at 12:57:04PM -0700, Kenneth Graunke wrote:
>> I don't think HALF_SLICE_CHICKEN3 is part of the logical context, FWIW.
>
> Oh but it is. Lots of chickens like to nest in the context.
In the context of lunch, HALF_SLICE
On Thu, Oct 30, 2014 at 06:12:51PM -0200, Paulo Zanoni wrote:
> 2014-10-30 15:42 GMT-02:00 :
> > From: Ville Syrjälä
> >
> > Genralize valleyview_display_irqs_install() and
> > valleyview_display_irqs_uninstall() enough so that they work on chv.
> > The only difference to vlv here being the third
For the series,
Reviewed-by: Ander Conselvan de Oliveira
On 10/30/2014 08:54 PM, Jesse Barnes wrote:
> This should allow us to avoid mode sets for some panel fitter config
> changes.
>
> v2:
>- fixup pfit comment (Ander)
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel
On Thu, Oct 30, 2014 at 05:51:49PM -0200, Paulo Zanoni wrote:
> 2014-10-30 15:42 GMT-02:00 :
> > From: Ville Syrjälä
> >
> > Looks like we forgot to call gen5_gt_irq_reset() for vlv in the
> > uninstall phase. Do so.
>
> I also see that valleyview_irq_preinstall() contains 2 writes to GTIIR
> ju
On Thu, Oct 30, 2014 at 12:57:04PM -0700, Kenneth Graunke wrote:
> On Thursday, October 30, 2014 09:26:01 PM Ville Syrjälä wrote:
> > On Thu, Oct 30, 2014 at 10:32:38AM -0700, Kenneth Graunke wrote:
> > > On Thursday, October 30, 2014 01:01:30 PM Ville Syrjälä wrote:
> > > > On Thu, Oct 30, 2014 at
On Thu, 30 Oct 2014, Rodrigo Vivi wrote:
> On Tue, Oct 28, 2014 at 5:04 AM, Jani Nikula wrote:
>> Similar to the hsw/bdw enable sequence rewrite.
>>
>> v3: replace vblank wait with a comment
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_audio.c | 58
>> +
When we capture the GPU error state, we allocate large amounts of memory
to preserve copies of the active objects on the GPU. We can compress the
copy in memory, and use an asci85 encoding when printing them out (to
avoid presenting binary data to unsuspecting catting of debugfs/procfs).
v2: Trail
On Thu, 30 Oct 2014, Rodrigo Vivi wrote:
> On Tue, Oct 28, 2014 at 5:03 AM, Jani Nikula wrote:
>> There's some serious confusion regarding ELD valid bit that gets set and
>> cleared back and forth etc. Rewrite it all based on the documented audio
>> codec enable/disable sequences.
>>
>> v3: repla
On Thu, Oct 30, 2014 at 09:18:18AM -0700, Rodrigo Vivi wrote:
> Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000;
> So the only way to avoid screen corruptions is setting PAT 0 to Uncached.
>
> MOCS can still be used though. But if userspace is trusting PTE for
> cache sele
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