On Mon, 10 Nov 2014, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Mon, 3 Nov 2014 11:39:24 +0100
Daniel Vetter daniel.vet...@ffwll.ch wrote:
On pre-ddi platforms we don't shut down the link when changing link
training parameters. Except when clock recovery fails too hard and we
restart
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate-patch_applied_pass_rate
BYT: pass/total=277/348-277/348
PNV:
Motivated by the per-plane locking I've gone through all the get*
ioctls and reduced the locking to the bare minimum required.
v2: Rebase and make it compile ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_crtc.c | 46
Turned out to be much simpler on top of my latest atomic stuff than
what I've feared. Some details:
- Drop the modeset_lock_all snakeoil in drm_plane_init. Same
justification as for the equivalent change in drm_crtc_init done in
commit d0fa1af40e784aaf7ebb7ba8a17b229bb3fa4c21
Hi Bob,
Thanks for the patch. Just a small comment below.
On 11/11/2014 01:09 AM, Bob Paauwe wrote:
Use the new pipe config values to calculate the updated pll dividers.
This regression was introduced in
commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
Author: Ander Conselvan de Oliveira
On Mon, Nov 10, 2014 at 01:44:31PM +, daniele.ceraolospu...@intel.com wrote:
From: Daniele Ceraolo Spurio daniele.ceraolospu...@intel.com
- ppgtt init/release: these tracepoints are useful for observing the
creation and destruction of Full PPGTTs.
- ctx create/free: we can use the
On Mon, Nov 10, 2014 at 07:15:04PM +0200, Ville Syrjälä wrote:
As a side note if someone is looking for stuff to do, then the pin/unpin
logic might be good thing to look at. We're currently a bit inconsistent
whether we have the buffer pinned when the plane is disabled, or just
otherwise
On Mon, Nov 10, 2014 at 07:15:04PM +0200, Ville Syrjälä wrote:
On Mon, Nov 10, 2014 at 02:47:30PM -0200, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Commit drm/i915: create a prepare phase for sprite plane updates
changed the old_obj pointer we use when committing
Where there were duplicate variables for the tail, context and ring (engine)
in the gem request and the execlist queue item, use the one from the request
and remove the duplicate from the execlist queue item.
Issue: VIZ-4274
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
Add a reference and pointer from the execlist queue item to the associated
gem request. For execlist requests that don't have a request, create one
as a placeholder.
This patchset requires John Harrison's Replace seqno values with request
structures
patchset.
Issue: VIZ-4274
Signed-off-by: Nick
The first pass implementation of execlists required a backpointer to the
context to be held
in the intel_ringbuffer. However the context pointer is available higher in the
call stack.
Remove the backpointer from the ring buffer structure and instead pass it down
through the
call stack.
v2:
On Fri, Nov 07, 2014 at 02:21:18PM +0200, Ville Syrjälä wrote:
On Tue, Oct 28, 2014 at 06:33:11PM +, Arun Siluvery wrote:
The patches in this series adds two new workarounds for CHV and
removes pre-production ones.
Based on review comments from Ville, add/remove patches are split-up
On Fri, Nov 07, 2014 at 10:46:31AM -0800, Matt Turner wrote:
On Wed, Oct 29, 2014 at 2:12 PM, Kenneth Graunke kenn...@whitecape.org
wrote:
Haswell significantly improved the performance of sampler_c messages,
but the optimization appears to be off by default. Later platforms
remove this
On Fri, Nov 07, 2014 at 04:01:29PM -0800, Rodrigo Vivi wrote:
After think a bit I still think this is the patch to go to -fixes.
On the reorg series with 4 patches I just sent I add VBT parse and get
this idle_frame from there. But I'd prefer that regorg going to dinq
and this patch here to
On Thu, Nov 06, 2014 at 09:57:29AM +0200, Ville Syrjälä wrote:
On Tue, Nov 04, 2014 at 04:51:38AM -0800, Rodrigo Vivi wrote:
Patch drm/i915: Make the physical object coherent with GTT - Reviewer:
Already has my r-b.
I still would like to see a little testcase here, e.g. a new mode to
On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 09:57:29AM +0200, Ville Syrjälä wrote:
On Tue, Nov 04, 2014 at 04:51:38AM -0800, Rodrigo Vivi wrote:
Patch drm/i915: Make the physical object coherent with GTT - Reviewer:
Already has my r-b.
I
On Fri, Nov 07, 2014 at 02:58:37PM +, Dave Gordon wrote:
On 06/11/14 14:09, Daniel Vetter wrote:
On Wed, Nov 05, 2014 at 05:30:52PM +0200, Mika Kuoppala wrote:
This reverts commit 5cb13c07dae73380d8b3ddc792740487b8742938.
While the relevance for WaRsDontPollForAckOnClearingFWBits is
On Sat, Nov 08, 2014 at 02:57:58PM +0200, Imre Deak wrote:
On Fri, 2014-11-07 at 18:42 -0200, Paulo Zanoni wrote:
2014-11-05 16:48 GMT-02:00 Imre Deak imre.d...@intel.com:
While fixing [1] I noticed that we can simplify a couple of things in
the RPS enabling/disabling code. So I did that
On Mon, Nov 10, 2014 at 03:34:33PM +0200, Imre Deak wrote:
Paulo noticed that we don't support RPS on GEN9 yet, so WARN for and
ignore any RPS interrupts on that platform.
Signed-off-by: Imre Deak imre.d...@intel.com
Pulled in up to this one from this series, I'll wait for Paulo to
On 11/10/2014 4:38 PM, Mika Kuoppala wrote:
Arun Siluvery arun.siluv...@linux.intel.com writes:
From: Michel Thierry michel.thie...@intel.com
Following the legacy ring submission example, update the
ring-init_context() hook to support the execlist submission mode.
v2: update to use the new
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of john.c.harri...@intel.com
Sent: Thursday, October 30, 2014 6:41 PM
To: Intel-GFX@Lists.FreeDesktop.Org
Subject: [Intel-gfx] [PATCH 05/29] drm/i915: Replace last_[rwf]_seqno with
On Tue, Nov 11, 2014 at 10:22:11AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 09:57:29AM +0200, Ville Syrjälä wrote:
On Tue, Nov 04, 2014 at 04:51:38AM -0800, Rodrigo Vivi wrote:
Patch drm/i915: Make the physical
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
Of john.c.harri...@intel.com
Sent: Thursday, October 30, 2014 6:41 PM
To: Intel-GFX@Lists.FreeDesktop.Org
Subject: [Intel-gfx] [PATCH 15/29] drm/i915: Add IRQ friendly request
deference
On Tue, Nov 11, 2014 at 12:54:13PM +0100, Daniel Vetter wrote:
On Tue, Nov 11, 2014 at 10:22:11AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 09:57:29AM +0200, Ville Syrjälä wrote:
On Tue, Nov 04, 2014 at 04:51:38AM
On Tue, Nov 11, 2014 at 12:54:13PM +0100, Daniel Vetter wrote:
On Tue, Nov 11, 2014 at 10:22:11AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 09:57:29AM +0200, Ville Syrjälä wrote:
On Tue, Nov 04, 2014 at 04:51:38AM
On Mon, Nov 10, 2014 at 09:21:47PM +0200, Imre Deak wrote:
On Fri, 2014-11-07 at 12:08 +, Damien Lespiau wrote:
On Tue, Sep 16, 2014 at 04:19:07PM +0300, Imre Deak wrote:
@@ -1233,6 +1233,9 @@ static bool edp_panel_vdd_on(struct intel_dp
*intel_dp)
power_domain =
On Tue, Nov 11, 2014 at 02:16:32PM +0200, Ville Syrjälä wrote:
On Tue, Nov 11, 2014 at 12:54:13PM +0100, Daniel Vetter wrote:
On Tue, Nov 11, 2014 at 10:22:11AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 09:57:29AM
On Tue, Nov 11, 2014 at 12:26:59PM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 02:16:32PM +0200, Ville Syrjälä wrote:
On Tue, Nov 11, 2014 at 12:54:13PM +0100, Daniel Vetter wrote:
On Tue, Nov 11, 2014 at 10:22:11AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 11:20:14AM
On Tue, Nov 11, 2014 at 02:38:15PM +0200, Ville Syrjälä wrote:
On Tue, Nov 11, 2014 at 12:26:59PM +, Chris Wilson wrote:
This patch includes an unconditional clflush for phys writes (or at
least this patch should be that patch) which is what I thought we were
arguing about at the time.
On Tue, 2014-11-11 at 12:22 +, Damien Lespiau wrote:
On Mon, Nov 10, 2014 at 09:21:47PM +0200, Imre Deak wrote:
On Fri, 2014-11-07 at 12:08 +, Damien Lespiau wrote:
On Tue, Sep 16, 2014 at 04:19:07PM +0300, Imre Deak wrote:
@@ -1233,6 +1233,9 @@ static bool
On Mon, Nov 10, 2014 at 11:39 PM, Daniel Vetter dan...@ffwll.ch wrote:
Hi Ben,
The below patch from Jani also touches nouveau, can you please take a
look at it an ack? The core part + nouveau apply on top of drm-next,
the i915 part needs stuff from my next queue. So I'd prefer if we can
get
On Tue, Nov 11, 2014 at 10:12:00AM +0100, Daniel Vetter wrote:
Turned out to be much simpler on top of my latest atomic stuff than
what I've feared. Some details:
- Drop the modeset_lock_all snakeoil in drm_plane_init. Same
justification as for the equivalent change in drm_crtc_init done
On Fri, Nov 07, 2014 at 03:26:32PM +0200, Jani Nikula wrote:
On Fri, 07 Nov 2014, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Now that the backlight device no longer gets registered too early we
should be able to drop most of the INVALID_PIPE
On Tue, Nov 11, 2014 at 12:22:28PM +, Damien Lespiau wrote:
Have us always take the AUX power domain in the AUX -transfer vfunc.
This won't toggle the power well on/off for each transfer if we
correctly wrap known heavy users of the AUX channel, intel_dp_detect(),
intel_dp_get_edid(),
On Tue, Nov 11, 2014 at 11:34:58AM +, Michel Thierry wrote:
On 11/10/2014 4:38 PM, Mika Kuoppala wrote:
- int (*init_context)(struct intel_engine_cs *ring);
+ int (*init_context)(struct intel_ringbuffer *ringbuf);
What is the rationale of this? This seems odd.
On Tue, Nov 11, 2014 at 11:57:16AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 12:54:13PM +0100, Daniel Vetter wrote:
On Tue, Nov 11, 2014 at 10:22:11AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 09:57:29AM
Don't save the panel power sequencer register on vlv/chv for two simple
reasons. First, these are the wrong registers to save to begin
with. Second, they are not restored anyway.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_suspend.c | 3 +--
1 file changed, 1
Since RSTDBYCTL is only saved on non-KMS path in within i915_save_state,
move the restore in i915_restore_state for symmetry.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
UNTESTED!!!
---
drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On Mon, Nov 10, 2014 at 09:21:47PM +0200, Imre Deak wrote:
On Fri, 2014-11-07 at 12:08 +, Damien Lespiau wrote:
On Tue, Sep 16, 2014 at 04:19:07PM +0300, Imre Deak wrote:
@@ -1233,6 +1233,9 @@ static bool edp_panel_vdd_on(struct intel_dp
*intel_dp)
power_domain =
On Tue, Nov 11, 2014 at 02:16:32PM +0200, Ville Syrjälä wrote:
On Tue, Nov 11, 2014 at 12:54:13PM +0100, Daniel Vetter wrote:
On Tue, Nov 11, 2014 at 10:22:11AM +, Chris Wilson wrote:
On Tue, Nov 11, 2014 at 11:20:14AM +0100, Daniel Vetter wrote:
On Thu, Nov 06, 2014 at 09:57:29AM
On Tue, Nov 11, 2014 at 10:12:01AM +0100, Daniel Vetter wrote:
Motivated by the per-plane locking I've gone through all the get*
ioctls and reduced the locking to the bare minimum required.
v2: Rebase and make it compile ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
Just a
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate-patch_applied_pass_rate
BYT: pass/total=247/348-275/348
PNV:
On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote:
This is useful for checking things later.
v2:
- fix hsw infoframe enabled check (Ander)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_drv.h | 4 +++
drivers/gpu/drm/i915/intel_hdmi.c
On Tue, Nov 11, 2014 at 04:48:04PM +0200, Jani Nikula wrote:
Since RSTDBYCTL is only saved on non-KMS path in within i915_save_state,
move the restore in i915_restore_state for symmetry.
Makes sense. And IIRC this is an ilk-only register anyway, so frobbing it
on snb+ is dubious at best.
On Mon, Nov 10, 2014 at 06:09:45PM +0200, Ander Conselvan de Oliveira wrote:
Reviewed-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
On 11/06/2014 12:26 AM, Jesse Barnes wrote:
This only affects the fastboot path as-is. In that case, we simply need
to make sure
On Tue, Nov 11, 2014 at 04:48:03PM +0200, Jani Nikula wrote:
Don't save the panel power sequencer register on vlv/chv for two simple
reasons. First, these are the wrong registers to save to begin
with. Second, they are not restored anyway.
Indeed. I also like how the display save/restore
On Fri, Nov 07, 2014 at 02:20:17PM -0800, O'Rourke, Tom wrote:
On Fri, Nov 07, 2014 at 10:50:02AM +0100, Daniel Vetter wrote:
+ ret = sandybridge_pcode_read(dev_priv,
+ HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ ddcc_status);
On Sat, Nov 08, 2014 at 08:25:04AM +, Chris Wilson wrote:
On Fri, Nov 07, 2014 at 02:25:38PM -0800, O'Rourke, Tom wrote:
On Fri, Nov 07, 2014 at 10:41:26AM +, Chris Wilson wrote:
On Wed, Nov 05, 2014 at 05:31:34PM -0800, Tom.O'rou...@intel.com wrote:
From: Tom O'Rourke
On Fri, Nov 07, 2014 at 11:38:48AM -0200, Paulo Zanoni wrote:
2014-11-07 10:07 GMT-02:00 Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com:
The cleanup path would reset pll-new_config to NULL but wouldn't free
the allocated memory.
Reviewed-by: Paulo Zanoni
On Tue, Nov 11, 2014 at 04:00:12PM +0100, Daniel Vetter wrote:
On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote:
This is useful for checking things later.
v2:
- fix hsw infoframe enabled check (Ander)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
On Fri, Nov 07, 2014 at 05:20:48PM +0200, Mika Kuoppala wrote:
to see if one can fool hangcheck by keeping non hanging
ring busy
Cc: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tests/gem_reset_stats.c | 43
On Tue, Nov 11, 2014 at 05:19:46PM +0200, Ville Syrjälä wrote:
On Tue, Nov 11, 2014 at 04:00:12PM +0100, Daniel Vetter wrote:
On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote:
This is useful for checking things later.
v2:
- fix hsw infoframe enabled check (Ander)
On Fri, Nov 07, 2014 at 07:00:26PM +, Neil Roberts wrote:
The predicate source registers are needed to implement conditional
rendering without stalling. The two source registers are used to load
the previous values of the PS_DEPTH_COUNT register saved from
PIPE_CONTROL commands. These can
On Wed, Nov 12, 2014 at 08:40:47AM +0530, Deepak S wrote:
On Saturday 08 November 2014 01:03 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When reading a CCK register we should obviously read it from CCK not
Punit. This problem has been present
On 11/11/2014 8:58 PM, Daniel Vetter wrote:
On Wed, Nov 12, 2014 at 08:40:47AM +0530, Deepak S wrote:
On Saturday 08 November 2014 01:03 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
When reading a CCK register we should obviously read it from CCK
Following the legacy ring submission example, update the
ring-init_context() hook to support the execlist submission mode.
v2: update to use the new workaround macros and cleanup unused code.
This takes care of both bdw and chv workarounds.
v2.1: Add missing call to init_context() during
On Tue, 11 Nov 2014 16:23:03 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Nov 11, 2014 at 05:19:46PM +0200, Ville Syrjälä wrote:
On Tue, Nov 11, 2014 at 04:00:12PM +0100, Daniel Vetter wrote:
On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote:
This is useful for checking
Michel Thierry michel.thie...@intel.com writes:
Following the legacy ring submission example, update the
ring-init_context() hook to support the execlist submission mode.
v2: update to use the new workaround macros and cleanup unused code.
This takes care of both bdw and chv workarounds.
On Tue, Nov 11, 2014 at 04:13:09PM +0100, Daniel Vetter wrote:
On Sat, Nov 08, 2014 at 08:25:04AM +, Chris Wilson wrote:
On Fri, Nov 07, 2014 at 02:25:38PM -0800, O'Rourke, Tom wrote:
On Fri, Nov 07, 2014 at 10:41:26AM +, Chris Wilson wrote:
On Wed, Nov 05, 2014 at 05:31:34PM
Motivated by the per-plane locking I've gone through all the get*
ioctls and reduced the locking to the bare minimum required.
v2: Rebase and make it compile ...
v3: Review from Sean:
- Simplify return handling in getplane_res.
- Add a comment to getplane_res that the plane list is invariant and
Following the legacy ring submission example, update the
ring-init_context() hook to support the execlist submission mode.
v2: update to use the new workaround macros and cleanup unused code.
This takes care of both bdw and chv workarounds.
v2.1: Add missing call to init_context() during
Michel Thierry michel.thie...@intel.com writes:
Following the legacy ring submission example, update the
ring-init_context() hook to support the execlist submission mode.
v2: update to use the new workaround macros and cleanup unused code.
This takes care of both bdw and chv workarounds.
On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
From: Mika Kuoppala mika.kuopp...@linux.intel.com
As per latest pm guide, we need to do this also on
past hsw.
Yep, matches the doc.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
BTW I wonder why we also wait for the
On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
From: Mika Kuoppala mika.kuopp...@linux.intel.com
As per latest pm guide, we need to do this also on
past hsw.
Yep, matches the doc.
Reviewed-by: Ville
Use the new pipe config values to calculate the updated pll dividers.
This regression was introduced in
commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
Author: Ander Conselvan de Oliveira ander.conselvan.de.olive...@intel.com
Date: Wed Oct 29 11:32:33 2014 +0200
drm/i915: Add
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate-patch_applied_pass_rate
BYT: pass/total=247/348-277/348
PNV:
On Tue, 11 Nov 2014 09:29:18 -0800
Bob Paauwe bob.j.paa...@intel.com wrote:
Use the new pipe config values to calculate the updated pll dividers.
This regression was introduced in
commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
Author: Ander Conselvan de Oliveira
This should allow us to avoid mode sets for some panel fitter config
changes.
v2:
- fixup pfit comment (Ander)
v3:
- fixup pfit disable shortcut, only apply to gen4 for now (Jesse)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 73
This is useful for checking things later.
v2:
- fix hsw infoframe enabled check (Ander)
v3:
- set infoframe status in compute_config too (Ville)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
A userspace brightness range that is larger than the hardware
brightness range does not have a 1:1 mapping and can result
in brightness != actual_brightness for some values.
Expose a fixed brightness range of [0..1000] to userspace so
that all values can map 1:1 into the hardware brightness
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate-patch_applied_pass_rate
BYT: pass/total=247/348-277/348
PNV:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate-patch_applied_pass_rate
BYT: pass/total=247/348-275/348
PNV:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform: baseline_drm_intel_nightly_pass_rate-patch_applied_pass_rate
BYT: pass/total=247/348-277/348
PNV:
Motivated by the per-plane locking I've gone through all the get*
ioctls and reduced the locking to the bare minimum required.
v2: Rebase and make it compile ...
v3: Review from Sean:
- Simplify return handling in getplane_res.
- Add a comment to getplane_res that the plane list is invariant and
On Tue, 11 Nov 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Tue, Nov 11, 2014 at 04:48:03PM +0200, Jani Nikula wrote:
Don't save the panel power sequencer register on vlv/chv for two simple
reasons. First, these are the wrong registers to save to begin
with. Second, they are not
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