On Tue, Dec 02, 2014 at 11:02:59AM +1000, Dave Airlie wrote:
> On 29 November 2014 at 00:22, Daniel Vetter wrote:
> > On Fri, Nov 28, 2014 at 02:30:45PM +0100, Daniel Vetter wrote:
> >> Hi Dave,
> >>
> >> As discussed on irc here's the slightly late (because our QA cycle was a
> >> bit misaligned)
This is to add fill operation using GPGPU pipeline which is similar to
current media fill. This can be used to simply verify GPGPU pipeline
and help to enable it on newer HW, currently it works on Gen7 only and
will add support on later platform.
Now this sets very simply thread group dispatch for
This is simply a copy of gem_media_fill but using new
GPGPU fill operation.
Signed-off-by: Zhenyu Wang
---
tests/Makefile.sources | 1 +
tests/gem_gpgpu_fill.c | 141 +
2 files changed, 142 insertions(+)
create mode 100644 tests/gem_gpgpu_fill.c
i915_gem_obj_ggtt_pin() is marked as __must_check, but one callsite in
debugfs (i915_dump_lrc) was not checking the return value. Add the
necessary check and make the debugfs node print something
semi-reasonable if we were to fail to pin.
I believe there's already in-progress discussion on the ma
On 29 November 2014 at 00:22, Daniel Vetter wrote:
> On Fri, Nov 28, 2014 at 02:30:45PM +0100, Daniel Vetter wrote:
>> Hi Dave,
>>
>> As discussed on irc here's the slightly late (because our QA cycle was a
>> bit misaligned) final feature pull request for 3.19. I have a few fixes to
>> sort out i
Our .update_plane() handlers do the same check/prepare/commit/cleanup
steps regardless of plane type. Consolidate them all into a single
function that calls check/commit through a vtable.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_display.c | 113 ++
From: Gustavo Padovan
We need to get hdisplay and vdisplay in a few places so create a
helper to make our job easier.
Note that drm_crtc_check_viewport() and intel_modeset_pipe_config() were
previously making adjustments for doublescan modes and vscan > 1 modes,
which was incorrect. Using our n
All plane update functions need to unpin the old framebuffer when
flipping to a new one. Pull this logic into a separate function to ease
the integration with atomic plane helpers.
v2: Don't wait for vblank if we don't have an old fb to cleanup (Ander)
Signed-off-by: Matt Roper
---
drivers/gpu
From: Gustavo Padovan
Merge it into the plane update_plane() callback and make other
users use the update_plane() functions instead.
The fb != crtc->cursor->fb was already inside intel_crtc_cursor_set_obj()
so we fold intel_crtc_cursor_set_obj() inside intel_commit_cursor_plane()
and merge both
Primary and sprite planes have already been refactored to include a
'prepare' step which handles all the commit-time operations that could
fail (i.e., pinning buffers and such). Refactor the cursor commit in a
similar manner.
For simplicity and consistency with other plane types, we also switch t
If we extend the commit_plane handlers for each plane type to be able to
handle fb=0, then we can easily implement plane disable via the
update_plane handler. The cursor plane already works this way, and this
is the direction we need to go to integrate with the atomic plane
handler. We can now ki
The 'prepare' step for all types of planes are pretty similar;
consolidate the three 'prepare' functions into a single function. This
paves the way for future integration with the atomic plane handlers.
Note that we pull the 'wait for pending flips' functionality out of the
primary plane's prepar
Reviewed-by: Bob Paauwe
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_display.c | 34 +-
drivers/gpu/drm/i915/intel_drv.h | 3 +--
drivers/gpu/drm/i915/intel_sprite.c | 16
3 files changed, 26 insertions(+), 27 deletions(-)
diff
When disabling a plane, it is legal to pass crtc = NULL. Since planes
on Intel hardware are tied to a fixed CRTC, go ahead and set state->crtc
to the appropriate crtc in cases where it is passed to us as NULL.
In a future patch, we will start using the update handler for plane
disables, so this w
From: Gustavo Padovan
After some refactor intel_primary_plane_setplane() does the same
as intel_pipe_set_base() so we can get rid of it and replace the calls
with intel_primary_plane_setplane().
v2: take Ville's comments:
- get the right arguments for update_plane()
- use drm_crt
On 11/26/2014 11:44 PM, Chris Wilson wrote:
On Wed, Nov 26, 2014 at 01:53:34PM -0800, michael.h.ngu...@intel.com wrote:
From: "Michael H. Nguyen"
This is v5 of the series sent here:
http://lists.freedesktop.org/archives/intel-gfx/2014-November/055141.html
This version incorporates the follo
On Mon, Dec 01, 2014 at 10:29:04AM +0200, Ander Conselvan de Oliveira wrote:
> On 11/24/2014 09:53 PM, Matt Roper wrote:
...
> >-static int
> >-intel_prepare_sprite_plane(struct drm_plane *plane,
> >- struct intel_plane_state *state)
> >-{
> >-struct drm_device *dev = plan
On Mon, Dec 1, 2014 at 6:35 PM, Jani Nikula wrote:
>>> Would it be just as easy to construct a scenario that had an infroframe
>>> change that didn't get applied with the revert? Besides which a full
>>> modeset on every pan should be good motiviation to make them nonblocking
>>> (or at least use
On Mon, 01 Dec 2014, "Singh, Gaurav K" wrote:
> On 12/1/2014 7:41 PM, Jani Nikula wrote:
>> On Mon, 01 Dec 2014, Jani Nikula wrote:
>>> On Sat, 29 Nov 2014, Gaurav K Singh wrote:
For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequen
On Mon, Dec 1, 2014 at 5:56 PM, Daniel Vetter wrote:
> Alexey, please test this patch.
Ok, I will.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 12/1/2014 7:41 PM, Jani Nikula wrote:
On Mon, 01 Dec 2014, Jani Nikula wrote:
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports need
Partial revert of
commit 206645910b9796bff13fcdb67bdca166b724ba62
Author: Jesse Barnes
Date: Wed Nov 5 14:26:09 2014 -0800
drm/i915: check for audio and infoframe changes across mode sets v2
References: https://bugs.freedesktop.org/show_bug.cgi?id=86683
Signed-off-by: Jesse Barnes
---
d
On 12/01/2014 05:19 PM, Daniel Vetter wrote:
On Mon, Dec 01, 2014 at 04:34:16PM +, Tvrtko Ursulin wrote:
On 12/01/2014 04:07 PM, Daniel Vetter wrote:
On Mon, Dec 01, 2014 at 11:32:42AM +, Tvrtko Ursulin wrote:
On 11/28/2014 05:31 PM, Daniel Vetter wrote:
On Thu, Nov 27, 2014 at 02:5
On 12/1/2014 6:57 PM, Jani Nikula wrote:
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
enabled.
v2: Address review comments by Jani
- Added wait time for PLL to be locked.
Signed-off-by: Gaurav K Singh
Signed-off-
2014-11-20 19:01 GMT-02:00 Imre Deak :
> Atm, we don't disable RPS interrupts and related work items before
> resetting the GPU. This may interfere with the following GPU
> initialization and cause RPS interrupts to show up in PM_IIR too early
> before calling gen6_enable_rps_interrupts() (triggeri
On Mon, 01 Dec 2014, Daniel Vetter wrote:
> On Mon, Dec 01, 2014 at 04:37:41PM +, Chris Wilson wrote:
>> On Mon, Dec 01, 2014 at 05:30:41PM +0100, Daniel Vetter wrote:
>> > On Mon, Dec 01, 2014 at 04:09:07PM +, Chris Wilson wrote:
>> > > On Mon, Dec 01, 2014 at 08:04:30AM -0800, Jesse Barn
On Mon, Dec 01, 2014 at 03:04:50PM -0200, Paulo Zanoni wrote:
> 2014-12-01 14:36 GMT-02:00 Daniel Vetter :
> > On Mon, Dec 01, 2014 at 11:41:42AM -0200, Paulo Zanoni wrote:
> >> 2014-11-26 16:17 GMT-02:00 Daniel Vetter :
> >> > On Wed, Nov 26, 2014 at 01:37:07PM -0200, Paulo Zanoni wrote:
> >> >> 2
On 12/01/2014 05:16 PM, Daniel Vetter wrote:
On Mon, Dec 01, 2014 at 04:39:36PM +, Tvrtko Ursulin wrote:
On 12/01/2014 04:01 PM, Daniel Vetter wrote:
On Mon, Dec 01, 2014 at 02:46:29PM +, Tvrtko Ursulin wrote:
On 12/01/2014 11:32 AM, Tvrtko Ursulin wrote:
@@ -5430,9 +5434,12 @@ str
On Mon, Dec 01, 2014 at 02:47:06PM -0200, Paulo Zanoni wrote:
> 2014-12-01 14:34 GMT-02:00 Chris Wilson :
> > On Mon, Dec 01, 2014 at 02:29:11PM -0200, Paulo Zanoni wrote:
> >> 2014-11-20 19:01 GMT-02:00 Imre Deak :
> >> > Atm, igt/gem_reset_stats can trigger the recently added WARN on
> >> > left-
On Mon, 1 Dec 2014 17:16:25 +0100
Daniel Vetter wrote:
> On Mon, Dec 01, 2014 at 12:25:45PM +0200, Jani Nikula wrote:
> > On Thu, 06 Nov 2014, Jesse Barnes wrote:
> > > If these change (e.g. after a modeset following a fastboot), we need to
> > > do a full mode set.
> > >
> > > v2:
> > > - put
On Mon, Dec 01, 2014 at 04:37:41PM +, Chris Wilson wrote:
> On Mon, Dec 01, 2014 at 05:30:41PM +0100, Daniel Vetter wrote:
> > On Mon, Dec 01, 2014 at 04:09:07PM +, Chris Wilson wrote:
> > > On Mon, Dec 01, 2014 at 08:04:30AM -0800, Jesse Barnes wrote:
> > > > On Mon, 01 Dec 2014 12:25:45 +
On Mon, Dec 01, 2014 at 04:34:16PM +, Tvrtko Ursulin wrote:
>
> On 12/01/2014 04:07 PM, Daniel Vetter wrote:
> >On Mon, Dec 01, 2014 at 11:32:42AM +, Tvrtko Ursulin wrote:
> >>On 11/28/2014 05:31 PM, Daniel Vetter wrote:
> >>>On Thu, Nov 27, 2014 at 02:52:44PM +, Tvrtko Ursulin wrote:
On Mon, Dec 01, 2014 at 04:39:36PM +, Tvrtko Ursulin wrote:
>
> On 12/01/2014 04:01 PM, Daniel Vetter wrote:
> >On Mon, Dec 01, 2014 at 02:46:29PM +, Tvrtko Ursulin wrote:
> >>
> >>On 12/01/2014 11:32 AM, Tvrtko Ursulin wrote:
> >@@ -5430,9 +5434,12 @@ struct i915_vma *i915_gem_obj_to_
On Mon, 2014-12-01 at 14:47 -0200, Paulo Zanoni wrote:
> 2014-12-01 14:34 GMT-02:00 Chris Wilson :
> > On Mon, Dec 01, 2014 at 02:29:11PM -0200, Paulo Zanoni wrote:
> >> 2014-11-20 19:01 GMT-02:00 Imre Deak :
> >> > Atm, igt/gem_reset_stats can trigger the recently added WARN on
> >> > left-over PM
On Mon, Dec 01, 2014 at 02:42:37PM +, tim.g...@intel.com wrote:
> From: Tim Gore
>
> This test will not run on Android as the coreu service
> remains running even after the android system is stopped.
> Coreu is a client of drm and when the test finds this it
> fails an assert.
> Coreu is star
2014-12-01 14:36 GMT-02:00 Daniel Vetter :
> On Mon, Dec 01, 2014 at 11:41:42AM -0200, Paulo Zanoni wrote:
>> 2014-11-26 16:17 GMT-02:00 Daniel Vetter :
>> > On Wed, Nov 26, 2014 at 01:37:07PM -0200, Paulo Zanoni wrote:
>> >> 2014-11-24 14:02 GMT-02:00 Daniel Vetter :
>> >> > Apparently PCH fifo un
Otherwise we'll have backtraces in assert_panel_unlocked because the
BIOS locks the register. In the reporter's case this regression was
introduced in
commit c31407a3672aaebb4acddf90944a114fa5c8af7b
Author: Chris Wilson
Date: Thu Oct 18 21:07:01 2012 +0100
drm/i915: Add no-lvds quirk for S
On Mon, Dec 01, 2014 at 06:01:05PM +0200, Mika Kuoppala wrote:
> From: Mika Kuoppala
>
> The conversion table can be replaced with simple enough function.
>
>text data bss dec hex filename
> 839688 10987 24 850699 cfb0b drivers/gpu/drm/i915/i915.ko
> 83
2014-12-01 14:34 GMT-02:00 Chris Wilson :
> On Mon, Dec 01, 2014 at 02:29:11PM -0200, Paulo Zanoni wrote:
>> 2014-11-20 19:01 GMT-02:00 Imre Deak :
>> > Atm, igt/gem_reset_stats can trigger the recently added WARN on
>> > left-over PM_IIR bits in gen6_enable_rps_interrupts(). There are two
>> > rea
On Mon, Dec 01, 2014 at 04:04:18PM +0200, Ander Conselvan de Oliveira wrote:
> On 11/24/2014 09:53 PM, Matt Roper wrote:
> >+/**
> >+ * intel_disable_plane - disable a plane
> >+ * @plane: plane to disable
> >+ *
> >+ * General disable handler for all plane types.
> >+ */
> >+int
> >+intel_disable_
On Mon, Dec 01, 2014 at 12:44:12PM +, John Harrison wrote:
> On 28/11/2014 18:06, Daniel Vetter wrote:
> >On Fri, Nov 28, 2014 at 05:49:26PM +, John Harrison wrote:
> >>On 26/11/2014 13:43, Daniel Vetter wrote:
> >>>On Mon, Nov 24, 2014 at 06:49:43PM +, john.c.harri...@intel.com wrote:
On Mon, 2014-12-01 at 14:29 -0200, Paulo Zanoni wrote:
> 2014-11-20 19:01 GMT-02:00 Imre Deak :
> > Atm, igt/gem_reset_stats can trigger the recently added WARN on
> > left-over PM_IIR bits in gen6_enable_rps_interrupts(). There are two
> > reasons for this:
> > 1. we call intel_enable_gt_powersave
On 12/01/2014 04:01 PM, Daniel Vetter wrote:
On Mon, Dec 01, 2014 at 02:46:29PM +, Tvrtko Ursulin wrote:
On 12/01/2014 11:32 AM, Tvrtko Ursulin wrote:
@@ -5430,9 +5434,12 @@ struct i915_vma *i915_gem_obj_to_ggtt(struct
drm_i915_gem_object *obj)
{
struct i915_vma *vma;
-vma =
On Mon, Dec 01, 2014 at 05:30:41PM +0100, Daniel Vetter wrote:
> On Mon, Dec 01, 2014 at 04:09:07PM +, Chris Wilson wrote:
> > On Mon, Dec 01, 2014 at 08:04:30AM -0800, Jesse Barnes wrote:
> > > On Mon, 01 Dec 2014 12:25:45 +0200
> > > Jani Nikula wrote:
> > >
> > > > On Thu, 06 Nov 2014, Jes
On Mon, Dec 01, 2014 at 11:41:42AM -0200, Paulo Zanoni wrote:
> 2014-11-26 16:17 GMT-02:00 Daniel Vetter :
> > On Wed, Nov 26, 2014 at 01:37:07PM -0200, Paulo Zanoni wrote:
> >> 2014-11-24 14:02 GMT-02:00 Daniel Vetter :
> >> > Apparently PCH fifo underruns are tricky, we have plenty reports that
>
On 12/01/2014 04:07 PM, Daniel Vetter wrote:
On Mon, Dec 01, 2014 at 11:32:42AM +, Tvrtko Ursulin wrote:
On 11/28/2014 05:31 PM, Daniel Vetter wrote:
On Thu, Nov 27, 2014 at 02:52:44PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/driver
On Mon, Dec 01, 2014 at 02:29:11PM -0200, Paulo Zanoni wrote:
> 2014-11-20 19:01 GMT-02:00 Imre Deak :
> > Atm, igt/gem_reset_stats can trigger the recently added WARN on
> > left-over PM_IIR bits in gen6_enable_rps_interrupts(). There are two
> > reasons for this:
> > 1. we call intel_enable_gt_po
On Mon, Dec 01, 2014 at 04:11:15PM +, Dave Gordon wrote:
> On 20/11/14 09:19, Daniel Vetter wrote:
> > On Thu, Nov 20, 2014 at 08:10:27AM +, Chris Wilson wrote:
> >> On Thu, Nov 20, 2014 at 12:33:08AM +0100, Daniel Vetter wrote:
> >>> Now that sanity prevails and we have the clean split bet
On Mon, Dec 01, 2014 at 04:09:07PM +, Chris Wilson wrote:
> On Mon, Dec 01, 2014 at 08:04:30AM -0800, Jesse Barnes wrote:
> > On Mon, 01 Dec 2014 12:25:45 +0200
> > Jani Nikula wrote:
> >
> > > On Thu, 06 Nov 2014, Jesse Barnes wrote:
> > > > If these change (e.g. after a modeset following a
2014-11-20 19:01 GMT-02:00 Imre Deak :
> Atm, igt/gem_reset_stats can trigger the recently added WARN on
> left-over PM_IIR bits in gen6_enable_rps_interrupts(). There are two
> reasons for this:
> 1. we call intel_enable_gt_powersave() without a preceeding
>intel_disable_gt_powersave()
> 2. ge
On 20/11/14 09:19, Daniel Vetter wrote:
> On Thu, Nov 20, 2014 at 08:10:27AM +, Chris Wilson wrote:
>> On Thu, Nov 20, 2014 at 12:33:08AM +0100, Daniel Vetter wrote:
>>> Now that sanity prevails and we have the clean split between software
>>> init and starting the engines we can drop all the "
On Mon, Dec 01, 2014 at 12:25:45PM +0200, Jani Nikula wrote:
> On Thu, 06 Nov 2014, Jesse Barnes wrote:
> > If these change (e.g. after a modeset following a fastboot), we need to
> > do a full mode set.
> >
> > v2:
> > - put under pipe_config check so we don't deref a null state (Jesse)
> >
> >
On Mon, Dec 01, 2014 at 08:04:30AM -0800, Jesse Barnes wrote:
> On Mon, 01 Dec 2014 12:25:45 +0200
> Jani Nikula wrote:
>
> > On Thu, 06 Nov 2014, Jesse Barnes wrote:
> > > If these change (e.g. after a modeset following a fastboot), we need to
> > > do a full mode set.
> > >
> > > v2:
> > > -
On Mon, Dec 01, 2014 at 11:32:42AM +, Tvrtko Ursulin wrote:
> On 11/28/2014 05:31 PM, Daniel Vetter wrote:
> >On Thu, Nov 27, 2014 at 02:52:44PM +, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>diff --git a/drivers/gpu/drm/i915/i915_gem.c
> >>b/drivers/gpu/drm/i915/i915_gem.c
> >>ind
On Mon, 01 Dec 2014 12:25:45 +0200
Jani Nikula wrote:
> On Thu, 06 Nov 2014, Jesse Barnes wrote:
> > If these change (e.g. after a modeset following a fastboot), we need to
> > do a full mode set.
> >
> > v2:
> > - put under pipe_config check so we don't deref a null state (Jesse)
> >
> > Sign
On Mon, Dec 01, 2014 at 02:46:29PM +, Tvrtko Ursulin wrote:
>
> On 12/01/2014 11:32 AM, Tvrtko Ursulin wrote:
> >>>@@ -5430,9 +5434,12 @@ struct i915_vma *i915_gem_obj_to_ggtt(struct
> >>>drm_i915_gem_object *obj)
> >>> {
> >>> struct i915_vma *vma;
> >>>
> >>>-vma = list_first_entry
From: Mika Kuoppala
The conversion table can be replaced with simple enough function.
textdata bss dec hex filename
839688 10987 24 850699 cfb0b drivers/gpu/drm/i915/i915.ko
839224 10987 24 850235 cf93b drivers/gpu/drm/i915/i915.ko
Result is 494 saved by
On 12/01/2014 11:32 AM, Tvrtko Ursulin wrote:
@@ -5430,9 +5434,12 @@ struct i915_vma *i915_gem_obj_to_ggtt(struct
drm_i915_gem_object *obj)
{
struct i915_vma *vma;
-vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
-if (vma->vm != i915_obj_to_ggtt(obj))
-re
From: Tim Gore
This test will not run on Android as the coreu service
remains running even after the android system is stopped.
Coreu is a client of drm and when the test finds this it
fails an assert.
Coreu is started by the init process and there is no
tidy, non invasive way to stop it (init ju
On Mon, 01 Dec 2014, Jani Nikula wrote:
> On Sat, 29 Nov 2014, Gaurav K Singh wrote:
>> For Dual Link MIPI Panels, both Port A and Port C should be enabled
>> during the MIPI encoder enabling sequence. Similarly, during the
>> disabling sequence, both ports needs to be disabled.
>>
>> v2: Used fo
On 11/24/2014 09:53 PM, Matt Roper wrote:
If we extend the commit_plane handlers for each plane type to be able to
handle fb=0, then we can easily implement plane disable via the
update_plane handler. The cursor plane already works this way, and this
is the direction we need to go to integrate w
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
> Hi,
>
> These set of patches build on top of the existing DSI Video mode support to
> enable dual link MIPI panels with high resolutions. These patches have been
> tested on a 25x16 panel and works well.
Good job, it's starting to look good. Please go
On 11/24/2014 09:53 PM, Matt Roper wrote:
All plane update functions need to unpin the old framebuffer when
flipping to a new one. Pull this logic into a separate function to ease
the integration with atomic plane helpers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_display.c |
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
> This patch is in preparation of DSI dual link panels. For dual link
> panels, few packets needs to be sent to Port A or Port C or both. Based
> on the portno from MIPI Sequence Block#53, these sequences needs to be
> sent accordingly.
>
> Signed-off-by:
2014-11-26 16:17 GMT-02:00 Daniel Vetter :
> On Wed, Nov 26, 2014 at 01:37:07PM -0200, Paulo Zanoni wrote:
>> 2014-11-24 14:02 GMT-02:00 Daniel Vetter :
>> > Apparently PCH fifo underruns are tricky, we have plenty reports that
>> > we see the occasional underrun (especially at boot-up).
>> >
>> >
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be
> enabled.
>
> v2: Address review comments by Jani
> - Added wait time for PLL to be locked.
>
> Signed-off-by: Gaurav K Singh
> Signed-off-by: Shobhit Kumar
> ---
> driv
On Sat, 29 Nov 2014, Gaurav K Singh wrote:
> For Dual Link MIPI Panels, both Port A and Port C should be enabled
> during the MIPI encoder enabling sequence. Similarly, during the
> disabling sequence, both ports needs to be disabled.
>
> v2: Used for_each_dsi_port macro instead of for loop
>
> Si
On Mon, 2014-12-01 at 15:59 +0530, Sagar Arun Kamble wrote:
> Thanks Daniel.
> This particular commit is moving power_domain_init into resume early.
> Does not have details about ordering with uncore early sanitize and
> uncore sanitize.
>
> Imre,
> Can you please clarify why this ordering with po
On 28/11/2014 18:06, Daniel Vetter wrote:
On Fri, Nov 28, 2014 at 05:49:26PM +, John Harrison wrote:
On 26/11/2014 13:43, Daniel Vetter wrote:
On Mon, Nov 24, 2014 at 06:49:43PM +, john.c.harri...@intel.com wrote:
From: John Harrison
The ring member of the object structure was always
On Mon, 01 Dec 2014, Jay Aurabind wrote:
>> Please file a new bug at [1], reference this mail, and attach
>> /sys/kernel/debug/dri/0/i915_opregion.
>
> Thank you for the response. But the file you mentioned to attach seems to be
> a binary file, because I'm getting lot of junk characters. Is this
On 12/01/2014 03:04 PM, Jani Nikula wrote:
> On Fri, 28 Nov 2014, Jay Aurabind wrote:
>> Hello all,
>>
>> I notice that some activity has been going on with the minimum value
>> of display brightness recently (e1c412e7575).
>>
>> But the minimum value thats currently chosen is not at all acceptabl
On 11/28/2014 05:31 PM, Daniel Vetter wrote:
On Thu, Nov 27, 2014 at 02:52:44PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.
Added a GGTT view concept an
On Mon, Dec 1, 2014 at 10:10 AM, Daniel Vetter wrote:
> Can you please boot with drm.debug=0xe and then grab the entire boot dmesg
> (up to the backtrace).
>
Here it is.
Regards,
Alexey
[0.00] Linux version 3.17.4-sm1118 (root@sm-build) (gcc version 4.8.2 (GCC) ) #1 SMP Sat Nov 22 22:39:
Thanks Daniel.
This particular commit is moving power_domain_init into resume early.
Does not have details about ordering with uncore early sanitize and
uncore sanitize.
Imre,
Can you please clarify why this ordering with power domain init was
done?
Thanks,
Sagar
On Mon, 2014-12-01 at 10:16 +010
On Thu, 06 Nov 2014, Jesse Barnes wrote:
> If these change (e.g. after a modeset following a fastboot), we need to
> do a full mode set.
>
> v2:
> - put under pipe_config check so we don't deref a null state (Jesse)
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_display.c |
On Fri, 28 Nov 2014, Chris Wilson wrote:
> On Fri, Nov 28, 2014 at 04:55:11PM +0200, Ville Syrjälä wrote:
>> On Thu, Nov 27, 2014 at 04:23:12PM +0200, Mika Kuoppala wrote:
>> > to a procedural to save space.
>
> I really don't like this style of changelog (run on sentences from
> the subject).
Ag
On Fri, 28 Nov 2014, Jay Aurabind wrote:
> Hello all,
>
> I notice that some activity has been going on with the minimum value
> of display brightness recently (e1c412e7575).
>
> But the minimum value thats currently chosen is not at all acceptable
> for my eyes. My display is working perfectly wi
On Mon, Dec 01, 2014 at 12:29:34PM +0530, sagar.a.kam...@intel.com wrote:
> From: Akash Goel
>
> During resume, modeset was being performed independent of DPMS state which
> increased resume time as well as it kept display wells ON. With this change
> this modeset will be skipped.
>
> Signed-off
On Mon, Dec 01, 2014 at 12:28:05PM +0530, sagar.a.kam...@intel.com wrote:
> From: Sagar Kamble
>
> Due to disabling of RC6 in uncore_sanitize in early resume, power is drained
> till it RC6 is re-enabled post resume.
> With this change RC6 disabling will be done at beginning of resume only.
> Thi
On Sun, Nov 30, 2014 at 11:14:26PM +0100, Alexey Orishko wrote:
> Hi all,
>
> I hope I'm sending this to the correct mailing list (if not, please,
> suggest a proper one).
>
> I'm using kernel 3.17.4 32-bit (custom build) and during boot I got a
> crash in i915 driver. It happens on the motherboa
Hello all,
I notice that some activity has been going on with the minimum value of display
brightness recently (e1c412e7575).
But the minimum value thats currently chosen is not at all acceptable for my
eyes. My display is working perfectly without that restriction on minimum
intensity.
I tend
Hi all,
We're pleased to announce a public release to Intel Graphics Virtualization
Technology (Intel GVT-g, formerly known as XenGT). Intel GVT-g is a complete
vGPU solution with mediated pass-through, supported today on 4th generation
Intel Core(TM) processors with Intel Graphics processors
On Mon, Dec 01, 2014 at 03:04:27AM +, Cheng, Yao wrote:
> > -Original Message-
> > From: Beckett, Robert
> > Sent: Saturday, November 29, 2014 0:59
> > To: Cheng, Yao; intel-gfx@lists.freedesktop.org; dri-
> > de...@lists.freedesktop.org; daniel.vet...@ffwll.ch; Kelley, Sean V; Chehab,
On 11/24/2014 09:53 PM, Matt Roper wrote:
The 'prepare' step for all types of planes are pretty similar;
consolidate the three 'prepare' functions into a single function. This
paves the way for future integration with the atomic plane handlers.
Note that we pull the 'wait for pending flips' fun
On 11/24/2014 09:53 PM, Matt Roper wrote:
Primary and sprite planes have already been refactored to include a
'prepare' step which handles all the commit-time operations that could
fail (i.e., pinning buffers and such). Refactor the cursor commit in a
similar manner.
For simplicity and consiste
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