On Tue, 09 Dec 2014, Dave Airlie airl...@gmail.com wrote:
Missed this version, see my reply to v1:
http://mid.gmane.org/87k32iqppg@intel.com
Also, what if you avoid sink dpms off with:
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index
On Tue, 09 Dec 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
DSI Pll1 is used for enabling DSI on Port C.
v2: Addressed review comments of Jani
- Used operator instead of == for intel_dsi-ports
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Reviewed-by: Jani Nikula
On 8 December 2014 at 22:55, Daniel Vetter daniel.vet...@ffwll.ch wrote:
When we unplug a dp mst branch we unreference the entire tree from
the root towards the leaves. Which is ok, since that's the way the
pointers and so also the refcounts go.
But when we drop the reference we must make
On Tue, 09 Dec 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Due to hardware limitations on BYT, MIPI Port C DPI Enable bit
does not get set. To check whether DSI Port C was enabled in BIOS,
check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
is linked with Pipe B.
v2:
On Sun, 07 Dec 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Common bit to be used for both DSI Port A DSI Port C.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
At some point I'd like to have the bits specific to port A only
extracted outside of the for loop, but this is fine
On Tue, 09 Dec 2014, Fennec Fox fennect...@gmail.com wrote:
do you know how to make the intel-drm-nightly kernel mentioned in this
bugfix id like to use that until 3.19 lands
It's the drm-intel-nightly branch of the upstream drm intel repository
[1]. The patch seems to apply cleanly on 3.18
On Mon, 2014-12-08 at 21:14 +0100, Daniel Vetter wrote:
On Mon, Dec 08, 2014 at 06:42:04PM +0200, Imre Deak wrote:
The current hda/i915 interface to enable/disable power wells and query
the CD clock rate is based on looking up the relevant i915 module
symbols from the hda driver. By using
On 12/08/2014 07:04 PM, Jani Nikula wrote:
On Mon, 08 Dec 2014, Jani Nikula jani.nik...@linux.intel.com wrote:
On Mon, 08 Dec 2014, Aaron Lu aaron...@intel.com wrote:
We have a new bug report that has the same problem:
https://bugzilla.kernel.org/show_bug.cgi?id=88941
The posted patch solves
Register a component to be used to interface with the snd_hda_intel
driver. This is meant to replace the same interface that is currently
based on module symbol lookup.
v2:
- change roles between the hda and i915 components (Daniel)
- add the implementation to a new file (Jani)
- use better
Register a component master to be used to interface with the i915
driver. This is meant to replace the current interface which is based on
module symbol lookups.
Note that currently we keep the existing behavior and pin the i915
module while the hda driver is loaded. Using the component interface
This will be needed by later patches, so factor it out.
No functional change.
v2:
- s/dev_to_i915_priv/dev_to_i915/ (Jani)
- don't use the helper in i915_pm_suspend (Chris)
- simplify the helper (Chris)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 9
On Mon, Dec 08, 2014 at 01:55:56PM -0800, Rodrigo Vivi wrote:
On Tue, Nov 25, 2014 at 5:04 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Nov 24, 2014 at 08:29:40AM -0800, Rodrigo Vivi wrote:
From: Zhipeng Gong zhipeng.g...@intel.com
On Broadwell GT3 we have 2 Video Command Streamers
On Tue, Dec 09, 2014 at 10:34:40AM +0200, Jani Nikula wrote:
On Tue, 09 Dec 2014, Gaurav K Singh gaurav.k.si...@intel.com wrote:
Due to hardware limitations on BYT, MIPI Port C DPI Enable bit
does not get set. To check whether DSI Port C was enabled in BIOS,
check the Pipe B enable bit for
On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on the DVO port from VBT block 2.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
---
On Mon, Dec 08, 2014 at 01:48:01PM -0800, Rodrigo Vivi wrote:
On Mon, Dec 8, 2014 at 8:49 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Dec 08, 2014 at 02:09:11PM -0200, Paulo Zanoni wrote:
+ * compress/decompress. However there are many known cases where we have
to
+ * forcibly
On Tue, Dec 09, 2014 at 10:59:54AM +0200, Imre Deak wrote:
On Mon, 2014-12-08 at 21:14 +0100, Daniel Vetter wrote:
On Mon, Dec 08, 2014 at 06:42:04PM +0200, Imre Deak wrote:
The current hda/i915 interface to enable/disable power wells and query
the CD clock rate is based on looking up the
On Tue, Dec 09, 2014 at 11:41:16AM +0200, Imre Deak wrote:
+static inline struct drm_i915_private *dev_to_i915(struct device *dev)
+{
+ return to_i915(pci_get_drvdata(to_pci_dev(dev)));
+}
dev_get_drvdata. No need to upcast to pci_dev for pci_get_drvdata to
downcast to device again. Let's
On Tue, Dec 09, 2014 at 11:41:17AM +0200, Imre Deak wrote:
Register a component to be used to interface with the snd_hda_intel
driver. This is meant to replace the same interface that is currently
based on module symbol lookup.
v2:
- change roles between the hda and i915 components (Daniel)
On Tue, Dec 09, 2014 at 11:41:18AM +0200, Imre Deak wrote:
Register a component master to be used to interface with the i915
driver. This is meant to replace the current interface which is based on
module symbol lookups.
Note that currently we keep the existing behavior and pin the i915
On Tue, Dec 09, 2014 at 10:59:15AM +0530, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
The pipe wm parameters is not correctly updated with sprite parameters
because it copies them for each plane from plane_list to the sprite
offset in pipe wm parameters. Since
On Tue, 09 Dec 2014, Singh, Gaurav K gaurav.k.si...@intel.com wrote:
On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on the DVO port from VBT block 2.
On Tue, 09 Dec 2014, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Dec 09, 2014 at 11:41:17AM +0200, Imre Deak wrote:
Register a component to be used to interface with the snd_hda_intel
driver. This is meant to replace the same interface that is currently
based on module symbol lookup.
v2:
On Wed, Dec 03, 2014 at 02:13:58PM +, Damien Lespiau wrote:
On Tue, Oct 28, 2014 at 06:39:27PM +0530, akash.g...@intel.com wrote:
@@ -1126,6 +1136,8 @@ static void
drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem)
/* We may need to evict a few entries in order
Yes, that can be done but that might involve more changes and testing.
I am not sure who can signup for this, I can check with people though.
But for now to fix the sprite plane wm this check would be required.
Regards,
Sonika
-Original Message-
From: Daniel Vetter
Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 41 +
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
From: Dave Gordon david.s.gor...@intel.com
There is a workaround for a hardware bug when reading the seqno from the status
page. The bug does not exist on VLV however, the workaround was still being
applied.
Change-Id: Ic781fdb31e1f794ce1fa8a6d0d5ee379756c5db6
Signed-off-by: Dave Gordon
From: John Harrison john.c.harri...@intel.com
There is a trace point in the legacy execbuffer execution path that is missing
from the execlist path. Trace points are extremely useful for debugging and are
used by various automated validation tests. Hence, this patch adds the missing
trace point
From: John Harrison john.c.harri...@intel.com
The scheduler needs to explicitly allocate a request to track each submitted
batch buffer. This must happen a long time before any commands are actually
written to the ring.
Change-Id: Id01fbda123bcfaa84531896c38292435270025b1
For: VIZ-1587
From: John Harrison john.c.harri...@intel.com
The scheduler decouples the submission of batch buffers to the driver with their
submission to the hardware. This basically means splitting the execbuffer()
function in half. This change rearranges some code ready for the split to occur.
Change-Id:
From: Dave Gordon david.s.gor...@intel.com
When querying the GTFIFOCTL register to check the FIFO space, the read value
must be masked. The operation is repeated explicitly in several places. This
change refactors the read-and-mask code into a function call.
Change-Id:
From: Dave Gordon david.s.gor...@intel.com
Added various definitions that will be useful for the scheduler in general and
pre-emptive context switching in particular.
Change-Id: Ica805b94160426def51f5d520f5ce51c60864a98
For: VIZ-1587
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
From: John Harrison john.c.harri...@intel.com
Cache a pointer to the ringbuf so that retire requests does not need to do messy
'are we in execlist mode' decisions.
Change-Id: I75bf6b73dc8a675a5be7bbff1927aa30f393788c
For: VIZ-1587
Signed-off-by: John Harrison john.c.harri...@intel.com
---
From: John Harrison john.c.harri...@intel.com
Split the execbuffer() function in half. The first half collects and validates
all the information requried to process the batch buffer. It also does all the
object pinning, relocations, active list management, etc - basically anything
that must be
From: John Harrison john.c.harri...@intel.com
Assorted patches to make the tree more friendly to the GPU scheduler.
The biggest change is to re-organise the execbuff code path. Basically, the
scheduler needs to split the submission path into two sections which are
essentially software only (data
From: John Harrison john.c.harri...@intel.com
There is a flags word that is passed through the execbuffer code path all the
way from initial decoding of the user parameters down to the very final dispatch
buffer call. It is simply called 'flags'. Unfortuantely, there are many other
flags words
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Mon, Dec 08, 2014 at 02:33:46PM -0800, michael.h.ngu...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is
On Mon, Dec 08, 2014 at 02:33:49PM -0800, michael.h.ngu...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
By adding a new exec_entry flag, we cleanly mark the shadow objects
as purgeable after they are on the active list.
v2:
- Move 'shadow_batch_obj-madv =
On Mon, Dec 08, 2014 at 02:33:50PM -0800, michael.h.ngu...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Move it to a separate function since the main do_execbuffer function
already has so much going on.
v2:
- Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7
On Tue, 09 Dec 2014, Mika Kuoppala mika.kuopp...@linux.intel.com wrote:
Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
On Tue, Dec 09, 2014 at 03:32:05PM +0200, Jani Nikula wrote:
On Tue, 09 Dec 2014, Mika Kuoppala mika.kuopp...@linux.intel.com wrote:
Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
On 12/5/2014 2:41 PM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote:
On Thu, Dec 04, 2014 at 03:07:52PM +, Michel Thierry wrote:
We already have it for chv, but was missing for bdw.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
On 12/9/2014 4:00 PM, Jani Nikula wrote:
On Tue, 09 Dec 2014, Singh, Gaurav K gaurav.k.si...@intel.com wrote:
On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on
From: Ville Syrjälä ville.syrj...@linux.intel.com
On CHV we sometimes see not just one but two bad CRCs. No real idea
what would cause that, but let's just throw away the second CRC as
well to gain some stability for the tests.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
On 12/5/2014 12:11 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.
Added a GGTT view concept and linked it with the VMA to distinguish
From: Ville Syrjälä ville.syrj...@linux.intel.com
Report SKIP only if none of the pipe/connector combos worked, instead of
trying to report for each pipe separately.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
tests/kms_mmio_vs_cs_flip.c | 36
On 12/5/2014 12:11 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A short section describing background, implementation and intended usage.
For: VIZ-4544
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
Documentation/DocBook/drm.tmpl | 5
Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.
v2: s/fw_domain/forcewake_domain (Jani)
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 45
'i915_gpu_state' debugfs entry can be used to
capture the current gpu state. This is similar to
what one would get from 'i915_error_state' if gpu
error state would have been captured.
The motivation for this was to enhance our toolbox
so that we can direct bug reporters to do things like:
'grep
In the following commits, we want to capture the hw state
also without any errors. Carve out the helper out from error
capture parts.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_gpu_error.c | 41 +++
1 file changed, 27
This is a similar to 'i915_gpu_state' but more dangerous
as it doesn't try to lock nor idle the gpu before grabbing
the state. But the obvious advantages are that one can
inspect the current running gpu state and also get a state
dump even if mutex is hold.
As we don't want a unsuspecting user to
Emphasize the more general applicability of the seekable
string buffer by decoupling it from error handling.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 14 +++
Register a component to be used to interface with the snd_hda_intel
driver. This is meant to replace the same interface that is currently
based on module symbol lookup.
v2:
- change roles between the hda and i915 components (Daniel)
- add the implementation to a new file (Jani)
- use better
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
Register a component master to be used to interface with the i915
driver. This is meant to replace the current interface which is based on
module symbol lookups.
Note that currently we keep the existing behavior and pin the i915
module while the hda driver is loaded. Using the component interface
This will be needed by later patches, so factor it out.
No functional change.
v2:
- s/dev_to_i915_priv/dev_to_i915/ (Jani)
- don't use the helper in i915_pm_suspend (Chris)
- simplify the helper (Chris)
v3:
- remove redundant upcasting in the helper (Daniel)
Signed-off-by: Imre Deak
On Tue, Dec 09, 2014 at 10:54:25AM +, Chris Wilson wrote:
On Wed, Dec 03, 2014 at 02:13:58PM +, Damien Lespiau wrote:
On Tue, Oct 28, 2014 at 06:39:27PM +0530, akash.g...@intel.com wrote:
@@ -1126,6 +1136,8 @@ static void
drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem
On Tue, 2014-12-09 at 11:03 +0100, Daniel Vetter wrote:
On Tue, Dec 09, 2014 at 10:59:54AM +0200, Imre Deak wrote:
On Mon, 2014-12-08 at 21:14 +0100, Daniel Vetter wrote:
On Mon, Dec 08, 2014 at 06:42:04PM +0200, Imre Deak wrote:
The current hda/i915 interface to enable/disable power
intel-gpu-tools now generates the render state with license headers and
the version of i-g-t that generated the files.
A similar patch was previously sent but wasn't actually generated with
the make target so was lacking the i-g-t revision. So here another
version before we totally forget about
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
tests/kms_cursor_crc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index 7a8f34a..875ac30 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms_cursor_crc.c
@@ -245,7
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
tests/drv_hangman.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c
index ec28c9d..15918ba 100644
--- a/tests/drv_hangman.c
+++ b/tests/drv_hangman.c
@@ -150,19 +150,6 @@ static
At Tue, 9 Dec 2014 11:19:34 +0100,
Daniel Vetter wrote:
On Tue, Dec 09, 2014 at 11:41:18AM +0200, Imre Deak wrote:
Register a component master to be used to interface with the i915
driver. This is meant to replace the current interface which is based on
module symbol lookups.
Note
At Tue, 09 Dec 2014 18:56:07 +0200,
Imre Deak wrote:
On Tue, 2014-12-09 at 11:03 +0100, Daniel Vetter wrote:
On Tue, Dec 09, 2014 at 10:59:54AM +0200, Imre Deak wrote:
On Mon, 2014-12-08 at 21:14 +0100, Daniel Vetter wrote:
On Mon, Dec 08, 2014 at 06:42:04PM +0200, Imre Deak wrote:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -5 311/311
On Tue, 11 Nov 2014 12:30:47 -0800
Jesse Barnes jbar...@virtuousgeek.org wrote:
This should allow us to avoid mode sets for some panel fitter config
changes.
v2:
- fixup pfit comment (Ander)
v3:
- fixup pfit disable shortcut, only apply to gen4 for now (Jesse)
Daniel pointed out
From: Chris Wilson ch...@chris-wilson.co.uk
We don't need to incur the overhead of checking whether the object is
pinned prior to changing its madvise. If the object is pinned, the
madvise will not take effect until it is unpinned and so we cannot free
the pages being pointed at by hardware.
From: Chris Wilson ch...@chris-wilson.co.uk
When constructing a batchbuffer, it is sometimes crucial to know the
largest hole into which we can fit a fenceable buffer (for example when
handling very large objects on gen2 and gen3). This depends on the
fragmentation of pinned buffers inside the
Similar to:
commit 02c9f7e3cfe76a7f54ef03438c36aade86cc1c8b
Author: Kenneth Graunke kenn...@whitecape.org
Date: Mon Jan 27 14:20:16 2014 -0800
drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
On Broadwell, any PIPE_CONTROL with the State Cache Invalidate bit set
From: Zhipeng Gong zhipeng.g...@intel.com
This will let userland only try to use the new ring
when the appropriate kernel is present
Signed-off-by: Zhipeng Gong zhipeng.g...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
Reviewed--by: Rodrigo Vivi rodrigo.v...@intel.com
---
From: Chris Wilson ch...@chris-wilson.co.uk
Sometimes we wish to tweak how an individual context behaves. Since we
always create a context for every filp, this means that individual
processes can fine tune their behaviour even if they do not explicitly
create a context.
The first example
To be used for a Workaroud. Similar to:
commit 884ceacee308f0e4616d0c933518af2639f7b1d8
Author: Kenneth Graunke kenn...@whitecape.org
Date: Sat Jun 28 02:04:20 2014 +0300
drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
This round is from discussions finished Nov 07 to Nov 21, plus the old ones
still pending reviews.
Here goes the update list in order for better reviewers assignment:
From: Chris Wilson ch...@chris-wilson.co.uk
This will allow us to set per-file, or even per-context, periods in the
future.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
From: Zhipeng Gong zhipeng.g...@intel.com
On Broadwell GT3 we have 2 Video Command Streamers (VCS), but userspace
has no control when using VCS1 or VCS2. This patch introduces a mechanism
to avoid the default ping-pong mode and use one specific ring through
execution flag.
v2: fix whitespace
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
From: Ville Syrjälä ville.syrj...@linux.intel.com
pipe_crc-entries[] is an array so allocate with kcalloc() instead of
kzalloc().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Ville Syrjälä ville.syrj...@linux.intel.com
A few CHV pipe C/port D specific things that slipped through the craps,
and also few generic fixes/cleanups to the CRC code.
Ville Syrjälä (5):
drm/i915: Engage the DP scramble reset for pipe C on CHV
drm/i915: Fix CRC support for DP port D
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add the missing CRC control register value for DP port D on CHV.
Untested as I don't have a CHV machine with DP on port D.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
1 file
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
A few of the sprite-related function names in i915 are very similar
(e.g., intel_enable_planes() vs intel_crtc_enable_planes()) and don't
make it clear whether they only operate on sprite planes, or whether
they also apply to all universal plane types. Rename a few functions to
be more consistent
This series transitions the i915 driver over to using that atomic plane helpers
to handle plane updates and disables. The previous display plane refactoring
series brought us in line with the plane helper design, so the main work here
is separating work that can sleep out of the main commit
Move the vblank evasion up from the low-level, hw-specific
update_plane() handlers to the general plane commit operation.
Everything inside commit should now be non-sleeping, so this brings us
closer to how vblank evasion will behave once we move over to atomic.
v2:
- Restore lost
Now that we have hooks to enable the atomic plane helpers, we can use
the plane helpers for our .update_plane() and .disable_plane()
entrypoints.
Note that we still need to make a few small behavioral changes to the
driver entrypoints here as we make the transition, due to differences
between how
Add the new driver entrypoints that will be called by the atomic plane
helpers.
This patch does not actually switch over to the new plane helpers yet,
so there should be no functional change here. Also note that although
plane programming was already split into check/prepare/commit steps,
some
The userspace-requested plane coordinates are now stored in
plane-state.base (and the i915-adjusted values are stored in
plane-state), so we no longer use the coordinate fields in intel_plane
or the orig_{src,dst} fields in intel_plane_state. Drop them.
Reviewed-by: Bob Paauwe
Once we integrate our work into the atomic pipeline, plane commit
operations will need to happen with interrupts disabled, due to vblank
evasion. Our commit functions today include sleepable work, so those
operations need to be split out and run either before or after the
atomic register
From: Ville Syrjälä ville.syrj...@linux.intel.com
Set the pipe_crc-entries pointer while holding the relevant spinlock.
Doesn't matter too much since a spurious pipe crc interrupt would then
just update one entry but later that entry would get cleared when head
and tail are both set to 0. But
From: Ville Syrjälä ville.syrj...@linux.intel.com
To get stable CRCs from the DP CRC source we need to reset the
scrambler for each frame. Enable the reset feature when grabbing
CRCs for pipe C on CHV. Pipes A and B were already covered due
sharing the code with VLV.
We can safely extend
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently i915_pipe_crc_read() will drop pipe_crc-lock for the entire
duration of the copy_to_user() loop, which means it'll access
pipe_crc-entries without any protection. If another thread sneaks in
and frees pipe_crc-entries the code will oops.
drm_plane_helper_check_update() currently uses crtc before testing whether
we're disabling the plane (fb == NULL). Move the fb test before the first crtc
usage so that crtc == NULL doesn't have to be handled by the caller.
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
The valid pipe/connector combo check was lost in
commit 57259d714d3fe1170cf931af72648219856a9918
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Mon Nov 24 16:08:32 2014 +0100
lib/igt_debugfs: Don't setup crc in _new
Restore it to
On 8 December 2014 at 22:55, Daniel Vetter daniel.vet...@ffwll.ch wrote:
When we unplug a dp mst branch we unreference the entire tree from
the root towards the leaves. Which is ok, since that's the way the
pointers and so also the refcounts go.
But when we drop the reference we must
On Tue, Dec 09, 2014 at 06:04:33PM +0200, Mika Kuoppala wrote:
This is a similar to 'i915_gpu_state' but more dangerous
as it doesn't try to lock nor idle the gpu before grabbing
the state. But the obvious advantages are that one can
inspect the current running gpu state and also get a state
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Tue, Dec 9, 2014 at 6:51 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 11 Nov 2014 12:30:47 -0800
Jesse Barnes jbar...@virtuousgeek.org wrote:
This should allow us to avoid mode sets for some panel fitter config
changes.
v2:
- fixup pfit comment (Ander)
v3:
- fixup pfit
On Tue, 9 Dec 2014 22:16:33 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Dec 9, 2014 at 6:51 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 11 Nov 2014 12:30:47 -0800
Jesse Barnes jbar...@virtuousgeek.org wrote:
This should allow us to avoid mode sets for some panel
On 12/09/2014 05:21 AM, Daniel Vetter wrote:
On Mon, Dec 08, 2014 at 02:33:49PM -0800, michael.h.ngu...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
By adding a new exec_entry flag, we cleanly mark the shadow objects
as purgeable after they are on the active list.
v2:
-
On 12/09/2014 05:22 AM, Daniel Vetter wrote:
On Mon, Dec 08, 2014 at 02:33:50PM -0800, michael.h.ngu...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Move it to a separate function since the main do_execbuffer function
already has so much going on.
v2:
- Move pin/unpin calls
1 - 100 of 124 matches
Mail list logo
