At present, dma_buf_export() takes a series of parameters, which
makes it difficult to add any new parameters for exporters, if required.
Make it simpler by moving all these parameters into a struct, and pass
the struct * as parameter to dma_buf_export().
While at it, unite dma_buf_export_named()
Reviewed-by: Ander Conselvan de Oliveira
On 01/23/2015 02:51 AM, Matt Roper wrote:
Even though we only support atomic plane updates at the moment, we still
need to add an .atomic_get_property() entrypoint for connectors before
we allow the driver to flip on the DRIVER_ATOMIC bit. As soon as th
Reviewed-by: Ander Conselvan de Oliveira
On 01/23/2015 02:50 AM, Matt Roper wrote:
We want to enable/test plane updates via the atomic interface, but as
soon as we flip DRIVER_ATOMIC on, the DRM core will take some atomic
codepaths to lookup properties during drmModeGetConnector() and some of
t
Self-explanatory code is better code.
Cc: Dave Airlie
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_irq.c | 8 +---
drivers/gpu/drm/i915/intel_dp.c | 8 +---
drivers/gpu/drm/i915/intel_drv.h | 6 +++---
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drive
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5629
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 353/353
On 01/22/2015 06:58 PM, Jani Nikula wrote:
On Thu, 22 Jan 2015, Shobhit Kumar wrote:
On 01/16/2015 05:57 PM, Jani Nikula wrote:
This series ports our DSI code over to the drm_panel and
mipi_dsi_host/mipi_dsi_device. There are some rough edges towards the
end of the series, see commit message f
On 01/22/2015 06:31 PM, Jani Nikula wrote:
This seems like the right thing to do. This also gets rid of a call to
intel_dsi_pipe_to_port() which we want to remove eventually.
v2: add braces to fix else logic (Shobhit)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 10 +
We don't have full atomic modeset support yet, but the "nuclear
pageflip" subset of functionality (i.e., plane operations only) should
be ready. Allow the user to force atomic on for debug purposes, or for
fixed-purpose embedded devices that will only use atomic for plane
updates.
The term 'nucle
Even though we only support atomic plane updates at the moment, we still
need to add an .atomic_get_property() entrypoint for connectors before
we allow the driver to flip on the DRIVER_ATOMIC bit. As soon as that
bit gets set, the DRM core will start adding atomic connector properties
(in additio
We want to enable/test plane updates via the atomic interface, but as
soon as we flip DRIVER_ATOMIC on, the DRM core will take some atomic
codepaths to lookup properties during drmModeGetConnector() and some of
those codepaths unconditionally dereference connector->state
(specifically when looking
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5625
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 353/353
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5626
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 353/353
On Thu, Jan 22, 2015 at 06:38:32PM +0100, Daniel Vetter wrote:
> On Thu, Jan 22, 2015 at 5:42 PM, Ville Syrjälä
> wrote:
> >> Which is pretty much what I do - you can only access the per-crtc ACTIVE
> >> property from the atomic ioctl, the per-connector dpms property is _not_
> >> exposed through
This builds on top of the crtc->active infrastructure to implement
legacy DPMS. My choice of semantics is somewhat arbitrary, but the
entire pipe is enabled as along as one output is still enabled.
Of course it also clamps everything that's not ON to OFF.
v2: Fix spelling in one comment.
v3: Don
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5623
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 353/353
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5620
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 353/353
On Thu, Jan 22, 2015 at 5:42 PM, Ville Syrjälä
wrote:
>> Which is pretty much what I do - you can only access the per-crtc ACTIVE
>> property from the atomic ioctl, the per-connector dpms property is _not_
>> exposed through atomic. Vice-versa legacy clients wont see atomic
>> properties (and henc
On 01/22/2015 02:35 AM, Matt Roper wrote:
We don't have full atomic modeset support yet, but the "nuclear
pageflip" subset of functionality (i.e., plane operations only) should
be ready. Allow the user to force atomic on for debug purposes, or for
fixed-purpose embedded devices that will only us
Reviewed-by: Ander Conselvan de Oliveira
On 01/22/2015 02:35 AM, Matt Roper wrote:
This will exercise our atomic pipeline for legacy property updates.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 9 +
drivers/gpu/drm/i915/intel_display.c | 3 ++-
Reviewed-by: Ander Conselvan de Oliveira
On 01/22/2015 02:35 AM, Matt Roper wrote:
The atomic helpers need these to prepare a new state object when
starting a new atomic operation.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_atomic.c | 35 +++
From: Ben Widawsky
When we do dynamic page table allocations for gen8, we'll need to have
more control over how and when we map page tables, similar to gen6.
In particular, DMA mappings for page directories/tables occur at allocation
time.
This patch adds the functionality and calls it at init,
From: Ben Widawsky
This finishes off the dynamic page tables allocations, in the legacy 3
level style that already exists. Most everything has already been setup
to this point, the patch finishes off the enabling by setting the
appropriate function pointers.
v2: Update aliasing/true ppgtt alloca
From: Ben Widawsky
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
v2: Updated to use unmap_and_free_pd functions.
v3: Updated gen8_ppgtt_free after teardown logic was removed.
Signed-off-by: Ben Widawsky
Si
From: Ben Widawsky
The problem is we're going to switch to a new context, which could be
the default context. The plan was to use restore inhibit, which would be
fine, except if we are using dynamic page tables (which we will). If we
use dynamic page tables and we don't load new page tables, the
From: Ben Widawsky
Like with gen6/7, we can enable bitmap tracking with all the
preallocations to make sure things actually don't blow up.
v2: Rebased to match changes from previous patches.
v3: Without teardown logic, rely on used_pdpes and used_pdes when
freeing page tables.
Signed-off-by: Be
From: Ben Widawsky
One important part of this patch is we now write a scratch page
directory into any unused PDP descriptors. This matters for 2 reasons,
first, we're not allowed to just use 0, or an invalid pointer, and second,
we must wipe out any previous contents from the last context.
The l
From: Ben Widawsky
Start using gen8_for_each_pde macro to allocate page tables.
v2: teardown_va_range references removed.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 46 +++--
1 file changed, 29 inse
From: Ben Widawsky
This patch continues on the idea from the previous patch. From here on,
in the steady state, PDEs are all pointing to the scratch page table (as
recommended in the spec). When an object is allocated in the VA range,
the code will determine if we need to allocate a page for the
From: Ben Widawsky
In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have
one, but it resembles having one). The #define was confusing as is, and
using "PDPE" is a much better description.
sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/gpu/drm/i915/*.[ch]
It also matches
This patchset continues addressing the comments from v2. In particular, it no
longer teardowns pagetables dynamically, now happening until the vm is free.
For GEN8, it has also been extended to work in logical ring submission (lrc)
mode, as it will be the preferred mode of operation.
I also tried
From: Ben Widawsky
When we move to dynamic page allocation, keeping page_directory and pagetabs as
separate structures will help to break actions into simpler tasks.
To help transition the code nicely there is some wasted space in gen6/7.
This will be ameliorated shortly.
Following the x86 page
From: Ben Widawsky
Move the remaining members over to the new page table structures.
This can be squashed with the previous commit if desire. The reasoning
is the same as that patch. I simply felt it is easier to review if split.
v2: In lrc: s/ppgtt->pd_dma_addr[i]/ppgtt->pdp.page_directory[i].
From: Ben Widawsky
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_trace.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index 6058a01..f004d3d 100644
--
From: Ben Widawsky
Start using gen8_for_each_pdpe macro to allocate the page directories.
v2: Rebased after s/free_pt_*/unmap_and_free_pt/ change.
v3: Rebased after teardown va range logic was removed.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i
From: Ben Widawsky
As we move toward dynamic page table allocation, it becomes much easier
to manage our data structures if break do things less coarsely by
breaking up all of our actions into individual tasks. This makes the
code easier to write, read, and verify.
Aside from the dissection of
From: Ben Widawsky
We have some fanciness coming up. This patch just breaks out the logic
of context switch skip, pd load pre, and pd load post.
v2: Use new functions to replace the logic right away (Daniel)
Cc: Daniel Vetter
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
The next patch in the series will require it for alloc_pt_single.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/
From: Ben Widawsky
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs within a
page table are currently being used for objects. The next patch wi
From: Ben Widawsky
Now that we don't need to trace num_pd_pages, we may as well kill all
need for the PPGTT structure in the alloc_page_directorys. This is very useful
for when we move to 48b addressing, and the PDP isn't the root of the
page table structure.
The param is replaced with drm_devic
From: Ben Widawsky
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
v2: Match trace_i915_va_teardown params
v3: Multiple
From: Ben Widawsky
The current code will both potentially print a WARN, and setup part of
the PPGTT structure. Neither of these harm the current code, it is
simply for clarity, and to perhaps prevent later bugs, or weird
debug messages.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
Traces for page directories and tables allocation and map.
v2: Removed references to teardown.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++
drivers/gpu/drm/i915/i915_trace.h | 99
From: Ben Widawsky
This patch was formerly known as, "Force pd restore when PDEs change,
gen6-7." I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new object is mapped
into the current address space. The GPU does not snoop the new mappi
Logic ring contexts need to know the PDPs when they are populated. With
dynamic page table allocations, these PDPs may not exist yet.
Check if PDPs have been allocated and use the scratch page if they do
not exist yet.
Before submission, update the PDPs in the logic ring context as PDPs
have been
From: Ben Widawsky
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9d998ec..8f76990 100644
---
On 01/22/2015 02:35 AM, Matt Roper wrote:
Even though we only support atomic plane updates at the moment, we still
need to add an .atomic_get_property() entrypoint for connectors before
we allow the driver to flip on the DRIVER_ATOMIC bit. As soon as that
bit gets set, the DRM core will start ad
From: Vandana Kannan
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4
From: Vandana Kannan
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will b
On Thu, Jan 22, 2015 at 05:15:26PM +0100, Daniel Vetter wrote:
> On Thu, Jan 22, 2015 at 05:56:54PM +0200, Ville Syrjälä wrote:
> > On Thu, Jan 22, 2015 at 04:36:21PM +0100, Daniel Vetter wrote:
> > > This is the infrastructure for DPMS ported to the atomic world.
> > > Fundamental changes compare
On Thu, Jan 22, 2015 at 05:56:54PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 22, 2015 at 04:36:21PM +0100, Daniel Vetter wrote:
> > This is the infrastructure for DPMS ported to the atomic world.
> > Fundamental changes compare to legacy DPMS are:
> >
> > - No more per-connector dpms state, instea
On Thu, Jan 22, 2015 at 03:54:29PM +, Tvrtko Ursulin wrote:
>
> On 01/22/2015 03:47 PM, Damien Lespiau wrote:
> >On Thu, Jan 22, 2015 at 03:28:04PM +, Tvrtko Ursulin wrote:
> >>
> >>On 01/22/2015 02:04 PM, Damien Lespiau wrote:
> >>>On Thu, Jan 22, 2015 at 01:41:48PM +, Tvrtko Ursulin
On 01/22/2015 02:35 AM, Matt Roper wrote:
We want to enable/test plane updates via the atomic interface, but as
soon as we flip DRIVER_ATOMIC on, the DRM core will take some atomic
codepaths to lookup properties during drmModeGetConnector() and some of
those codepaths unconditionally dereference
On Thu, Jan 22, 2015 at 04:36:21PM +0100, Daniel Vetter wrote:
> This is the infrastructure for DPMS ported to the atomic world.
> Fundamental changes compare to legacy DPMS are:
>
> - No more per-connector dpms state, instead there's just one per each
> display pipeline. So if you clone either
On 01/22/2015 03:47 PM, Damien Lespiau wrote:
On Thu, Jan 22, 2015 at 03:28:04PM +, Tvrtko Ursulin wrote:
On 01/22/2015 02:04 PM, Damien Lespiau wrote:
On Thu, Jan 22, 2015 at 01:41:48PM +, Tvrtko Ursulin wrote:
@@ -718,7 +718,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXE
On Thu, Jan 22, 2015 at 03:28:04PM +, Tvrtko Ursulin wrote:
>
> On 01/22/2015 02:04 PM, Damien Lespiau wrote:
> >On Thu, Jan 22, 2015 at 01:41:48PM +, Tvrtko Ursulin wrote:
> @@ -718,7 +718,7 @@ struct drm_i915_gem_execbuffer2 {
> #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /*
For historical reasons going all the way back to how the Xrandr code
was implemented the semantics of the callbacks used to enable/disable
crtcs and encoders are ... interesting.
But with atomic helpers all that complexity has been binned, with only
a well-defined on/off action left. Unfortunately
Cursor plane updates have historically been fully async and mutliple
updates batched together for the next vsync. And userspace relies upon
that. Since implementing a full queue of async atomic updates is a bit
of work lets just recover the cursor specific behaviour with a hint
flag and some hacks
With the combination of ->enable and ->active it's a bit complicated
to follow what exactly is going on sometimes within a full modeset.
Add debug output to make this all traceable.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic_helper.c | 22 +-
1 file changed,
This builds on top of the crtc->active infrastructure to implement
legacy DPMS. My choice of semantics is somewhat arbitrary, but the
entire pipe is enabled as along as one output is still enabled.
Of course it also clamps everything that's not ON to OFF.
v2: Fix spelling in one comment.
Signed-
This is the infrastructure for DPMS ported to the atomic world.
Fundamental changes compare to legacy DPMS are:
- No more per-connector dpms state, instead there's just one per each
display pipeline. So if you clone either you have to unclone first
if you only want to switch off one screen, or
On 01/22/2015 02:04 PM, Damien Lespiau wrote:
On Thu, Jan 22, 2015 at 01:41:48PM +, Tvrtko Ursulin wrote:
@@ -718,7 +718,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
__u64 flags;
__u64 rsvd1; /* now used for contex
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5619
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 353/353
On Thu, Jan 22, 2015 at 01:41:48PM +, Tvrtko Ursulin wrote:
> >>@@ -718,7 +718,7 @@ struct drm_i915_gem_execbuffer2 {
> >> #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
> >>__u64 flags;
> >>__u64 rsvd1; /* now used for context info */
> >>- __u64 rsvd2;
> >>+ __u
On 01/22/2015 01:49 PM, Chris Wilson wrote:
On Thu, Jan 22, 2015 at 01:41:48PM +, Tvrtko Ursulin wrote:
On 01/22/2015 11:42 AM, Chris Wilson wrote:
+ if (args->flags & I915_EXEC_FENCE_OUT) {
+ ret = i915_create_sync_fence_ring(ring, ctx,
+
On Thu, Jan 22, 2015 at 01:41:48PM +, Tvrtko Ursulin wrote:
>
> On 01/22/2015 11:42 AM, Chris Wilson wrote:
> >>+ if (args->flags & I915_EXEC_FENCE_OUT) {
> >>+ ret = i915_create_sync_fence_ring(ring, ctx,
> >>+ &sync_fence, &fence_fd);
>
On 01/22/2015 11:42 AM, Chris Wilson wrote:
On Thu, Jan 22, 2015 at 11:15:40AM +, Tvrtko Ursulin wrote:
From: Jesse Barnes
Add Android native sync support with fences exported as file descriptors via
the execbuf ioctl (rsvd2 field is used).
This is a continuation of Jesse Barnes's previo
This looked like an odd regression from
commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b
Author: Chris Wilson
Date: Thu Jun 12 10:28:55 2014 +0100
drm/i915: Restrict GPU boost to the RCS engine
but in reality it undercovered a much older coherency bug. The issue that
boosting the GPU frequ
On Thu, Jan 22, 2015 at 02:24:18PM +0100, Daniel Vetter wrote:
> On Thu, Jan 22, 2015 at 2:13 PM, Chris Wilson
> wrote:
> > This looked like an odd regression from
> >
> > commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b
> > Author: Chris Wilson
> > Date: Thu Jun 12 10:28:55 2014 +0100
> >
> >
On Thu, 22 Jan 2015, Shobhit Kumar wrote:
> On 01/16/2015 05:57 PM, Jani Nikula wrote:
>> This series ports our DSI code over to the drm_panel and
>> mipi_dsi_host/mipi_dsi_device. There are some rough edges towards the
>> end of the series, see commit message for patch 8 for details.
>>
>> Patche
On Thu, Jan 22, 2015 at 2:13 PM, Chris Wilson wrote:
> This looked like an odd regression from
>
> commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b
> Author: Chris Wilson
> Date: Thu Jun 12 10:28:55 2014 +0100
>
> drm/i915: Restrict GPU boost to the RCS engine
>
> but in reality it undercove
On Thu, Jan 22, 2015 at 01:21:14PM +, Chris Wilson wrote:
Nothing to see here; please move along.
Just a git-send-email going astray.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx mailing list
Intel-gfx@lists.freedeskto
On Thu, 22 Jan 2015, Shobhit Kumar wrote:
> On 01/16/2015 05:57 PM, Jani Nikula wrote:
>> Remove all the trivial and/or dummy callbacks from intel dsi device
>> ops. Merge send_otp_cmds into panel_reset as they're called back to
>> back.
>>
>> This will be helpful for switching to use drm_panel fo
---
tests/gem_concurrent_blit.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/gem_concurrent_blit.c b/tests/gem_concurrent_blit.c
index 48ee48a..8e0a851 100644
--- a/tests/gem_concurrent_blit.c
+++ b/tests/gem_concurrent_blit.c
@@ -90,14 +90,14 @@ prw_set
The choice is to either move the igt_require from the buffer allocation
(and allow the allocation to fail) inside the igt_fixture, or move the
buffer allocation to the subtest. Moving it to the subtest has the
advantage of ensuring that every test has the same initial state (no
chance of leaking st
This looked like an odd regression from
commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b
Author: Chris Wilson
Date: Thu Jun 12 10:28:55 2014 +0100
drm/i915: Restrict GPU boost to the RCS engine
but in reality it undercovered a much older coherency bug. The issue that
boosting the GPU frequ
This seems like the right thing to do. This also gets rid of a call to
intel_dsi_pipe_to_port() which we want to remove eventually.
v2: add braces to fix else logic (Shobhit)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 10 +-
1 file changed, 5 insertions(+), 5 dele
On Thu, 22 Jan 2015, Shobhit Kumar wrote:
> On 01/16/2015 05:57 PM, Jani Nikula wrote:
>> This seems like the right thing to do. This also gets rid of a call to
>> intel_dsi_pipe_to_port() which we want to remove eventually.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_
On 01/22/2015 02:35 AM, Matt Roper wrote:
Add the top-level atomic entrypoints for check/commit. These won't get
called yet; we still need to either enable the atomic ioctl or switch to
using the non-transitional atomic helpers for legacy operations.
v2:
- Use plane->pipe rather than plane->p
On 01/16/2015 05:57 PM, Jani Nikula wrote:
This series ports our DSI code over to the drm_panel and
mipi_dsi_host/mipi_dsi_device. There are some rough edges towards the
end of the series, see commit message for patch 8 for details.
Patches 1-6 are prep work, fairly independent
While I continu
On Thu, Jan 22, 2015 at 11:15:40AM +, Tvrtko Ursulin wrote:
> From: Jesse Barnes
>
> Add Android native sync support with fences exported as file descriptors via
> the execbuf ioctl (rsvd2 field is used).
>
> This is a continuation of Jesse Barnes's previous work, squashed to arrive at
> the
On Thursday 22 January 2015 12:18 PM, Daniel Vetter wrote:
On Tue, Jan 13, 2015 at 05:27:01PM -0800, Rodrigo Vivi wrote:
I believe we could start this re-org by moving it out to intel_drrs.c
renaming functions and adding entry docbook entry.
But anyway this patch is right and doesn't seem to c
On 01/16/2015 05:57 PM, Jani Nikula wrote:
Const is good for you. No functional changes.
Signed-off-by: Jani Nikula
Reviewed-By: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu
On 01/16/2015 05:57 PM, Jani Nikula wrote:
Remove all the trivial and/or dummy callbacks from intel dsi device
ops. Merge send_otp_cmds into panel_reset as they're called back to
back.
This will be helpful for switching to use drm_panel for the
callbacks. If we ever need the additional callbacks
From: Jesse Barnes
Add Android native sync support with fences exported as file descriptors via
the execbuf ioctl (rsvd2 field is used).
This is a continuation of Jesse Barnes's previous work, squashed to arrive at
the final destination, cleaned up, with some fixes and preliminary light
testing.
Reviewed-by: Ander Conselvan de Oliveira
On 01/22/2015 02:35 AM, Matt Roper wrote:
When we flip on the DRIVER_ATOMIC bit, the DRM core will start calling
this entrypoint to set and lookup driver-specific plane property values,
rather than maintaining a shadow copy in object->properties.
Note t
On Wednesday 21 January 2015 08:33 PM, Rodrigo Vivi wrote:
On Wed, 2015-01-21 at 17:43 +0530, Ramalingam C wrote:
Hi
On Friday 16 January 2015 04:41 AM, Rodrigo Vivi wrote:
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
wrote:
From: Durgadoss R
This patch enables eDP DRRS for CHV by add
On 01/16/2015 05:57 PM, Jani Nikula wrote:
Add port parameter to wait_for_dsi_fifo_empty, and call it for each dsi
port.
We can now remove the transitional intel_dsi_pipe_to_port() function.
Signed-off-by: Jani Nikula
Reviewed-By: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 17
Reviewed-by: Ander Conselvan de Oliveira
On 01/22/2015 02:35 AM, Matt Roper wrote:
> Runtime state that can be manipulated via properties should now go in
> intel_plane_state/drm_plane_state so that it can be tracked as part of
> an atomic transaction.
>
> We add a new 'intel_create_plane_state'
On 01/16/2015 05:57 PM, Jani Nikula wrote:
This seems like the right thing to do. This also gets rid of a call to
intel_dsi_pipe_to_port() which we want to remove eventually.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deleti
From: Vandana Kannan
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will b
From: Vandana Kannan
Calling enable/disable DRRS when enable/disable DDI are called.
These functions are responsible for setup of drrs data (in enable) and
reset of drrs (in disable).
has_drrs is true when downclock_mode is found and SEAMLESS_DRRS is set in
the VBT. A check has been added for has
From: Vandana Kannan
Add DRRS work function to trigger a switch to low refresh rate,
when no activity is detected on screen till 1 sec duration.
v2: [By Ram]: drrs.dp also protected with drrs.mutex and worker function
is renamed to intel_edp_drrs_downclock_work [Rodrigo]
Signed-off-by: Vandana
Mainly taking care of some register offsets, otherwise things are similar to
hsw. Also, programming ddi aux to use hardcoded values for psr data select.
v2: introduce EDP_PSR_AUX_BASE macro (Chris)
v3: Moving to HW tracking for SKL+ platforms, so activating source psr during
psr_enabling and then
On Thu, Jan 22, 2015 at 08:04:33AM +0100, Daniel Vetter wrote:
[...]
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
[...]
> @@ -1391,6 +1395,12 @@ static int drm_mode_create_standard_properties(struct
> drm_device *dev)
> return -ENOMEM;
> dev->mode_conf
Thrown up my brain's parser for a moment ;-)
Signed-off-by: Daniel Vetter
---
tests/gem_concurrent_blit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_concurrent_blit.c b/tests/gem_concurrent_blit.c
index beb96757eeb7..726198012c14 100644
--- a/tests/gem_concurre
On 01/16/2015 05:57 PM, Jani Nikula wrote:
wait_for_dsi_fifo_empty can be static in intel_dsi.c. No functional
changes.
Signed-off-by: Jani Nikula
Reviewed-By: Shobhit Kumar
---
drivers/gpu/drm/i915/intel_dsi.c | 16
drivers/gpu/drm/i915/intel_dsi_cmd.c | 16 ---
On Thu, Jan 22, 2015 at 09:49:54AM +0100, Daniel Vetter wrote:
> Our tooling doesn't cope with () in the testnames (piglit becomes all
> confused apparently) and the naming convention says to use "blt" and
> "render".
Time to fix the tooling. The next one I will call "; rm -rf /"
-Chris
--
Chris
On Wed, Jan 21, 2015 at 08:47:38AM +0100, Daniel Vetter wrote:
[...]
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
[...]
> @@ -3738,6 +3738,24 @@ struct drm_property *drm_property_create_range(struct
> drm_device *dev, int flags
> }
> EXPORT_SYMBOL(drm_property_create_ra
Our tooling doesn't cope with () in the testnames (piglit becomes all
confused apparently) and the naming convention says to use "blt" and
"render".
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88220
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88349
Signed-off-by: Daniel Vette
On 01/16/2015 05:57 PM, Jani Nikula wrote:
Instead of having the for each dsi port loop within dpi_send_cmd(), add
a port parameter to the function and call it for each port instead.
This is a rewrite of
commit 4510cd779e5897eeb8691aecbd639bb62ec27d55
Author: Gaurav K Singh
Date: Thu Dec 4 1
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