On Mon, Feb 23, 2015 at 03:56:00PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Display watermarks need different programming for different tiling
modes.
Set the relevant flag so this happens during the plane commit and
add relevant data into a structure made
On Tue, Feb 24, 2015 at 03:22:54PM +, Damien Lespiau wrote:
On Wed, Feb 18, 2015 at 07:31:11PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
On SKL, the frequency programmed in RPNSWREQ (A008) register
has to be in units of 16.66 MHZ. So updated the
On Mon, Feb 23, 2015 at 03:57:55PM +, Tvrtko Ursulin wrote:
From: Damien Lespiau damien.lesp...@intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
testdisplay is a bit an awkward test, mostly used by QA for manual
testing. I think we also need some basic kms_setmode subtest
On Mon, Feb 23, 2015 at 03:57:43PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Starting with Skylake the display engine can scan out Y tiled objects. (Both
legacy Y tiled, and the new Yf format.)
This series takes the original work by Damien Lespiau and
Required to run on any recent, freon-based and X11-free ChromeOS release.
Signed-off-by: Marc Herbert marc.herb...@intel.com
---
Changes from v1:
- igt_debug() instead of igt_warn()
- return KD_GRAPHICS instead of -1UL
- print previous mode in debug statements. Among others this help a tiny
On Tue, Feb 24, 2015 at 04:22:33PM +, Michel Thierry wrote:
This patchset addresses comments from v5 by Mika, specially some rename
changes
touched several patches.
For GEN8, it has also been extended to work in logical ring submission (lrc)
mode, as it will be the preferred mode of
On Tue, Feb 24, 2015 at 01:37:54PM -0800, Rodrigo Vivi wrote:
This return 0 without setting atomic bits on fb == crtc-cursor-fb
where causing frontbuffer false positives.
According to Daniel:
The original regression seems to have been introduced in the original
check/commit split:
On Tue, Feb 24, 2015 at 10:44:19AM -0800, Matt Roper wrote:
On Tue, Feb 24, 2015 at 10:36:32AM -0800, Rodrigo Vivi wrote:
Atomic bits needs to be set when cursor check function is returning 0
and intel_crtc is active.
v2: When putting more debug prints I notice the solution was simpler
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
Hi,
Am Mi den 18. Feb 2015 um 16:39 schrieb Jani Nikula:
On Tue, 17 Feb 2015, Klaus Ethgen klaus+l...@ethgen.de wrote:
After solving the conflicts, I applied the revert (see attachment) to
v3.18.7. I think it should also apply to the current
On Sun, Feb 22, 2015 at 11:38:36AM +0100, Daniel Vetter wrote:
In
daniel@phenom:~/linux/src$ git show ccfc08655
commit ccfc08655d5fd5076828f45fb09194c070f2f63a
Author: Rob Clark robdcl...@gmail.com
Date: Thu Dec 18 16:01:48 2014 -0500
drm: tweak getconnector locking
We need to
Imre Deak imre.d...@intel.com writes:
The poweroff handlers undo the actions of the thaw handlers. As the
original commit stated saving the registers is not needed there, but
it's also not a big overhead and there should be no problem doing it. We
are planning to optimize the hibernation
On Mon, Feb 23, 2015 at 03:56:01PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
By this patch all underlying bits have been implemented and this
patch actually enables the feature.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
This return 0 without setting atomic bits on fb == crtc-cursor-fb
where causing frontbuffer false positives.
According to Daniel:
The original regression seems to have been introduced in the original
check/commit split:
commit 757f9a3e5b8a812af0c213099a5b31cb423f4d3c
Author: Gustavo Padovan
Hello,
My Lenovo Thinkpad X301 has failed to power off after saving the
hibernation image ever since v3.19-rc1. This is a regression since
v3.18. The regression is still present i v4.0-rc1.
The symptoms are: Hibernation proceeds as usual, writing a complete
image. But instead of powering off
Atm, it's possible that the interrupt handler is called when the device
is in D3 or some other low-power state. It can be due to another device
that is still in D0 state and shares the interrupt line with i915, or on
some platforms there could be spurious interrupts even without sharing
the
On Tue, Feb 24, 2015 at 12:58:19AM +0100, Daniel Vetter wrote:
On Thu, Feb 19, 2015 at 04:41:12PM +, Chris Wilson wrote:
On Thu, Feb 19, 2015 at 06:18:55PM +0200, Mika Kuoppala wrote:
There are multiple players interested in the ring-request_list
state. Request submission can happen
On 23 February 2015 at 23:49, Daniel Vetter dan...@ffwll.ch wrote:
What's the benifit here? Would be nice to add that to the commit message
with a short sentence. Series lgtm otherwise, imo you could push it as-is.
It is partly as preparation for the next patch and partly just a
simplification
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Monday, February 23, 2015 11:28 PM
To: Gordon, David S
Cc: Daniel, Thomas; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Shift driver's HWSP usage out
On Mon, Feb 23, 2015 at 03:15:58PM +0200, Jani Nikula wrote:
On Mon, 16 Feb 2015, Damien Lespiau damien.lesp...@intel.com wrote:
On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote:
skylake_update_primary_plane() did not handle all pixel formats returned
by skl_format_to_fourcc().
On Tue, Feb 24, 2015 at 11:39:08AM +0100, Daniel Vetter wrote:
On Tue, Feb 24, 2015 at 08:31:18AM +, Chris Wilson wrote:
On Tue, Feb 24, 2015 at 12:58:19AM +0100, Daniel Vetter wrote:
On Thu, Feb 19, 2015 at 04:41:12PM +, Chris Wilson wrote:
On Thu, Feb 19, 2015 at 06:18:55PM
From: Ben Widawsky benjamin.widaw...@intel.com
When we move to dynamic page allocation, keeping page_directory and pagetabs as
separate structures will help to break actions into simpler tasks.
To help transition the code nicely there is some wasted space in gen6/7.
This will be ameliorated
On Tue, Feb 24, 2015 at 11:42:20AM +0100, Daniel Vetter wrote:
On Tue, Feb 24, 2015 at 09:29:15AM +, Chris Wilson wrote:
On Tue, Feb 24, 2015 at 11:14:30AM +0200, Imre Deak wrote:
Atm, it's possible that the interrupt handler is called when the device
is in D3 or some other low-power
Chris Wilson ch...@chris-wilson.co.uk writes:
On Tue, Feb 24, 2015 at 11:39:08AM +0100, Daniel Vetter wrote:
On Tue, Feb 24, 2015 at 08:31:18AM +, Chris Wilson wrote:
On Tue, Feb 24, 2015 at 12:58:19AM +0100, Daniel Vetter wrote:
On Thu, Feb 19, 2015 at 04:41:12PM +, Chris Wilson
On Wed, Feb 18, 2015 at 07:31:11PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
On SKL, the frequency programmed in RPNSWREQ (A008) register
has to be in units of 16.66 MHZ. So updated the gen6_set_rps
function, as per this change.
Signed-off-by: Akash Goel
On Tue, 24 Feb 2015, Imre Deak imre.d...@intel.com wrote:
Atm, it's possible that the interrupt handler is called when the device
is in D3 or some other low-power state. It can be due to another device
that is still in D0 state and shares the interrupt line with i915, or on
some platforms
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
john.c.harri...@intel.com
Sent: Thursday, February 19, 2015 5:17 PM
To: Intel-GFX@Lists.FreeDesktop.Org
Subject: [Intel-gfx] [PATCH 17/53] drm/i915: Split i915_ppgtt_init_hw() in
half -
On Tue, 10 Feb 2015, Jani Nikula jani.nik...@intel.com wrote:
On Mon, 09 Feb 2015, Daniel Vetter daniel.vet...@ffwll.ch wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
This (partially) reverts
commit 5537252b6b6d71fb1a8ed7395a8e5babf91953fd
Author: Chris Wilson ch...@chris-wilson.co.uk
On Thu, 12 Feb 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Feb 12, 2015 at 07:53:18AM +, Chris Wilson wrote:
When we walk the list of vma, or even for protecting against concurrent
framebuffer creation, we must hold the struct_mutex or else a second
thread can corrupt the list as we
Michel Thierry michel.thie...@intel.com writes:
From: Ben Widawsky benjamin.widaw...@intel.com
As we move toward dynamic page table allocation, it becomes much easier
to manage our data structures if break do things less coarsely by
breaking up all of our actions into individual tasks. This
On Thu, Feb 12, 2015 at 03:41:35PM -0800, Bob Paauwe wrote:
Add a new section with subsections to the ACPI configuration table
that mimics much of the information typically stored in the VBT/option
ROM. This allows for a way to override incorrect VBT data or to provide
the configuration if VBT
On Mon, 23 Feb 2015, Daniel, Thomas thomas.dan...@intel.com wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Nick Hoath
Sent: Thursday, February 19, 2015 4:31 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH]
From: Ben Widawsky benjamin.widaw...@intel.com
Start using gen8_for_each_pde macro to allocate page tables.
v2: teardown_va_range references removed.
v3: Rebase after s/page_tables/page_table/.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
On Wed, Feb 18, 2015 at 07:31:18PM +0530, akash.g...@intel.com wrote:
From: Akash Goel akash.g...@intel.com
Added support for SKL in the 'i915_frequency_info' debugfs function
v2: Added missing conversion to 50MHZ for reqf cagf (Damien)
Signed-off-by: Akash Goel akash.g...@intel.com
On Thu, Feb 12, 2015 at 03:41:27PM -0800, Bob Paauwe wrote:
This adds an init-time configuration framework that parses configuration
data from an ACPI property table. The table is assumed to have well
defined sub-device property tables that correspond to the various
driver components.
On Mon, Feb 23, 2015 at 03:55:56PM +, Tvrtko Ursulin wrote:
From: Damien Lespiau damien.lesp...@intel.com
Skylake is able to scannout those tiling formats. We need to allow them
in the ADDFB ioctl and tell the harware about it.
v2: Rebased for addfb2 interface. (Tvrtko Ursulin)
v3:
On ke, 2015-02-18 at 18:43 +0200, Imre Deak wrote:
On ke, 2015-02-11 at 16:46 +0200, David Weinehall wrote:
intel-gpu-tools currently has a bunch of tests for suspend,
but currently none (that I could find) for hibernate.
Attached is a rudimentary patch to add said test. It does so
by
On ti, 2015-02-24 at 15:58 +0100, Bjørn Mork wrote:
This fixes a bug where hibernation completes, but the system
fails to power off after the image has been saved.
Bisection lead to commit da2bc1b9db33 (drm/i915: add poweroff_late
handler) which added a .poweroff_late hook pointing to the
From: Ben Widawsky benjamin.widaw...@intel.com
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier to swallow. The patch also introduces the PML4, ie. the new top
level structure of the page tables.
Use 48b addresses if hw supports it and i915.enable_ppgtt=3.
Aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++-
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 6 deletions(-)
The next patch in the series will require it for alloc_pt_single.
v2: Rebased after s/page_tables/page_table/.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
From: Ben Widawsky benjamin.widaw...@intel.com
One important part of this patch is we now write a scratch page
directory into any unused PDP descriptors. This matters for 2 reasons,
first, we're not allowed to just use 0, or an invalid pointer, and second,
we must wipe out any previous contents
From: Ben Widawsky benjamin.widaw...@intel.com
Map is easy, it's the same register as the PDP descriptor 0, but it only
has one entry.
v2: PML4 update in legacy context switch is left for historic reasons,
the preferred mode of operation is with lrc context based submission.
Signed-off-by: Ben
From: Ben Widawsky benjamin.widaw...@intel.com
When we move to dynamic page allocation, keeping page_directory and pagetabs as
separate structures will help to break actions into simpler tasks.
To help transition the code nicely there is some wasted space in gen6/7.
This will be ameliorated
From: Ben Widawsky benjamin.widaw...@intel.com
This patch continues on the idea from the previous patch. From here on,
in the steady state, PDEs are all pointing to the scratch page table (as
recommended in the spec). When an object is allocated in the VA range,
the code will determine if we need
From: Ben Widawsky benjamin.widaw...@intel.com
This patch was formerly known as, Force pd restore when PDEs change,
gen6-7. I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new object is mapped
into the current address space. The GPU
From: Ben Widawsky benjamin.widaw...@intel.com
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs within a
page table are currently being used
From: Ben Widawsky benjamin.widaw...@intel.com
The problem is we're going to switch to a new context, which could be
the default context. The plan was to use restore inhibit, which would be
fine, except if we are using dynamic page tables (which we will). If we
use dynamic page tables and we
From: Ben Widawsky benjamin.widaw...@intel.com
Note that there is no gen8 ppgtt debug_dump function yet.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 ++-
From: Ben Widawsky benjamin.widaw...@intel.com
We have some fanciness coming up. This patch just breaks out the logic
of context switch skip, pd load pre, and pd load post.
v2: Use new functions to replace the logic right away (Daniel)
Cc: Daniel Vetter dan...@ffwll.ch
Signed-off-by: Ben
From: Ben Widawsky benjamin.widaw...@intel.com
Up until now, ppgtt-pdp has always been the root of our page tables.
Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs.
In preparation for 4 level page tables, we need to stop use ppgtt-pdp
directly unless we know it's what we want. The
From: Ben Widawsky benjamin.widaw...@intel.com
The page directory freer is left here for now as it's still useful given
that GEN8 still preallocates. Once the allocation functions are broken
up into more discrete chunks, we'll follow suit and destroy this
leftover piece.
v2: Match
From: Ben Widawsky benjamin.widaw...@intel.com
These values are never quite useful for dynamic allocations of the page
tables. Getting rid of them will help prevent later confusion.
v2: Updated to use unmap_and_free_pd functions.
v3: Updated gen8_ppgtt_free after teardown logic was removed.
v4:
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
it will write to.
Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
Also add a scratch page for PML4.
This patch was inspired by
Traces for page directories and tables allocation and map.
v2: Removed references to teardown.
v3: bitmap_scnprintf has been deprecated.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++
On Tue, 24 Feb 2015 14:57:48 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Feb 12, 2015 at 03:41:35PM -0800, Bob Paauwe wrote:
Add a new section with subsections to the ACPI configuration table
that mimics much of the information typically stored in the VBT/option
ROM. This allows for
Atomic bits needs to be set when cursor check function is returning 0
and intel_crtc is active.
v2: When putting more debug prints I notice the solution was simpler
than I thought. AMS design is solid, just this return was wrong.
Sorry for the noise.
Cc: Matt Roper matthew.d.ro...@intel.com
On Mon, Feb 23, 2015 at 6:13 PM, Matt Roper matthew.d.ro...@intel.com wrote:
On Mon, Feb 23, 2015 at 05:52:24PM -0800, Rodrigo Vivi wrote:
Hi Daniel,
It seems that one check with one good commit followed by many zeroed
intel_crtc-atomic commits is again in place.
Can you elaborate on what
On Mon, Feb 23, 2015 at 03:55:59PM +, Tvrtko Ursulin wrote:
From: Damien Lespiau damien.lesp...@intel.com
v2: Rebased for addfb2 interface and consolidated a bit. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau
On Tue, 24 Feb 2015 17:17:18 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Feb 12, 2015 at 03:41:27PM -0800, Bob Paauwe wrote:
This adds an init-time configuration framework that parses configuration
data from an ACPI property table. The table is assumed to have well
defined
On Mon, Feb 23, 2015 at 03:55:57PM +, Tvrtko Ursulin wrote:
From: Damien Lespiau damien.lesp...@intel.com
We now need the bpp of the fb as Yf tiling has different tile widths
depending on it.
v2: Rebased for the new addfb2 interface. (Tvrtko Ursulin)
v3: Rebased for fb modifier
On Mon, Feb 23, 2015 at 03:55:56PM +, Tvrtko Ursulin wrote:
From: Damien Lespiau damien.lesp...@intel.com
Skylake is able to scannout those tiling formats. We need to allow them
in the ADDFB ioctl and tell the harware about it.
v2: Rebased for addfb2 interface. (Tvrtko Ursulin)
v3:
It doesn't fix.
Let's me grab some new logs...
On Tue, Feb 24, 2015 at 9:43 AM, Rodrigo Vivi rodrigo.v...@gmail.com wrote:
Hi Matt,
It probably doesn't fix because the issue is to have many commits
without a check, having many commits with intel_crtc-atomic zeroed
already.
imho cleaning it
On Tue, Feb 24, 2015 at 09:32:25AM -0800, Rodrigo Vivi wrote:
On Mon, Feb 23, 2015 at 6:13 PM, Matt Roper matthew.d.ro...@intel.com wrote:
On Mon, Feb 23, 2015 at 05:52:24PM -0800, Rodrigo Vivi wrote:
Hi Daniel,
It seems that one check with one good commit followed by many zeroed
On Mon, Feb 09, 2015 at 01:35:10PM +, Damien Lespiau wrote:
I overlooked the fact that we need to allocate a minimum 8 blocks and
that just allocating the planes depending on how much they need to fetch
from the DDB in proportion of how much memory bw is necessary for the
whole display can
On Tue, 24 Feb 2015 14:51:31 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Feb 12, 2015 at 03:41:33PM -0800, Bob Paauwe wrote:
Add ability to parse a list of workarounds from the ACPI table.
Initially, this expects all workarounds listed to be valid and
they replace the hard coded
On Mon, Feb 23, 2015 at 03:56:00PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Display watermarks need different programming for different tiling
modes.
Set the relevant flag so this happens during the plane commit and
add relevant data into a structure made
On Mon, Feb 23, 2015 at 03:56:01PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
By this patch all underlying bits have been implemented and this
patch actually enables the feature.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
Ville noticed that
On Tue, Feb 24, 2015 at 12:29:22PM -0800, Marc Herbert wrote:
Required to run on any recent, freon-based and X11-free ChromeOS release.
Signed-off-by: Marc Herbert marc.herb...@intel.com
---
Changes from v1:
- igt_debug() instead of igt_warn()
- return KD_GRAPHICS instead of -1UL
-
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5814
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Tue, 24 Feb 2015 21:52:16 +0100
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Feb 24, 2015 at 10:37:10AM -0800, Bob Paauwe wrote:
On Tue, 24 Feb 2015 14:57:48 +0100
Daniel Vetter dan...@ffwll.ch wrote:
As Jani points out we already have vbt headaches, it would be good if we
only have
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/intel_display.c between commit f37b5c2be897
(drm/i915: Align initial plane backing objects correctly) from the
drm-intel-fixes tree and commit 6bf129df6ffa (drm/i915: Use an
intermediate variable to
Based upon vbt's vswing preemph settings value select the appropriate
translations for edp.
v2: Incorporating bspec changes for vswing and preemph levels, adding edp
translation table. Removed HSW from selection 9 which is specific to skl and
correcting the returning of level2 from max pre emph
Skylake supports low voltage swing in edp 1.4. The translation table is selected
based upon the vbt entry for selecting low vswing
These patches are being pulled from -internal to -nightly.
Sonika Jindal (2):
drm/i915/skl: Support for edp low_vswing param in vbt
drm/i915/skl: Add support for
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