Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5889
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 280/280
On Wed, 04 Mar 2015, Ville Syrjälä wrote:
> On Wed, Mar 04, 2015 at 08:11:38PM +0530, Purushothaman, Vijay A wrote:
>> Minor nitpick: typo in patch title
>
> Dang. I already fixed a typo there before sending this out, but turns
> out I only managed to cchange it into a different typo :( Maybe I ne
There is one minor conflict when apply the KMD patch to latest
drm-intel-nightly branch. It should be easy to fix.
Another issue is that IMO, we should bump libdrm's version number
when increase these new APIs. Then in Beignet, we can check the
libdrm version at build time and determine whether we
v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
v3: Reading dpcd's supported link rates tables based upon edp version in the
same patch.
v4: Move version check under is_edp (Satheesh)
v5: Using le16 for rates, some naming, and removing nested if block (Ville)
v6: Corre
eDp 1.4 supports custom frequencies.
Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and
4.32 GHz along with usual LBR, HBR and HBR2 frequencies.
Read sink supported frequencies and get common frequencies from sink and
source and use these for link training.
v2: Rebased, r
From: Deepak S
We update the GT PM interrupts mask at the end of set rps. We observed even
though we are requesting a RPn or RP0, there is a chance to get a DOWN or UP
interrupts before interrupts mask. These extra interrupts are simply wasting
cpu cycles. In this patch we mask the interrupts for
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
suggested-by: Jesse Barnes
Signed-off-by:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
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Task id: 5887
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 280/280
Hi Daniel,
OpenCL language support NULL pointer, using zero as the NULL pointer is the
obvious way. That is zero will be treated as invalid address.
Then it requires drm won't allocate zero to drm buffer. And David in CC list
has help us make a patch, please see attached. The logic is only for
p
Reviewed by: Dhinakaran Pandiyan
Tested by: Dhinakaran Pandiyan
The screen update lag that was earlier seen on BSW is fixed by this patch.
From: Vivi, Rodrigo
Sent: Friday, February 27, 2015 5:26 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo; P
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
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Task id: 5886
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 280/280
On Wed, Mar 4, 2015 at 6:30 AM, Daniel Vetter wrote:
> On Tue, Mar 03, 2015 at 08:03:13PM +, Vivi, Rodrigo wrote:
>> On Tue, 2015-03-03 at 09:28 +0100, Daniel Vetter wrote:
>> > On Mon, Mar 02, 2015 at 06:35:26PM +, Vivi, Rodrigo wrote:
>> > > On Mon, 2015-03-02 at 18:59 +0100, Daniel Vett
On Tue, Mar 3, 2015 at 7:23 AM, Ramalingam C wrote:
> From: Vandana Kannan
>
> Adding a debugfs entry to determine if DRRS is supported or not
>
> V2: [By Ram]: Following details about the active crtc will be filled
> in seq-file of the debugfs
> 1. Encoder output type
> 2
On 03/04/2015 02:40 PM, Jesse Barnes wrote:
> I need this on my machine or eDP doesn't come up.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/driv
Looks enough for me...
Reviewed-by: Rodrigo Vivi
On Mon, Mar 2, 2015 at 10:41 PM, Ramalingam C wrote:
> In invalidate and flush functions of eDP DRRS, if deferred downclock
> work starts execution at a time window between acquiring the drrs
> mutex and cancellation of the deferred work
> (intel
I need this on my machine or eDP doesn't come up.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 480dd79..741a454 100644
On Wed, 2015-03-04 at 15:03 -0300, Paulo Zanoni wrote:
> 2015-03-03 21:57 GMT-03:00 Rodrigo Vivi :
> > On Fri, Feb 13, 2015 at 11:23 AM, Paulo Zanoni wrote:
> >> From: Paulo Zanoni
> >>
> >> Kill the blt/render tracking we currently have and use the frontbuffer
> >> tracking infrastructure.
> >>
On Tue, Mar 03, 2015 at 05:03:29PM +0200, Mika Kuoppala wrote:
> If the mappable size is less than what the full range
> of pdps can address, we end up setting pdps for only the
> mappable area.
>
> The logical context however needs valid pdp entries.
> Prior to commit 06fda602dbca ("drm/i915: Cre
On Wed, Mar 04, 2015 at 02:55:17PM +0200, Mika Kuoppala wrote:
> If the requested size is less than what the full range
> of pdps can address, we end up setting pdps for only the
> requested area.
>
> The logical context however needs all pdp entries to be valid.
> Prior to commit 06fda602dbca ("d
i915 was using the main atomic 'disable plane' to turn off sprite planes
during a CRTC disable. This was problematic because it modified the
plane state, preventing us from recovering the original state later.
One such case was that during a DPMS OFF followed by a DPMS ON, any
sprite planes would
We need to disable all sprite planes when disabling the CRTC. We had
been using the top-level atomic 'disable' entrypoint to accomplish this,
which was wrong. Not only can this lead to various locking issues, it
also modifies the actual plane state, making it impossible to restore
the plane prope
On Wed, Mar 04, 2015 at 06:42:53PM +0100, Thomas Meyer wrote:
> Hi,
>
> my kernel log is full with those messages:
>
> [ 262.685467] [ cut here ]
> [ 262.685481] WARNING: CPU: 0 PID: 50 at
> drivers/gpu/drm/i915/intel_display.c:9719 intel_check_page_flip+0x9a/0xe0()
> [
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Task id: 5884
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Platform Delta drm-intel-nightly Series Applied
PNV -6 278/278
On Wed, Mar 04, 2015 at 05:13:07PM +0100, Daniel Vetter wrote:
> On Wed, Mar 04, 2015 at 11:45:42AM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 03, 2015 at 06:15:12PM -0800, Matt Roper wrote:
> > > Universal planes allow us to have an active CRTC without a primary plane
> > > framebuffer bound. Dr
This fixes a regression from
commit 5ed0bdf21a85d78e04f89f15ccf227562177cbd9
Author: Thomas Gleixner
Date: Wed Jul 16 21:05:06 2014 +
drm: i915: Use nsec based interfaces
that made a negative timeout return immediately rather than the
previously defined behaviour of waiting indefinite
2015-03-03 21:57 GMT-03:00 Rodrigo Vivi :
> On Fri, Feb 13, 2015 at 11:23 AM, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> Kill the blt/render tracking we currently have and use the frontbuffer
>> tracking infrastructure.
>>
>> Don't enable things by default yet.
>>
>> v2: (Rodrigo) Fix small
Hi,
my kernel log is full with those messages:
[ 262.685467] [ cut here ]
[ 262.685481] WARNING: CPU: 0 PID: 50 at
drivers/gpu/drm/i915/intel_display.c:9719 intel_check_page_flip+0x9a/0xe0()
[ 262.685484] WARN_ON(!in_irq())
[ 262.685486] Modules linked in:
[ 262.6854
On Wed, Mar 4, 2015 at 5:58 PM, Conselvan De Oliveira, Ander
wrote:
>> > +
I meant this empty line between 2 closing braces ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
Intel-gfx mail
On Wed, Mar 04, 2015 at 05:26:36PM +, Tvrtko Ursulin wrote:
>
> On 03/04/2015 02:15 AM, Matt Roper wrote:
> >Universal planes allow us to have an active CRTC without a primary plane
> >framebuffer bound. Drop the test for primary->fb from
> >intel_crtc_active() since we can clearly have activ
On 03/04/2015 02:15 AM, Matt Roper wrote:
Current ILK-style watermark code assumes the primary plane and cursor
plane are always enabled. This assumption, along with the combination
of two independent commits that got merged at the same time, results in
a NULL dereference. The offending commit
On 03/04/2015 02:15 AM, Matt Roper wrote:
Universal planes allow us to have an active CRTC without a primary plane
framebuffer bound. Drop the test for primary->fb from
intel_crtc_active() since we can clearly have active CRTC's without a
framebuffer, and this check is now interfering with wate
On Wed, 2015-03-04 at 17:03 +0100, Daniel Vetter wrote:
> On Tue, Mar 03, 2015 at 03:22:15PM +0200, Ander Conselvan de Oliveira wrote:
> > Pass a crtc_state to it and find whether the pipe has an encoder of a
> > given type by looking at the drm_atomic_state the crtc_state points to.
> >
> > Note
On Wed, Mar 4, 2015 at 5:51 PM, Conselvan De Oliveira, Ander
wrote:
>> The tricky bit here is that we must have all the connectors added to the
>> drm_atomic_sate for the given crtc. Otherwise there might be no connector
>> at all and we'd return a bogus answer. drm_atomic_add_affected_connectors
On Wed, 2015-03-04 at 16:46 +0100, Daniel Vetter wrote:
> On Tue, Mar 03, 2015 at 03:22:05PM +0200, Ander Conselvan de Oliveira wrote:
> > With this in place, we can start converting pieces of the modeset code
> > to look at the connector atomic state instead of the staged config.
> >
> > Signed-o
On Tue, Mar 3, 2015 at 9:22 AM, Tvrtko Ursulin
wrote:
> From: Tvrtko Ursulin
>
> Use cases like rotation require these hooks to have some context so they
> know how to prepare and cleanup the frame buffer correctly.
>
> For i915 specifically, object backing pages need to be mapped differently
> f
On Fri, Jan 23, 2015 at 3:05 AM, Thierry Reding
wrote:
> From: Thierry Reding
>
> The current implementation is limited by the number of addresses that
> fit into an unsigned long. This causes problems on 32-bit Tegra where
> unsigned long is 32-bit but drm_mm is used to manage an IOVA space of
>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
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Task id: 5883
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Platform Delta drm-intel-nightly Series Applied
PNV -8 278/278
On Wed, Mar 04, 2015 at 02:41:16PM +, Neil Roberts wrote:
> Adds a parameter which can be used with DRM_I915_GETPARAM to query the
> GPU revision. The intention is to use this in Mesa to implement the
> WaDisableSIMD16On3SrcInstr workaround on Skylake but only for
> revision 2.
>
> Signed-off-
On 03/04/2015 12:56 AM, Chris Wilson wrote:
> On Tue, Mar 03, 2015 at 04:27:47PM -0800, Jesse Barnes wrote:
>> My "rant du jour" still is. mlock() is a good solution for some things,
>> but for the simple task of testing kernel swap out code, just running
>> that code is the most straightforward t
On Tue, Mar 03, 2015 at 06:15:12PM -0800, Matt Roper wrote:
> Universal planes allow us to have an active CRTC without a primary plane
> framebuffer bound. Drop the test for primary->fb from
> intel_crtc_active() since we can clearly have active CRTC's without a
> framebuffer, and this check is no
On Tue, Mar 03, 2015 at 04:27:47PM -0800, Jesse Barnes wrote:
> On 03/03/2015 04:06 PM, Daniel Vetter wrote:
> > On Tue, Mar 3, 2015 at 10:15 PM, Chris Wilson
> > wrote:
> >> On Tue, Mar 03, 2015 at 11:23:53AM -0800, Jesse Barnes wrote:
> >>> On 03/03/2015 09:03 AM, Daniel Vetter wrote:
> Th
On Wed, Mar 04, 2015 at 11:45:42AM +0200, Ville Syrjälä wrote:
> On Tue, Mar 03, 2015 at 06:15:12PM -0800, Matt Roper wrote:
> > Universal planes allow us to have an active CRTC without a primary plane
> > framebuffer bound. Drop the test for primary->fb from
> > intel_crtc_active() since we can c
On Tue, Mar 03, 2015 at 03:22:15PM +0200, Ander Conselvan de Oliveira wrote:
> Pass a crtc_state to it and find whether the pipe has an encoder of a
> given type by looking at the drm_atomic_state the crtc_state points to.
>
> Note that is possible to reach i9xx_get_refclk() without a proper atomi
On Tue, Mar 03, 2015 at 03:22:14PM +0200, Ander Conselvan de Oliveira wrote:
> This function is called indirectly by intel_crtc_compute_config(),
> which needs to be converted to work only with an atomic state.
>
> ---
>
> I'm not sure what are the implications of ignoring intel_crtc->active in
>
On Tue, Mar 03, 2015 at 03:22:05PM +0200, Ander Conselvan de Oliveira wrote:
> With this in place, we can start converting pieces of the modeset code
> to look at the connector atomic state instead of the staged config.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i9
On Tue, Mar 03, 2015 at 03:22:00PM +0200, Ander Conselvan de Oliveira wrote:
> In the set config modeset path, the atomic state is updated when
> changing the staged config in intel_modeset_stage_output_config(). The
> load detect code also causes a modeset, but it changes the staged config
> befor
On Tue, Mar 03, 2015 at 03:21:59PM +0200, Ander Conselvan de Oliveira wrote:
> For the atomic conversion, the mode set paths need to be changed to rely
> on an atomic state instead of using the staged config. By using an
> atomic state for the legacy code, we will be able to convert the code
> base
On Tue, Mar 03, 2015 at 03:21:58PM +0200, Ander Conselvan de Oliveira wrote:
> The pattern of getting the crtc state with drm_atomic_get_crtc_state()
> and then converting it to intel_crtc_state will repeat quite often in
> the following patches, so add a helper function to save some typing.
>
> S
On Wed, Mar 04, 2015 at 07:55:21PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:
> > From: Vidya Srinivas
> >
> > PFI credit programming is required when CD clock (related to data flow from
> > display pipeline to end display) is greater than CZ
On Tue, Mar 03, 2015 at 03:21:55PM +0200, Ander Conselvan de Oliveira wrote:
> In the path were there is no state to duplicate, the allocated crtc
> state wouldn't have the crtc backpointer initialized.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_atomic.c
On Tue, Mar 03, 2015 at 10:43:43AM +, tim.g...@intel.com wrote:
> From: Tim Gore
>
> The gem_render_tiled_blits test tends to get oom killed
> on low memory (< 4GB) Android systems. This is because the
> test tries to allocate (sysinfo.totalram * 9 / 10) in
> buffer objects and the remaining
On Tue, Mar 03, 2015 at 03:21:54PM +0200, Ander Conselvan de Oliveira wrote:
> This patch series starts to remove dependencies from the modeset code to
> enable the transition to atomic. That is achieved by using an atomic
> state struct for the legacy modeset, and changing related functiond to
> d
On Wed, Mar 04, 2015 at 05:10:02PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 04, 2015 at 08:11:38PM +0530, Purushothaman, Vijay A wrote:
> > On 2/27/2015 12:31 AM, ville.syrj...@linux.intel.com wrote:
> > > From: Ville Syrjälä
> > >
> > > The current minimum vco frequency leaves us with a gap in o
On Wed, Mar 04, 2015 at 08:11:38PM +0530, Purushothaman, Vijay A wrote:
> On 2/27/2015 12:31 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > The current minimum vco frequency leaves us with a gap in our supported
> > frequencies at 233-243 MHz. Your typical 2560x1440@60 di
On Wed, Mar 04, 2015 at 07:58:50PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > CHV has a new knob in Punit to select between some memory power savings
> > modes PM2 and PM5. We can allow the deeper PM5 when maxfi
On Wed, Mar 04, 2015 at 07:55:21PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:
> > From: Vidya Srinivas
> >
> > PFI credit programming is required when CD clock (related to data flow from
> > display pipeline to end display) is greater than CZ
On 03/04/2015 02:43 PM, Daniel Vetter wrote:
On Tue, Mar 03, 2015 at 09:59:31AM +, Tvrtko Ursulin wrote:
On 03/02/2015 06:21 PM, Daniel Vetter wrote:
On Mon, Mar 02, 2015 at 02:43:50PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
90/270 rotated scanout needs a rotated GTT view of
On 2/27/2015 12:31 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
The current minimum vco frequency leaves us with a gap in our supported
frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
allo
On Wed, Mar 04, 2015 at 07:34:50PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > CHV supposedly does maxfifo mode even with two enabled
> > (primary/sprite) planes. Lets try to support that by halving the FIFO
> >
On Tue, Mar 03, 2015 at 02:22:53PM +0530, meghanelogal wrote:
> From: meghanelogal
>
> Adding the Sprite Stress Test Feature
>
> Signed-off-by: meghanelogal
I really, really prefer if all automated and stress tests would be a part
of igt testsuite and that we'd abandon intel_sprite_on as a dem
On Tue, Mar 03, 2015 at 09:59:31AM +, Tvrtko Ursulin wrote:
>
> On 03/02/2015 06:21 PM, Daniel Vetter wrote:
> >On Mon, Mar 02, 2015 at 02:43:50PM +, Tvrtko Ursulin wrote:
> >>From: Tvrtko Ursulin
> >>
> >>90/270 rotated scanout needs a rotated GTT view of the framebuffer.
> >>
> >>This i
Adds a parameter which can be used with DRM_I915_GETPARAM to query the
GPU revision. The intention is to use this in Mesa to implement the
WaDisableSIMD16On3SrcInstr workaround on Skylake but only for
revision 2.
Signed-off-by: Neil Roberts
---
The corresponding Mesa patches are here:
http://lis
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Task id: 5880
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Platform Delta drm-intel-nightly Series Applied
PNV -2 278/278
On Tue, Mar 03, 2015 at 08:03:13PM +, Vivi, Rodrigo wrote:
> On Tue, 2015-03-03 at 09:28 +0100, Daniel Vetter wrote:
> > On Mon, Mar 02, 2015 at 06:35:26PM +, Vivi, Rodrigo wrote:
> > > On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> > > > On Fri, Feb 27, 2015 at 08:26:05PM -0500,
On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.
Signed-off-by:
On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:
From: Vidya Srinivas
PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display plane). This programming should be d
On Wednesday, March 04, 2015 09:55:55 AM Aaron Lu wrote:
> On Sun, Mar 01, 2015 at 10:41:37AM +, Chris Wilson wrote:
> > i915.ko depends upon the acpi/video.ko module and so refuses to load if
> > ACPI is disabled at runtime if for example the BIOS is broken beyond
> > repair. acpi/video provid
On 2/10/2015 6:58 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
CHV supposedly does maxfifo mode even with two enabled
(primary/sprite) planes. Lets try to support that by halving the FIFO
size for the calculations and picking the smallest calculcated
watermark from the enabled p
On Tue, Mar 03, 2015 at 06:31:03PM +0530, akash goel wrote:
> On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry
> wrote:
> > +static void gen8_map_page_directory(struct
> > i915_page_directory_pointer_entry *pdp,
> > + struct i915_page_directory_entry *pd,
> > +
On Tue, Mar 03, 2015 at 06:25:27PM +0530, akash goel wrote:
> On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
> > + pdp = ppgtt->pml4.pdps[i];
> > + if (!pdp->daddr)
> > + pci_unmap_page(hwdev, pdp->daddr, PAGE_SIZE,
> > +
If the requested size is less than what the full range
of pdps can address, we end up setting pdps for only the
requested area.
The logical context however needs all pdp entries to be valid.
Prior to commit 06fda602dbca ("drm/i915: Create page table allocators")
we have been writing pdp entries wi
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Task id: 5879
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PNV -6 278/278
On Sat, Feb 21, 2015 at 11:12:13AM +0530, Sonika Jindal wrote:
> v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
> (Ville)
>
> Signed-off-by: Sonika Jindal
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_dp.c | 28 ++--
> 1
On Sat, Feb 21, 2015 at 11:12:12AM +0530, Sonika Jindal wrote:
> eDp 1.4 supports custom frequencies.
> Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and
> 4.32 GHz along with usual LBR, HBR and HBR2 frequencies.
> Read sink supported frequencies and get common frequencie
On Tue, Mar 03, 2015 at 04:47:33PM -0800, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi
>
> On Fri, Feb 13, 2015 at 11:23 AM, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > We need this for FBC, and possibly for PSR too.
> >
> > v2: Don't only flush: invalidate too (Daniel).
> >
> > Signe
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Task id: 5878
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Platform Delta drm-intel-nightly Series Applied
PNV -9 278/278
Generalization to cover DP case
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9497eb6..abf8c7d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
On Sat, Feb 21, 2015 at 11:12:11AM +0530, Sonika Jindal wrote:
> v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
> v3: Reading dpcd's supported link rates tables based upon edp version in the
> same patch.
> v4: Move version check under is_edp (Satheesh)
> v5: Using le
On Tue, Mar 03, 2015 at 06:15:12PM -0800, Matt Roper wrote:
> Universal planes allow us to have an active CRTC without a primary plane
> framebuffer bound. Drop the test for primary->fb from
> intel_crtc_active() since we can clearly have active CRTC's without a
> framebuffer, and this check is no
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5877
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 278/278
On Tue, Mar 03, 2015 at 04:27:47PM -0800, Jesse Barnes wrote:
> My "rant du jour" still is. mlock() is a good solution for some things,
> but for the simple task of testing kernel swap out code, just running
> that code is the most straightforward thing to do, rather than trying to
> contort into
On Wed, 04 Mar 2015, Matt Roper wrote:
> Current ILK-style watermark code assumes the primary plane and cursor
> plane are always enabled. This assumption, along with the combination
> of two independent commits that got merged at the same time, results in
> a NULL dereference. The offending com
On Mon, 02 Mar 2015, Bjørn Mork wrote:
> Jani Nikula writes:
>
>> On Mon, 02 Mar 2015, Imre Deak wrote:
>>> Bjørn reported that his machine hang during hibernation and eventually
>>> bisected the problem to the following commit:
>>>
>>> commit da2bc1b9db3351addd293e5b82757efe1f77ed1d
>>> Author:
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