_crtc_state *pipe_config)
{
@@ -5812,6 +5844,8 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
pipe_config-pipe_bpp = 8*3;
}
+ intel_compute_psr_config(crtc, pipe_config);
+
if (HAS_IPS(dev))
hsw_compute_ips_config(crtc,
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6034
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6036
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 275/275
On Mon, Mar 23, 2015 at 09:41:20PM -0400, Dave Jones wrote:
On Mon, Mar 23, 2015 at 11:33:42AM -0400, Josh Boyer wrote:
I have a machine that no longer boots in a headless manner with -rc5.
It's an Celeron based NUC device. I blacklisted the i915 driver and
it boots fine, then I ran
On Mon, Mar 23, 2015 at 11:33:42AM -0400, Josh Boyer wrote:
I have a machine that no longer boots in a headless manner with -rc5.
It's an Celeron based NUC device. I blacklisted the i915 driver and
it boots fine, then I ran insmod manually and got the backtrace below.
This machine only
At Mon, 23 Mar 2015 09:25:06 +0100,
Daniel Vetter wrote:
On Mon, Mar 23, 2015 at 07:25:27AM +0100, Sedat Dilek wrote:
Hi,
I did my weekly update of the Linux RC (here: v4.0-rc5) and fell over
some warning in the drm area.
Please have a look...
Just to confirm: Both are new in
On Tue, Mar 24, 2015 at 12:10:28PM -0400, Josh Boyer wrote:
On Tue, Mar 24, 2015 at 10:46 AM, Josh Boyer jwbo...@fedoraproject.org
wrote:
On Tue, Mar 24, 2015 at 10:34 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Mar 24, 2015 at 10:22:30AM -0400, Josh Boyer wrote:
On Tue, Mar 24, 2015
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It should have been negative since it is returned with ERR_PTR().
Introduced in new code commit:
commit 50470bb011c4be278097670bea92462f4e8c8945
Author: Tvrtko Ursulin tvrtko.ursu...@intel.com
Date: Mon Mar 23 11:10:36 2015 +
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6037
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 269/269
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This tests the new EXEC_OBJECT_PAD_TO_SIZE exec_object2 flag.
It uses the fact DRM allocation policy is set as ABI and allocates
space in order. That means that we should be able to easily get
two bos mapped at adjacent GTT addresses and then test
On Thu, 19 Mar 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
The existing ABI says that scanouts are pinned into the mappable region
so that legacy clients (e.g. old Xorg or plymouthd) can write directly
into the scanout through a GTT mapping. However if the surface does not
fit into the
On Wed, Mar 25, 2015 at 4:54 AM, Daniel Vetter dan...@ffwll.ch wrote:
commit f55548b5af87ebfc586ca75748947f1c1b1a4a52
Author: Damien Lespiau damien.lesp...@intel.com
Date: Thu Feb 5 18:30:20 2015 +
drm/i915: Don't try to reference the fb in get_initial_plane_config()
From
On Wed, Mar 25, 2015 at 01:24:01PM +0100, Linus Walleij wrote:
On Tue, Mar 24, 2015 at 11:53 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Mar 24, 2015 at 11:16 AM, Linus Walleij
linus.wall...@linaro.org wrote:
So summary:
- Reusing the dynamic gpio lookup stuff would be nice, and
On Tue, Mar 24, 2015 at 10:14:01PM -0700, Matt Roper wrote:
On Fri, Mar 20, 2015 at 05:04:26PM -0700, Chandra Konduru wrote:
+static void skl_init_scalers(struct drm_device *dev, int pipe,
+ struct intel_crtc_state *crtc_state)
+{
+ int i;
+ struct intel_scaler *intel_scaler;
+
On Tue, Mar 24, 2015 at 05:21:35PM +, Tvrtko Ursulin wrote:
On 03/24/2015 02:44 PM, Jani Nikula wrote:
On Tue, 24 Mar 2015, Tvrtko Ursulin tvrtko.ursu...@linux.intel.com wrote:
On 03/24/2015 01:16 PM, Jani Nikula wrote:
On Tue, 24 Mar 2015, Tvrtko Ursulin tvrtko.ursu...@linux.intel.com
Add ERROR decodings for gen8
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/intel_error_decode.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index 035b17f..fb4a2a4 100644
---
Add decodings for FAULT_REG
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/intel_error_decode.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index fb4a2a4..553307f 100644
---
These two registers contains the 48bit fault address.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/intel_error_decode.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index
On Tue, Mar 24, 2015 at 11:53 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Mar 24, 2015 at 11:16 AM, Linus Walleij
linus.wall...@linaro.org wrote:
So summary:
- Reusing the dynamic gpio lookup stuff would be nice, and might be
interesting as a new crazy use-case (or maybe not). But not a
On Tue, Mar 24, 2015 at 06:51:43PM +, Konduru, Chandra wrote:
Please use igt_interactive_debug if you want to make a testcase useful for
visual
inspection. But igts _really_ must run fully automated, and that's possible
using
crc checksums. I.e. you need to draw reference frames
On Tue, Mar 24, 2015 at 06:39:03PM +, Mike Lothian wrote:
Hi
Since [31c946e85ce6b48ce0f25e3cdca8362e4fe8b300] drm: If available use
atomic state in getcrtc ioctl, X doesn't start correctly on my
Sandybridge machine
I've tried reverting this commit and my X session still starts up
On Wed, Feb 18, 2015 at 1:18 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
Export Panel BACKLIGHT_EN(offset 0x51) and PANEL_EN(offset 0x52) as two
additional GPIOs. Needed by display driver to enable the DSI panel on
BYT platform where the Panel EN/Disable and Backlight control are
routed
The existing ABI says that scanouts are pinned into the mappable region
so that legacy clients (e.g. old Xorg or plymouthd) can write directly
into the scanout through a GTT mapping. However if the surface does not
fit into the mappable region, we are better off just trying to fit it
anywhere and
On Tue, Mar 24, 2015 at 10:19:59AM +0200, Jani Nikula wrote:
On Mon, 23 Mar 2015, Jesse Barnes jbar...@virtuousgeek.org wrote:
Or users can just spam the log all they want.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89628
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
On Wed, Mar 25, 2015 at 10:15:26AM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It should have been negative since it is returned with ERR_PTR().
Introduced in new code commit:
commit 50470bb011c4be278097670bea92462f4e8c8945
Author: Tvrtko Ursulin
On Tue, Mar 24, 2015 at 01:01:54PM +, Michel Thierry wrote:
On 3/24/2015 12:54 PM, Mika Kuoppala wrote:
The faulting virtual address is 32bits and has been moved
to different registers. Add to error state and output upper
register first, in the same line for easy reconstruction of
the
On Wed, Mar 25, 2015 at 09:11:17AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 4:54 AM, Daniel Vetter dan...@ffwll.ch wrote:
commit f55548b5af87ebfc586ca75748947f1c1b1a4a52
Author: Damien Lespiau damien.lesp...@intel.com
Date: Thu Feb 5 18:30:20 2015 +
drm/i915:
On Wed, 2015-03-25 at 13:27 +0100, Linus Walleij wrote:
On Wed, Feb 18, 2015 at 1:18 PM, Shobhit Kumar shobhit.ku...@intel.com
wrote:
Export Panel BACKLIGHT_EN(offset 0x51) and PANEL_EN(offset 0x52) as two
additional GPIOs. Needed by display driver to enable the DSI panel on
BYT
On 03/25/2015 02:28 PM, Chris Wilson wrote:
On Wed, Mar 25, 2015 at 02:21:00PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This tests the new EXEC_OBJECT_PAD_TO_SIZE exec_object2 flag.
It uses the fact DRM allocation policy is set as ABI and allocates
space in
On Wed, Mar 25, 2015 at 02:21:00PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This tests the new EXEC_OBJECT_PAD_TO_SIZE exec_object2 flag.
It uses the fact DRM allocation policy is set as ABI and allocates
space in order.
Ssh. That's not what I meant to
The existing ABI says that scanouts are pinned into the mappable region
so that legacy clients (e.g. old Xorg or plymouthd) can write directly
into the scanout through a GTT mapping. However if the surface does not
fit into the mappable region, we are better off just trying to fit it
anywhere and
On Wed, Mar 25, 2015 at 12:44:47PM +, Chris Wilson wrote:
The existing ABI says that scanouts are pinned into the mappable region
so that legacy clients (e.g. old Xorg or plymouthd) can write directly
into the scanout through a GTT mapping. However if the surface does not
fit into the
At Wed, 25 Mar 2015 14:26:50 +0100,
Daniel Vetter wrote:
On Tue, Mar 24, 2015 at 07:09:03PM +0100, Sedat Dilek wrote:
On Mon, Mar 23, 2015 at 9:25 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Mar 23, 2015 at 07:25:27AM +0100, Sedat Dilek wrote:
Hi,
I did my weekly update of
On Wed, Mar 25, 2015 at 09:56:28AM +0100, Daniel Vetter wrote:
I've started seeing this one too as of rc5.
Along with..
Yeah we're freeing memory too early with these bugs. To get up to the
current debug state can you please cherry-pick
commit
On Tue, Mar 24, 2015 at 07:09:03PM +0100, Sedat Dilek wrote:
On Mon, Mar 23, 2015 at 9:25 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Mar 23, 2015 at 07:25:27AM +0100, Sedat Dilek wrote:
Hi,
I did my weekly update of the Linux RC (here: v4.0-rc5) and fell over
some warning in the
On Tue, Mar 24, 2015 at 08:50:34PM +, Chris Wilson wrote:
On Tue, Mar 24, 2015 at 12:40:09PM -0700, Rodrigo Vivi wrote:
This flag was being mostly used as a meta flag in some
cases and not covering other cases.
One of the risks is that it was masking some frontbuffer
trackings
On 03/25/2015 06:43 PM, Daniel Vetter wrote:
On Wed, Mar 25, 2015 at 01:24:01PM +0100, Linus Walleij wrote:
On Tue, Mar 24, 2015 at 11:53 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Mar 24, 2015 at 11:16 AM, Linus Walleij
linus.wall...@linaro.org wrote:
So summary:
- Reusing the
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6039
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 275/275
On Tue, Mar 24, 2015 at 10:13:54PM -0700, Matt Roper wrote:
On Fri, Mar 20, 2015 at 05:04:25PM -0700, Chandra Konduru wrote:
+struct intel_scaler {
+ int id;
+ int in_use;
+ uint32_t mode;
If I'm reading later patches correctly, this looks like this is always
PS_SCALER_MODE_HQ
On Tue, Mar 24, 2015 at 10:05:03PM +, ch...@chris-wilson.co.uk wrote:
On Tue, Mar 24, 2015 at 08:55:04PM +, Vivi, Rodrigo wrote:
On Tue, 2015-03-24 at 10:08 +, Chris Wilson wrote:
On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
On Mon, Mar 23, 2015 at
Our GPUs impose certain requirements upon buffers that depend upon how
exactly they are used. Typically this is expressed as that they require
a larger surface than would be naively computed by pitch * height.
Normally such requirements are hidden away in the userspace driver, but
when we accept
On Tue, Mar 24, 2015 at 08:35:42AM -0500, Chris wrote:
I am hoping that by joining this list I can get some kind of assistance
with this bug in the subject line. Every one to one and a half days my
system will just lockup with a black screen and only the mouse cursor
shown. It can be moved but
On 03/25/2015 06:28 AM, Daniel Vetter wrote:
On Tue, Mar 24, 2015 at 10:19:59AM +0200, Jani Nikula wrote:
On Mon, 23 Mar 2015, Jesse Barnes jbar...@virtuousgeek.org wrote:
Or users can just spam the log all they want.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89628
On Thu, Mar 12, 2015 at 5:31 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed
by display driver to enable the DSI panel on BYT platform where
the Panel EN/Disable control is routed thorugh CRC PMIC
CC: Samuel Ortiz
On Tue, 17 Mar 2015, Imre Deak imre.d...@intel.com wrote:
From: Vandana Kannan vandana.kan...@intel.com
The port detection register flags in SFUSE_STRAP and DDI_BUF_CTL_A are
not defined for BXT, so don't use them.
Suggested by Satheesh.
v2:
- DDI_BUF_CTL_A bit 0 is not useful on BXT.
On 20/03/2015 10:37, Deak, Imre wrote:
On Fri, 2015-03-20 at 09:08 +, Nick Hoath wrote:
On 17/03/2015 13:06, Imre Deak wrote:
On ti, 2015-03-17 at 11:35 +0100, Daniel Vetter wrote:
On Tue, Mar 17, 2015 at 11:39:40AM +0200, Imre Deak wrote:
Signed-off-by: Imre Deak imre.d...@intel.com
---
On Thu, Mar 12, 2015 at 5:31 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
CC: Samuel Ortiz
On Wed, Mar 25, 2015 at 10:00 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 25, 2015 at 09:11:17AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 4:54 AM, Daniel Vetter dan...@ffwll.ch wrote:
commit f55548b5af87ebfc586ca75748947f1c1b1a4a52
Author: Damien Lespiau
On Wed, Mar 25, 2015 at 03:55:43PM +0100, Linus Walleij wrote:
On Wed, Mar 25, 2015 at 2:13 PM, Daniel Vetter dan...@ffwll.ch wrote:
I quickly checked out your linux-gpio and it only has patch 2 to implement
the gpio. We also need patch 1 (but with the leak Thierry spotted fixed).
Should
On 03/25/2015 at 10:56 PM, Xi Ruoyao wrote:
On 03/25/2015 at 10:00 PM, Daniel Vetter wrote:
On Wed, Mar 25, 2015 at 09:11:17AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 4:54 AM, Daniel Vetter dan...@ffwll.ch wrote:
commit f55548b5af87ebfc586ca75748947f1c1b1a4a52
Author: Damien
At Wed, 25 Mar 2015 15:00:08 +0100,
Daniel Vetter wrote:
On Wed, Mar 25, 2015 at 09:11:17AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 4:54 AM, Daniel Vetter dan...@ffwll.ch wrote:
commit f55548b5af87ebfc586ca75748947f1c1b1a4a52
Author: Damien Lespiau damien.lesp...@intel.com
Include debugging symbols in tests by default to improve stack traces
and also set the compiler optimisation level to improve the debugging
experience.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
configure.ac | 14
m4/as-compiler-flag.m4 | 62
On Wed, Mar 25, 2015 at 3:15 PM, Kumar, Shobhit shobhit.ku...@intel.com wrote:
On Wed, 2015-03-25 at 13:27 +0100, Linus Walleij wrote:
On Wed, Feb 18, 2015 at 1:18 PM, Shobhit Kumar shobhit.ku...@intel.com
wrote:
Export Panel BACKLIGHT_EN(offset 0x51) and PANEL_EN(offset 0x52) as two
On Mon, Mar 23, 2015 at 04:21:07PM +0530, Sivakumar Thulasimani wrote:
void intel_prepare_ddi(struct drm_device *dev)
{
-int port;
+struct intel_digital_port *intel_dig_port;
+bool visited[I915_MAX_PORTS] = { 0, };
if (!HAS_DDI(dev))
return;
-for (port
On 03/25/2015 01:29 PM, Chris Wilson wrote:
Our GPUs impose certain requirements upon buffers that depend upon how
exactly they are used. Typically this is expressed as that they require
a larger surface than would be naively computed by pitch * height.
Normally such requirements are hidden
On Wed, Mar 25, 2015 at 11:37:35AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 10:00 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 25, 2015 at 09:11:17AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 4:54 AM, Daniel Vetter dan...@ffwll.ch wrote:
commit
On Wed, Mar 25, 2015 at 11:50 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 25, 2015 at 11:37:35AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 10:00 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 25, 2015 at 09:11:17AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 4:54
Add decodings for FAULT_REG
v2: fix fault encodings and ignore addr type for gen8+ (Michel)
fix engine mask
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/intel_error_decode.c | 42 ++
1 file changed, 42 insertions(+)
diff --git
On 03/25/2015 02:41 PM, Chris Wilson wrote:
On Wed, Mar 25, 2015 at 02:32:05PM +, Tvrtko Ursulin wrote:
On 03/25/2015 02:28 PM, Chris Wilson wrote:
What's important to make this trick work is to allocate new handles
every time. That way we fill up the GTT and thereby hope to skip over
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6048
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 269/269
On 03/25/2015 at 10:00 PM, Daniel Vetter wrote:
On Wed, Mar 25, 2015 at 09:11:17AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 4:54 AM, Daniel Vetter dan...@ffwll.ch wrote:
commit f55548b5af87ebfc586ca75748947f1c1b1a4a52
Author: Damien Lespiau damien.lesp...@intel.com
Date: Thu Feb 5
On Wed, 25 Mar 2015, Xi Ruoyao xry...@outlook.com wrote:
It's annoying to see my code caused so much trouble. I didn't test my code
with a HDMI device or I should've found this trouble before commiting. I
apologize for that again.
Don't worry about it. It's our fail, not yours.
BR,
Jani.
--
On Wed, 2015-03-25 at 16:08 +0530, Ramalingam C wrote:
On Wednesday 25 March 2015 12:42 AM, Rodrigo Vivi wrote:
With PSR enabled being pre computed on pipe_config we can now
prevent DRRS to be enabled along with PSR.
Cc: Ramalingam C ramalinga...@intel.com
Signed-off-by: Rodrigo Vivi
Avoid producing longs lists of subtests in the documentation and instead
provide instructions on how to obtain the full list.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
docs/reference/intel-gpu-tools/Makefile.am | 22 +++---
1 file changed, 15 insertions(+), 7
On Wed, Mar 25, 2015 at 02:32:05PM +, Tvrtko Ursulin wrote:
On 03/25/2015 02:28 PM, Chris Wilson wrote:
What's important to make this trick work is to allocate new handles
every time. That way we fill up the GTT and thereby hope to skip over
the fragmented part.
It does do that!
I
On 20/03/2015 10:25, Deak, Imre wrote:
On Fri, 2015-03-20 at 09:05 +, Nick Hoath wrote:
On 17/03/2015 09:39, Imre Deak wrote:
From: Ben Widawsky benjamin.widaw...@intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Imre Deak imre.d...@intel.com
---
On Wed, Mar 25, 2015 at 11:53 AM, Josh Boyer jwbo...@fedoraproject.org wrote:
On Wed, Mar 25, 2015 at 11:50 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 25, 2015 at 11:37:35AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 10:00 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar
On Tue, 17 Mar 2015, Imre Deak imre.d...@intel.com wrote:
From: A.Sunil Kamath sunil.kam...@intel.com
This patch will WARN if unused gmbus ports gets accessed for
BXT using gmbus_get_adapter also ensure that only valid ports
of BXT gets used. For BXT its more important to do this as it
has
On Wed, Mar 25, 2015 at 04:53:38PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
New kernels add the ability to pad objects to specified size at execbuf time.
Add the drm_intel_bo_pad_to_size API via which this padded size can be set.
Looks good, exactly what I
On Fri, Mar 20, 2015 at 05:04:33PM -0700, Chandra Konduru wrote:
Plane scaling and colorkey are mutually exclusive. Ensure scaling
isn't active at the time of enabling colorkey.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
I guess this is fine for now, but eventually we're going
On Fri, Mar 20, 2015 at 05:04:37PM -0700, Chandra Konduru wrote:
From intel_atomic_check, call intel_atomic_setup_scalers() to
assign scalers based on staged scaling requests. Fail the
transaction if setup returns error.
Setting up of scalers should be moved to atomic crtc check once
-Original Message-
From: Roper, Matthew D
Sent: Wednesday, March 25, 2015 10:22 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH 16/21 v2] drm/i915: Ensure setting up scalers into staged
crtc_state
On
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6049
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -6 269/269
On Tue, 17 Mar 2015, Imre Deak imre.d...@intel.com wrote:
From: A.Sunil Kamath sunil.kam...@intel.com
For BXT gmbus is pulled from GPU to CPU. From implementation
point of view only pin pair configuration will change. The
existing implementation supports all platforms previous to GEN8
and
On 3/25/2015 1:42 PM, Mika Kuoppala wrote:
These two registers contains the 48bit fault address.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/intel_error_decode.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git
On Wed, Mar 25, 2015 at 1:17 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 25, 2015 at 12:42:46PM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 11:53 AM, Josh Boyer jwbo...@fedoraproject.org
wrote:
On Wed, Mar 25, 2015 at 11:50 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, March 24, 2015 10:14 PM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH 07/21 v2] drm/i915: Helper function to update skylake
scaling ratio.
On
On 25 March 2015 at 02:50, He, Shuang shuang...@intel.com wrote:
(He Shuang on behalf of Liu Lei)
Tested-by: Lei,Liu lei.a@intel.com
Thanks, both patches in this series are now merged.
I-G-T test result:
./pm_sseu
IGT-Version: 1.9-g07be8fe (x86_64) (Linux:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
New kernels add the ability to pad objects to specified size at execbuf time.
Add the drm_intel_bo_pad_to_size API via which this padded size can be set.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Chris Wilson
On Wed, Mar 25, 2015 at 08:47:59AM -0700, Jesse Barnes wrote:
On 03/25/2015 06:28 AM, Daniel Vetter wrote:
On Tue, Mar 24, 2015 at 10:19:59AM +0200, Jani Nikula wrote:
On Mon, 23 Mar 2015, Jesse Barnes jbar...@virtuousgeek.org wrote:
Or users can just spam the log all they want.
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, March 24, 2015 10:14 PM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH 04/21 v2] drm/i915: skylake scaler structure definitions
On Fri, Mar 20,
On Wed, Mar 25, 2015 at 12:42:46PM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015 at 11:53 AM, Josh Boyer jwbo...@fedoraproject.org
wrote:
On Wed, Mar 25, 2015 at 11:50 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 25, 2015 at 11:37:35AM -0400, Josh Boyer wrote:
On Wed, Mar 25, 2015
Add rules to fix unused-result warnings when compiling with
_FORTIFY_SOURCE defined and apply them to the library and tests.
Signed-off-by: Thomas Wood thomas.w...@intel.com
---
lib/igt.cocci | 28
lib/igt_core.c| 20
From: Ville Syrjälä ville.syrj...@linux.intel.com
Recent BSW VBT has a VBT child device size 37 bytes instead of the 33
bytes our code assumes. This means we fail to parse the VBT and thus
fail to detect eDP ports properly and just register them as DP ports
instead.
Fix it up by using the
On 3/25/2015 1:42 PM, Mika Kuoppala wrote:
Add ERROR decodings for gen8
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/intel_error_decode.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index
On 3/25/2015 4:13 PM, Mika Kuoppala wrote:
Add decodings for FAULT_REG
v2: fix fault encodings and ignore addr type for gen8+ (Michel)
fix engine mask
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
tools/intel_error_decode.c | 42 ++
1
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, March 24, 2015 10:14 PM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH 05/21 v2] drm/i915: Initialize skylake scalers
On Fri, Mar 20, 2015 at
This is a very similar bug in the load detect code fixed in
commit 9128b040eb774e04bc23777b005ace2b66ab2a85
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Tue Mar 3 17:31:21 2015 +0100
drm/i915: Fix modeset state confusion in the load detect code
But this time around it was the
-Original Message-
From: Roper, Matthew D
Sent: Wednesday, March 25, 2015 10:22 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH 12/21 v2] drm/i915: Ensure colorkey and scaling aren't
enabled at same
From: Ville Syrjälä ville.syrj...@linux.intel.com
Replace the hardcoded 9 with a call to intel_freq_opcode(450).
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, March 24, 2015 10:15 PM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH 08/21 v2] drm/i915: Add helper function to update
scaler_users in
On Wed, Mar 25, 2015 at 07:27:35PM +, Vivi, Rodrigo wrote:
On Tue, 2015-03-24 at 22:05 +, ch...@chris-wilson.co.uk wrote:
On Tue, Mar 24, 2015 at 08:55:04PM +, Vivi, Rodrigo wrote:
On Tue, 2015-03-24 at 10:08 +, Chris Wilson wrote:
On Tue, Mar 24, 2015 at 11:03:30AM
On Wed, Mar 25, 2015 at 01:37:41PM -0400, Josh Boyer wrote:
Yeah that fail looks like we're freeing an fb that's still in use.
Hilarity happens and since that happens under console_lock at boot-up
your
machine dies.
Does that machine die the same way in drm-intel-nightly/linux-next?
From: Ville Syrjälä ville.syrj...@linux.intel.com
Check that the offset where expect to find the device id is withing the
BIOS image, instead of accessing whatever (if anything) happens to be
there.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
tools/intel_bios_reader.c | 7
From: Ville Syrjälä ville.syrj...@linux.intel.com
New stuff has been added to the end of the child device block at various
times, so using a hardcoded size for the block is a bad idea.
Fortunately the size of the block is listed in the VBT just before the
blocks themselves, so grab it from there.
psr.active is being unset out of the if so this here is useless and
duplicated.
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_psr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index
On Tue, 2015-03-24 at 22:05 +, ch...@chris-wilson.co.uk wrote:
On Tue, Mar 24, 2015 at 08:55:04PM +, Vivi, Rodrigo wrote:
On Tue, 2015-03-24 at 10:08 +, Chris Wilson wrote:
On Tue, Mar 24, 2015 at 11:03:30AM +0100, Daniel Vetter wrote:
On Mon, Mar 23, 2015 at 01:20:07PM
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, March 24, 2015 10:15 PM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Conselvan De Oliveira,
Ander
Subject: Re: [PATCH 09/21 v2] drm/i915: Add atomic function to setup scalers
scalers for a
On Wed, Mar 25, 2015 at 05:34:26PM +, Thomas Wood wrote:
Add rules to fix unused-result warnings when compiling with
_FORTIFY_SOURCE defined and apply them to the library and tests.
Signed-off-by: Thomas Wood thomas.w...@intel.com
I wasn't sure whether this is really worth the trouble.
On Fri, Mar 20, 2015 at 05:04:42PM -0700, Chandra Konduru wrote:
This patch enables skylake sprite plane display scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
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