Hi,
On to, 2015-03-26 at 16:14 +, Chris Wilson wrote:
On Thu, Mar 26, 2015 at 06:05:27PM +0200, Joonas Lahtinen wrote:
Install the test programs by default so that they can be packaged.
v2:
- Install more tests including scripts and their data
Packaged by whom?
Developers
On 3/27/2015 12:50 AM, Rodrigo Vivi wrote:
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and document it since it is now external.
Moving to a
On Thu, 26 Mar 2015, Tommi Rantala tt.rant...@gmail.com wrote:
Fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl, so that it
is different from the DRM_IOCTL_I915_SET_SPRITE_COLORKEY ioctl.
Signed-off-by: Tommi Rantala tt.rant...@gmail.com
Whoa. Broken since its introduction in
On to, 2015-03-26 at 17:29 +, Thomas Wood wrote:
On 26 March 2015 at 16:05, Joonas Lahtinen
joonas.lahti...@linux.intel.com wrote:
Install the test programs by default so that they can be packaged.
Could you also explain why the tests should be packaged?
Explained in previous e-mail.
On Fri, Mar 27, 2015 at 09:48:20AM +0100, Daniel Vetter wrote:
On Thu, Mar 26, 2015 at 12:41:16PM -0700, yu@intel.com wrote:
From: Alex Dai yu@intel.com
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM
On Thu, Mar 26, 2015 at 12:41:25PM -0700, yu@intel.com wrote:
From: Alex Dai yu@intel.com
Whenever RC6 state (0xA210) is changed, driver needs to notify GuC
via guc_action.
Issue: VIZ-4884
Change-Id: I15c661a915c670691d020471ecaccb00f7afb624
Signed-off-by: Alex Dai
On Thu, Mar 26, 2015 at 12:41:24PM -0700, yu@intel.com wrote:
From: Sagar Kamble sagar.a.kam...@intel.com
Need to take forcewake before GuC loading.
Please explain why and how things fall over if we're not doing this.
-Daniel
Issue: VIZ-4884
Change-Id:
On Fri, Mar 20, 2015 at 04:18:18PM +0200, Ander Conselvan de Oliveira wrote:
The function intel_dp_set_drrs_state() would decide which pipe to
downclock based on the staged config for the given connector. However,
the result of that function is immediate, and it uses input values from
On Fri, Mar 27, 2015 at 09:40:56AM +0100, Daniel Vetter wrote:
On Fri, Mar 27, 2015 at 09:03:35AM +0100, Thomas Richter wrote:
Hi folks, hi Daniel, hi Ville,
thanks again for getting my old Laptops (the R31 and the S6010) back to
life. It's been quite a way, but everything looks fine
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_i2c.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index cadbc17d2775..61931ca17cd9 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_i2c.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 61931ca17cd9..9696b738a691 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
We are conservative on the amount of free space available in the ring to
avoid overruning the potential MI_INTERRUPT after the seqno write.
Further undermining the justification for the change was that it was
applied incorrectly.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
The list handling during submission was quite confusing as the retired
requests were out of order - making it much harder in future to reduce
the extra lists. Simplify the submission mechanism to explicitly track
the actual requests current on each port and so trim the amount of work
required to
This is just so that I don't have to read about the batch pool on
systems that are not using it! Rather than using a newline between the
kernel clients and userspace clients, just distinguish the internal
allocations with a '[k]'
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
Since we use obj-active as a hint in many places throughout the code,
knowing its state in debugfs is extremely useful.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2
This is mostly useful for execlists where the rings switch between
contexts (and so checking that the ring's start register matches the
context is important).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
We can use the simpler spinlock form to disable interrupts as we are
always outside of an irq/softirq handler.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
In the next patch, I want to use the structure elsewhere and so require
it defined earlier. Rather than move the definition to an earlier location
where it feels very odd, place it in its own header file.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin
requests are even more frequently allocated than objects and equally
benefit from having a dedicated slab.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_dma.c | 12
drivers/gpu/drm/i915/i915_drv.h | 5 -
Move the madvise logic out of the execbuffer main path into the
relatively rare allocation path, making the execbuffer manipulation less
fragile.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 12 +++--
When we pin the execlists context on queuing, it the ideal time to map
the register page that we need to update when we submit the request to
the hardware (and keep it around for future requests).
This avoids having to do an atomic kmap on every submission. On the
other hand, it does depend upon
With a little complexity to handle cmds straddling page boundaries, we
can completely avoiding having to vmap the batch and the shadow batch
objects whilst running the command parser.
On ivb i7-3720MQ:
x11perf -dot before 54.3M, after 53.2M (max 203M)
glxgears before 7110 fps, after 7300 fps
This eliminates six needless spin lock/unlock pairs when writing out
ELSP.
v2: Respin with my preferred colour.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk [v2]
---
drivers/gpu/drm/i915/i915_drv.h | 18
At runtime, this helps ensure that the batch pools are kept trim and
fast. Then at suspend, this releases memory that we do not need to
restore. It also ties into the oom-notifier to ensure that we recover as
much kernel memory as possible during OOM.
Signed-off-by: Chris Wilson
We already assign a unique identifier to every request: seqno. That
someone felt like adding a second one without even mentioning why and
tweaking ABI smells very fishy.
Fixes regression from
commit b3a38998f042b862f5ba4d7f2268f3a8dfb4883a
Author: Nick Hoath nicholas.ho...@intel.com
Date: Thu
Instead of querying the reset counter before every access to the ring,
query it the first time we touch the ring, and do a final compare when
submitting the request. For correctness, we need to then sanitize how
the reset_counter is incremented to prevent broken submission and
waiting across
We want to run the execlists retire-ring callback whilst we retire the
requests on a particular ring. Having done so, we know that the per-ring
request list is the superset of all requests and so can simplify the
is-idle check.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
Since
commit 17cabf571e50677d980e9ab2a43c5f11213003ae
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Wed Jan 14 11:20:57 2015 +
drm/i915: Trim the command parser allocations
we may then try to allocate a zero-sized object and attempt to extract
its pages. Understandably this
I woke up one morning and found 50k objects sitting in the batch pool
and every search seemed to iterate the entire list... Painting the
screen in oils would provide a more fluid display.
One issue with the current design is that we only check for retirements
on the current ring when preparing to
On Fri, Mar 27, 2015 at 12:06 PM, Takashi Iwai ti...@suse.de wrote:
At Fri, 27 Mar 2015 12:01:33 +0100,
Sedat Dilek wrote:
On Wed, Mar 25, 2015 at 3:34 PM, Takashi Iwai ti...@suse.de wrote:
At Wed, 25 Mar 2015 14:26:50 +0100,
Daniel Vetter wrote:
On Tue, Mar 24, 2015 at 07:09:03PM
To allow for views where the view type is not defined by the view type only,
like it is in stereo or rotated 90 degree view, change the semantic to require
the whole view structure for comparison when we match a GGTT view.
This allows including parameters like offset to be included in the view
On Broxton per specification the GTT has to be mapped as uncached.
This was caught by the PTE write readback warning, which showed a
corrupted PTE value with using the current write-combine mapping.
v2:
- add comment explaining how the problem with WC mapping manifests
(Daniel)
Signed-off-by:
To allow for views where the view type is not defined by the view type only,
like it is in stereo or rotated 90 degree view, change the semantic to require
the whole view structure for comparison when we match a GGTT view.
This allows including parameters like offset to be included in the view
Hi,
On 03/27/2015 10:03 AM, Joonas Lahtinen wrote:
To allow for views where the view type is not defined by the view type only,
like it is in stereo or rotated 90 degree view, change the semantic to require
the whole view structure for comparison when we match a GGTT view.
This allows
Not only does it make for good documentation and debugging aide, but it
is also vital for when we want to unwind requests - such as when
throwing away an incomplete request.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 12 +++
Quite a few of our objects used for internal hardware programming do not
benefit from being swappable or from being zero initialised. As such
they do not benefit from using a shmemfs backing storage and since they
are internal and never directly exposed to the user, we do not need to
worry about
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so frequently waiting on the GPU as it
switches rings. In
In a few cases, having a direct pointer to the drm_i915_private from the
request is useful.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 11 ---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 5 insertions(+), 8 deletions(-)
diff
I was looking at the performance degredation due to execlists and
decided to pick a few of the easier microoptimisations. Individually
they may not amount to much (except for spinning on requests!) but the
volume does quickly add up, giving benefit to quite a few of our more
driver bound tests.
We were missing a convenience stub to aquire the right mutex whilst
dropping the request, so add it.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_gem.c | 8 ++--
2 files changed, 15 insertions(+), 6
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c| 56 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +-
2 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
12:58 jlahtine there're actually equally many i915_is_ggtt(vma-vm)
calls
12:58 jlahtine (one less)
12:59 jlahtine so while at it I'd make it vm-is_ggtt and
vma-is_ggtt
12:59 jlahtine then get rid of the whole helper, maybe
13:00 ickle you preempted my beautiful macro
13:03 ickle just don't
Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to compensate for the RPS boosts.
v2: Rebase
v3: Exclude
Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls as we synchronise between rings -
greatly
The multiple levels of indirect do nothing but hinder the compiler and
the pointer chasing turns to be quite painful but painless to fix.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 4 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a visible stutter. Boosting the GPU frequency
doesn't prevent us
With boosting for missed pageflips, we have a much stronger indication
of when we need to (temporarily) boost GPU frequency to ensure smooth
delivery of frames. So now only allow each client to perform one RPS boost
in each period of GPU activity due to stalling on results.
Signed-off-by: Chris
The issue is that by computing the last_adj value after applying the
clamping, we can end up with a bogus value for feeding into the next RPS
autotuning step.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Deepak S deepa...@linux.intel.com
As we perform the mmio-flip without any locking and then try to acquire
the struct_mutex prior to dereferencing the request, it is possible for
userspace to queue a new pageflip before the worker can finish clearing
the old state - and then it will clear the new flip request. The result
is that
The biggest user of i915_gem_object_get_page() is the relocation
processing during execbuffer. Typically userspace passes in a set of
relocations in sorted order. Sadly, we alternate between relocations
increasing from the start of the buffers, and relocations decreasing
from the end. However the
The cmd parser has the biggest impact on the BLT ring, because it is
relatively verbose composed to the other engines as the vertex data is
inline. It also typically has runs of repeating commands (again since
the vertex data is inline, it typically has sequences of XY_SETUP_BLT,
This reverts commit ec5cc0f9b019af95e4571a9fa162d94294c8d90b
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Thu Jun 12 10:28:55 2014 +0100
drm/i915: Restrict GPU boost to the RCS engine
The premise that media/blitter workloads are not affected by boosting is
patently false with a trip
The hardware is documentated as treating the TAIL register update as
serialising, so we can relax the barriers when filling the rings.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.h| 7 ---
drivers/gpu/drm/i915/intel_ringbuffer.h | 17
The offset doesn't change once the context is pinned, but the lookup
turns out to be comparatively costly as it gets repeated for every
request.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c| 22 --
After we successfully allocate them, we will fill them with their
initial contents (either the chain of page tables, or a pointer to the
scratch page).
Regression from
commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Tue Feb 24 16:22:36 2015
After the removal of DRI1, all access to the rings are through requests
and so we can always be sure that there is a request to wait upon to
free up available space. The fallback code only existed so that we could
quiesce the GPU following unmediated access by DRI1.
Signed-off-by: Chris Wilson
Similar in vain in reducing the number of unrequired spinlocks used for
execlist command submission (where the forcewake is required but
manually controlled), we know that the IRQ registers are outside of the
powerwell and so we can access them directly. Since we now have direct
access exported
Remove some needless variables and parameter passing.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_irq.c | 113 +---
1 file changed, 49 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
Delay the expensive read on the FPGA_DBG register from once per mmio to
once per forcewake section when we are doing the general wellbeing
check rather than the targetted error detection. This almost reduces
the overhead of the debug facility (for example when submitting execlists)
to zero whilst
Now with the trimmed memcpy before the command parser, we try to
allocate many different sizes of batches, predominantly one or two
pages. We can therefore speed up searching for a good sized batch by
keeping the objects of buckets of roughly the same size.
v2: Add a comment about bucket sizes
This reimplements the denial-of-service protection against igt from
commit 227f782e4667fc622810bce8be8ccdeee45f89c2
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Thu May 15 10:41:42 2014 +0100
drm/i915: Retire requests before creating a new one
and transfers the stall from before
As we never expose context objects directly to userspace, we can forgo
allocating a first-class GEM object for them and prefer to use the
limited resource of reserved/stolen memory for them. Note this means
that their initial contents are undefined.
However, a downside of using stolen objects for
If we have llc coherency, we can write directly into the ringbuffer
using ordinary cached writes rather than forcing WC access.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 60 +++--
1 file changed, 49
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f87e7b90939c..1104a21abc08 100644
---
When we submit a request to the GPU, we first take the rpm wakelock, and
only release it once the GPU has been idle for a small period of time
after all requests have been complete. This means that we are sure no
new interrupt can arrive whilst we do not hold the rpm wakelock and so
can drop the
Slightly more extravagant than the previous patch is to use the
I915_READ_FW() registers for all the bounded reads in
intel_lrc_irq_handler - for even more spinlock reduction.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c | 32
BSpec recommends to keep the main link state consistent
between the source and the sink. As per that, update
the main link state in sink DPCD register to 'active',
for Valleyview based platforms.
Signed-off-by: Durgadoss R durgados...@intel.com
---
drivers/gpu/drm/i915/intel_psr.c | 2 +-
1 file
On Wed, Mar 25, 2015 at 3:34 PM, Takashi Iwai ti...@suse.de wrote:
At Wed, 25 Mar 2015 14:26:50 +0100,
Daniel Vetter wrote:
On Tue, Mar 24, 2015 at 07:09:03PM +0100, Sedat Dilek wrote:
On Mon, Mar 23, 2015 at 9:25 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Mar 23, 2015 at 07:25:27AM
At Fri, 27 Mar 2015 12:01:33 +0100,
Sedat Dilek wrote:
On Wed, Mar 25, 2015 at 3:34 PM, Takashi Iwai ti...@suse.de wrote:
At Wed, 25 Mar 2015 14:26:50 +0100,
Daniel Vetter wrote:
On Tue, Mar 24, 2015 at 07:09:03PM +0100, Sedat Dilek wrote:
On Mon, Mar 23, 2015 at 9:25 AM, Daniel
On 03/26/2015 09:31 PM, Chris Wilson wrote:
On Thu, Mar 26, 2015 at 05:43:33PM +, Tvrtko Ursulin wrote:
-static int
-i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
-{
- if (!obj-active)
- return 0;
-
- /* Manually manage the write flush as
drivers/gpu/drm/i915/i915_gem_gtt.c:1349:1-4: WARNING: end returns can be
simpified and declaration on line 1347 can be dropped
Simplify a trivial if-return sequence. Possibly combine with a
preceding function call.
Generated by: scripts/coccinelle/misc/simple_return.cocci
CC: Michel Thierry
On Fri, Mar 27, 2015 at 09:10:02AM +0100, Daniel Vetter wrote:
It's completely unused and Tommi noticed that the #define is borked
since forever. I've done a git search in userspace and only found
broken definitions and no users anywhere.
Cc: Tommi Rantala tt.rant...@gmail.com
On Fri, Mar 27, 2015 at 11:37:09AM +0530, Sivakumar Thulasimani wrote:
On 3/27/2015 12:50 AM, Rodrigo Vivi wrote:
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is not used after this patch.
Rename
On Thu, Mar 26, 2015 at 12:41:13PM -0700, yu@intel.com wrote:
From: Dave Gordon david.s.gor...@intel.com
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But we can't do that until any
required firmware has been loaded, which
On 3/27/2015 2:02 PM, Daniel Vetter wrote:
On Fri, Mar 27, 2015 at 11:37:09AM +0530, Sivakumar Thulasimani wrote:
On 3/27/2015 12:50 AM, Rodrigo Vivi wrote:
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is
From: A.Sunil Kamath sunil.kam...@intel.com
For BXT gmbus is pulled from PCH to CPU. From implementation point of
view only pin pair configuration will change. The existing
implementation supports all platforms previous to GEN8 and also SKL. But
for BXT pin pair configuration is completely
On Fri, Mar 20, 2015 at 04:18:03PM +0200, Ander Conselvan de Oliveira wrote:
@@ -8924,6 +8932,11 @@ retry:
else
intel_crtc-new_config = NULL;
fail_unlock:
+ if (state) {
+ drm_atomic_state_free(state);
+ state = NULL;
+ }
I think we
On Fri, Mar 20, 2015 at 04:18:19PM +0200, Ander Conselvan de Oliveira wrote:
Some of the crtc_compute_clock() still depended on encoder-new_crtc
since they didn't use intel_pipe_will_have_type() and used an open
coded version of that function instead. This patch replaces those with
the
Reviewed-by: Ander Conselvan de Oliveira conselv...@gmail.com
On Tue, 2015-03-03 at 18:03 +0100, Daniel Vetter wrote:
This is useful for writing igts to make sure we don't break this,
without being forced to own a one of these dinosaurs.
Suggested-by: Jesse Barnes jbar...@virtuousgeek.org
On Thu, Mar 26, 2015 at 05:43:51PM +0200, Mika Kuoppala wrote:
Michel Thierry michel.thie...@intel.com writes:
The first 2 patches are fixes from the previous patchset, reported by static
analysis tools, while the last 2 patches complete the required work for
gen6/7.
I've also
On Thu, Mar 26, 2015 at 12:41:16PM -0700, yu@intel.com wrote:
From: Alex Dai yu@intel.com
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
used internally for its Boot ROM, SRAM etc. Currently this
Install the test programs by default so that they can be packaged.
Tested the testdisplay test so that it still runs after modifications,
as it depends on script data.
Packaging is useful when building a complete software stack for a
DUT from scratch. This should bring us closer to achieving a
On Fri, Mar 20, 2015 at 04:18:00PM +0200, Ander Conselvan de Oliveira wrote:
Version 3 of the series with comments from Chandra addressed. I'm sending the
whole series again so it goes through another round of PRTS testing.
Thanks,
Ander
Ander Conselvan de Oliveira (19):
drm/i915: Add
On Fri, Mar 27, 2015 at 09:03:35AM +0100, Thomas Richter wrote:
Hi folks, hi Daniel, hi Ville,
thanks again for getting my old Laptops (the R31 and the S6010) back to
life. It's been quite a way, but everything looks fine now.
There is one interesting observation I made, though, on my IBM
From: A.Sunil Kamath sunil.kam...@intel.com
For BXT gmbus is pulled from PCH to CPU. From implementation point of
view only pin pair configuration will change. The existing
implementation supports all platforms previous to GEN8 and also SKL. But
for BXT pin pair configuration is completely
On Fri, Mar 27, 2015 at 08:39:56AM +0200, Jani Nikula wrote:
On Thu, 26 Mar 2015, Tommi Rantala tt.rant...@gmail.com wrote:
Fix definition of the DRM_IOCTL_I915_GET_SPRITE_COLORKEY ioctl, so that it
is different from the DRM_IOCTL_I915_SET_SPRITE_COLORKEY ioctl.
Signed-off-by: Tommi
It's completely unused and Tommi noticed that the #define is borked
since forever. I've done a git search in userspace and only found
broken definitions and no users anywhere.
Cc: Tommi Rantala tt.rant...@gmail.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
On Thu, Mar 26, 2015 at 10:27:25AM -0700, Jesse Barnes wrote:
On 03/26/2015 06:22 AM, Daniel Vetter wrote:
On Mon, Mar 23, 2015 at 12:13:56PM +, John Harrison wrote:
On 23/03/2015 09:22, Daniel Vetter wrote:
On Fri, Mar 20, 2015 at 09:11:35PM +, Chris Wilson wrote:
On Fri, Mar 20,
On pe, 2015-03-27 at 10:51 +0200, Joonas Lahtinen wrote:
Install the test programs by default so that they can be packaged.
Tested the testdisplay test so that it still runs after modifications,
as it depends on script data.
Duh, s/depends on script data/depends on a data file/.
Also,
On Fri, Mar 20, 2015 at 04:18:16PM +0200, Ander Conselvan de Oliveira wrote:
Makes that code atomic ready.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 49
++--
1 file
On Fri, Mar 20, 2015 at 04:18:17PM +0200, Ander Conselvan de Oliveira wrote:
Pass a crtc_state to it and find whether the pipe has an encoder of a
given type by looking at the drm_atomic_state the crtc_state points to.
Until recently i9xx_get_refclk() used to be called indirectly from
On Fri, Mar 27, 2015 at 12:20:23AM +0200, Jani Nikula wrote:
From: A.Sunil Kamath sunil.kam...@intel.com
For BXT gmbus is pulled from GPU to CPU. From implementation point of
s/GPU/PCH/
-Daniel
view only pin pair configuration will change. The existing
implementation supports all platforms
On Thu, Mar 26, 2015 at 12:41:07PM -0700, yu@intel.com wrote:
From: Alex Dai yu@intel.com
This series of patch is to enable ExecList submission via GuC. Here are some
key points related to this series, not in particular order.
*** i915_guc_client ***
We use the term client to
On Fri, 2015-03-27 at 10:01 +0100, Daniel Vetter wrote:
On Fri, Mar 20, 2015 at 04:18:03PM +0200, Ander Conselvan de Oliveira wrote:
@@ -8924,6 +8932,11 @@ retry:
else
intel_crtc-new_config = NULL;
fail_unlock:
+ if (state) {
+
On 03/27/2015 11:01 AM, Chris Wilson wrote:
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so
From: Shashank Sharma shashank.sha...@intel.com
In BXT, DDI hotplug control has been moved to CPU from PCH.
This patch adds a new IRQ setup function for BXT which:
1. Checks which HPD ports are requested to be enabled by encoders.
2. Enables those ports in the hot plug control register.
3.
On 03/27/2015 11:47 AM, Chris Wilson wrote:
On Fri, Mar 27, 2015 at 11:40:12AM +, Tvrtko Ursulin wrote:
+/* Like above but take and hold the uncore lock for the duration.
+ * Must be used with I915_READ_FW and friends.
+ */
+void intel_uncore_forcewake_irqlock(struct drm_i915_private
v2:
- Make the condition to select between SKL and BXT consistent with the
corresponding condition in init_workarounds_ring (Nick)
Signed-off-by: Imre Deak imre.d...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git
On 3/27/2015 11:26 AM, kbuild test robot wrote:
drivers/gpu/drm/i915/i915_gem_gtt.c:1349:1-4: WARNING: end returns can be
simpified and declaration on line 1347 can be dropped
Simplify a trivial if-return sequence. Possibly combine with a
preceding function call.
Generated by:
On Thu, 26 Mar 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Mar 26, 2015 at 10:42:00AM +0200, Jani Nikula wrote:
If the user supplies EDID through firmware or debugfs override, the
driver callbacks are bypassed and the connector ELD does not get
updated, and audio fails. Set ELD for
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