On Tue, Apr 14, 2015 at 04:08:44PM +0100, Chris Wilson wrote:
Convert the bo-cache into 2 phases:
1. A two second cache of recently used buffers, keep untouched.
2. A two second cache of older buffers, marked for eviction.
This helps reduce ioctl traffic on a rapid turnover in working
Hi Daniel, hi Ville,
please find a patch attached for the NatSemi 2501 DVO found in the
Fujitsu S6010 (and others). This patch
includes proper definitions for some registers of the (undocumented)
scaler of the DVO chip, and
also enables dithering by default on all modes. This improves image
On Tue, 14 Apr 2015, Mika Kuoppala mika.kuopp...@linux.intel.com wrote:
Daniel Vetter daniel.vet...@ffwll.ch writes:
We stopped handling them in
commit aaecdf611a05cac26a94713bad25297e60225c29
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Tue Nov 4 15:52:22 2014 +0100
drm/i915:
On Tue, 14 Apr 2015, Sonika Jindal sonika.jin...@intel.com wrote:
The HDMI translation table is added back to bspec, so adding it,
and defaulting the 800mV+0dB entry.
add back? Please reference the commit that removed the translations.
BR,
Jani.
Cc: Damien Lespiau damien.lesp...@intel.com
On Tue, Apr 14, 2015 at 05:35:22PM +0200, Daniel Vetter wrote:
With the binding regression from the original full ppgtt patches
fixed we can throw the switch. Yay!
This changelog is misleading. The validation part of the command parser
has been running for some time, with people starting to
On Tue, 2015-04-14 at 20:04 +0200, Daniel Vetter wrote:
On Fri, Apr 10, 2015 at 11:15:10AM -0700, Rodrigo Vivi wrote:
According to spec: In PSR HW or SW mode, SW set this bit before writing
registers for a flip. It will be self-clear when it gets to the PSR
active state.
Some versions
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