Chris Wilson ch...@chris-wilson.co.uk writes:
On Tue, Apr 14, 2015 at 05:35:12PM +0200, Daniel Vetter wrote:
They change with the address space and not with each vma, so move them
into the right pile of vfuncs. Save 2 pointers per vma and clarifies
the code.
Using per-vma vfunc allows you
On 04/16/2015 03:29 AM, Peter Hurley wrote:
On 04/15/2015 05:26 PM, Mario Kleiner wrote:
A couple of questions to educate me and one review comment.
On 04/15/2015 07:34 PM, Daniel Vetter wrote:
This was a bit too much cargo-culted, so lets make it solid:
- vblank-count doesn't need to be an
On ke, 2015-04-15 at 16:52 -0700, Rodrigo Vivi wrote:
From: Imre Deak imre.d...@intel.com
Due this typo we don't save/restore the GFX_MAX_REQ_COUNT register across
suspend/resume, so fix this.
This was introduced in
commit ddeea5b0c36f3665446518c609be91f9336ef674
Author: Imre Deak
Update the hot plug function to handle the SST case. Instead of placing
the SST case within the long/short pulse block, it is now handled after
determining that MST mode is not in use. This way, the topology management
layer can handle any MST-related operations while SST operations are still
On Wed, Apr 15, 2015 at 03:14:38PM -0700, Chandra Konduru wrote:
This patch enables skylake primary plane scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-move detach_scalers to crtc commit path (Matt)
-use values in plane_state-src as
On Wed, 2015-04-15 at 16:34 +0200, Maarten Lankhorst wrote:
This makes disabling planes more explicit.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
drivers/gpu/drm/i915/intel_display.c | 36
On Tue, Mar 17, 2015 at 11:39:58AM +0200, Imre Deak wrote:
From: A.Sunil Kamath sunil.kam...@intel.com
v2: Modified as per review comments from Imre
- Mention enabling instead of allowing in the debug trace and
remove unnecessary comments.
v3:
- Rebase to latest.
- Move DC9-related
On Wed, Apr 15, 2015 at 03:15:02PM -0700, Chandra Konduru wrote:
This patch enables skylake sprite plane display scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-detaching scalers moved to crtc commit path (Matt)
v4:
-changes to align with
On Thu, Apr 16, 2015 at 09:18:48AM +0300, Mika Kuoppala wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
On Tue, Apr 14, 2015 at 05:35:12PM +0200, Daniel Vetter wrote:
They change with the address space and not with each vma, so move them
into the right pile of vfuncs. Save 2 pointers
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6204
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, Apr 15, 2015 at 11:59:13PM +, Vivi, Rodrigo wrote:
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Nak. Head isn't unused now.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Intel-gfx mailing list
On Thu, Apr 16, 2015 at 09:28:02AM +0200, Ingo Molnar wrote:
* Chris Wilson ch...@chris-wilson.co.uk wrote:
For fixed sized copies, copy_to_user() will utilize __put_user_size
fastpaths. However, it is missing the translation for 64bit copies on
x86/32. Testing on a Pinetrail Atom, the
On Thu, Apr 16, 2015 at 12:46:53AM +0300, Laurent Pinchart wrote:
Hi Daniel,
Thank you for the patch.
On Friday 10 April 2015 16:22:39 Daniel Vetter wrote:
It's a silly thing to do and surprises driver writers. Most likely
this did already blow up for exynos.
It's also a silly
On Thu, Apr 16, 2015 at 02:22:07PM +0530, Animesh Manna wrote:
+#define I915_CSR_SKL i915/skl_dmc_ver1.bin
This needs to be skl_dmc_ver4.bin, because that's the version we made
public.
--
Damien
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On Tue, Mar 17, 2015 at 11:40:08AM +0200, Imre Deak wrote:
From: Satheeshakrishna M satheeshakrishn...@intel.com
Assign PLL for pipe (dependent on port attached to the pipe)
v2:
- fix incorrect encoder vs. new_encoder check for crtc (imre)
v3:
- warn and return error if no encoder is
Single channel LVDS maxes out at 112 MHz. All 17 models with i915
graphics had a resolution of 1920x1200 (193 MHz), necessitating dual
channel LVDS. The 15 pre-retina models had either 1440x900 (106 MHz)
or 1680x1050 (119 MHz), both versions used dual channel LVDS even
though the smaller one would
Hi Intel Graphics Drivers Team,
Please see my earlier email below regarding the current Intel Drivers Package
that is held on the 01.org site.
It doesn't work for my system, which is running Ubuntu 14.04 LTS. The version
the website is telling me to download runs on Ubuntu 14.10, but refuses
On Wed, Apr 15, 2015 at 02:22:54PM +, Antoine, Peter wrote:
Hi Daniel,
I am having a look at this now, as have some time.
So, to sum up what I think you want.
1. Re-base and apply the patches (so that the known holes are closed in
the Nouveau driver).
2. Add DRIVER_KMS_LEGACY_CONTEXT
* Chris Wilson ch...@chris-wilson.co.uk wrote:
For fixed sized copies, copy_to_user() will utilize __put_user_size
fastpaths. However, it is missing the translation for 64bit copies on
x86/32. Testing on a Pinetrail Atom, the 64 bit put_user fastpath is
substantially faster than the generic
From: Ville Syrjälä ville.syrj...@linux.intel.com
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the actual hardware programming differs,
the rest is pretty much the same.
The
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add support for changing cdclk frequency during runtime on BDW. The
procedure is quite a bit different on BDW from the one on HSW, so
add a separate function for it.
Also with IPS enabled the actual pixel rate mustn't exceed 95% of cdclk,
so take
From: Ville Syrjälä ville.syrj...@linux.intel.com
Implement cdclk extraction for g33, 965gm and g4x platforms. The details
came from configdb. Sadly there isn't anything there for other gen3/gen4
chipsets.
So far I've tested this on one ELK where it gave me a HPLL VCO of 5333
MHz and cdclk of
From: Ville Syrjälä ville.syrj...@linux.intel.com
We need to tell BDW ULT and ULX apart.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
v2: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
Author:Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
Rather that extracting the current cdclk freuqncy every time someone
wants to know it, cache the current value and use that. VLV/CHV already
stored a cached value there so just expand that to cover all platforms.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
Print a warning if we fall through the .get_display_clock_speed() function
pointer setup. We end up assuming a 133MHz cdclk which should mean that
at least we avoid any 0 deivisions and whatnot. But this could at least
help remind people that they
From: Ville Syrjälä ville.syrj...@linux.intel.com
Actually read the HPLLCC register insted of assuming it's 0. Fix the
HPLLCC bit definitions and all the missing ones from the 852GME spec.
852GME, 854 and 855 all seem to match the same HPLLC encoding even
though only some of the values are valid
From: Ville Syrjälä ville.syrj...@linux.intel.com
ilk_get_aux_clock_divider() is now a subset of
hsw_get_aux_clock_divider() so unify them.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
v2: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
Author:Ville
This patch series rebases Ville's original cdclk patch series
excluding the ones that are already reviewed.
http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html
The patches include modifications to
Ville Syrjälä (12):
drm/i915: Fix i855 get_display_clock_speed
drm/i915:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.
There's no similar restriction listed for HSW, so leave that one alone
for now.
v2: Add
From: Ville Syrjälä ville.syrj...@linux.intel.com
It seems 852GM/GMV uses a different HPLLCC encoding than the other
85x platforms. For 852GM/GMV cdclk is always 133MHz. Try to detect that
using the PCI revision (sinc the device ID seems useless for that). I'm
not at all sure this is a good idea,
From: Ville Syrjälä ville.syrj...@linux.intel.com
Keep the cdclk maximum supported frequency around in dev_priv so that we
can verify certain things against it before actually changing the cdclk
frequency.
For now only VLV/CHV have support changing cdclk frequency, so other
plarforms get to
From: Ville Syrjälä ville.syrj...@linux.intel.com
Rather than reading out the current cdclk value use the cached value we
have tucked away in dev_priv.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
v2: Rebased to the latest
Signed-off-by: Mika Kahola mika.kah...@intel.com
Author:
On Thu, Apr 16, 2015 at 12:26:52PM +0200, Maarten Lankhorst wrote:
This makes disabling planes more explicit.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
Changes since v1:
- Create a intel_crtc_reset function for i915_debugfs.c instead of calling
.crtc members
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