Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6343
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1
On Thu, May 7, 2015 at 9:40 PM, Steven Rostedt rost...@goodmis.org wrote:
[ cut here ]
WARNING: CPU: 2 PID: 0 at
/work/autotest/nobackup/linux-test.git/drivers/gpu/drm/i915/intel_uncore.c:566
hsw_unclaimed_reg_debug.isra.10+0x6c/0x84()
Unclaimed register detected
On Fri, May 08, 2015 at 02:29:30AM +, Konduru, Chandra wrote:
+/* Primary plane formats for gen = 9 */
+static const uint32_t intel_primary_formats_gen9[] = {
+ COMMON_PRIMARY_FORMATS, \
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+
On Thu, May 07, 2015 at 06:38:37PM +0100, Damien Lespiau wrote:
A part of this function was indented with 2 tabs and 1 space instead of
just 2 tabs. We're going to touch that code, so start by re-indenting
it.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Queued for -next, thanks
On Thu, May 07, 2015 at 03:23:17PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Let's just steal the crc namespace and add this by default to
igt_pipe_crc_collect_crc() instead of adding more calls to other
tests. If tests want special waits on just some of their
On Thu, 2015-05-07 at 14:31 -0700, Matt Roper wrote:
With the recent modeset internal rework, we wind up setting
crtc_state-enable to false, but leave crtc_state-active as true, which
is incorrect. This mismatch gets caught by drm_atomic_crtc_check() and
causes subsequent atomic operations
On 05/08/2015 01:03 AM, Konduru, Chandra wrote:
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Thursday, May 07, 2015 2:15 AM
To: Konduru, Chandra; Intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko
Subject: Re: [PATCH i-g-t 3/4] igt_kms: Do not
On Fri, May 08, 2015 at 10:56:03AM +0300, Ander Conselvan De Oliveira wrote:
On Thu, 2015-05-07 at 14:31 -0700, Matt Roper wrote:
With the recent modeset internal rework, we wind up setting
crtc_state-enable to false, but leave crtc_state-active as true, which
is incorrect. This mismatch
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6345
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, May 07, 2015 at 06:16:04PM -0700, Chandra Konduru wrote:
Scaler id is added for skylake to handle its shared scalers.
This is not applicable for platforms before SKL. This patch limits
the scaler_id check during intel_pipe_config_compare to platforms
SKL and above.
Please add a
On Fri, May 08, 2015 at 10:54:26AM +0530, Ankitprasad Sharma wrote:
On Thu, 2015-05-07 at 08:52 +0200, Daniel Vetter wrote:
On Wed, May 06, 2015 at 03:51:52PM +0530, ankitprasad.r.sha...@intel.com
wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds the
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6344
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6346
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Thu, Apr 30, 2015 at 12:32:15PM +0100, Rebecca N. Palmer wrote:
i915_parse_cmds returns -EACCES on chained batches, which tells the
caller to abort and dispatch the workload as a non-secure batch,
but the mechanism implementing that was broken when
flags |= I915_DISPATCH_SECURE was moved
Hi Dave, sorry, I'm a bit late this week with the i915 fixes.
BR,
Jani.
The following changes since commit 5ebe6afaf0057ac3eaeb98defd5456894b446d22:
Linux 4.1-rc2 (2015-05-03 19:22:23 -0700)
are available in the git repository at:
git://anongit.freedesktop.org/drm-intel
Rebecca N. Palmer rebecca_pal...@zoho.com writes:
Hi,
i915_parse_cmds returns -EACCES on chained batches, which tells the
caller to abort and dispatch the workload as a non-secure batch,
but the mechanism implementing that was broken when
flags |= I915_DISPATCH_SECURE was moved from
Hello,
the kernel oops reported back in April
(http://lists.freedesktop.org/archives/intel-gfx/2015-April/064066.html) is
back resulting in the same oops as soon as I connect my Laptop to its docking
station or boot with docking already connected. The issue was introduced again
somewhere
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
Since Punit validates the rps
From: Deepak S deepa...@linux.intel.com
It is obsered on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let it enter rc6 with a
high frequency Vnn also remains high. Extending vlv_set_rps_idle()
workaround on CHV/BSW.
suggested-by: Ville Syrjälä
On Fri, 8 May 2015 12:10:15 -0300
Ismael Luceno ism...@iodev.co.uk wrote:
On Thu, 07 May 2015 16:41:48 +0300
Jani Nikula jani.nik...@linux.intel.com wrote:
On Thu, 07 May 2015, Matt Roper matthew.d.ro...@intel.com wrote:
On Thu, May 07, 2015 at 12:12:18PM +0300, Jani Nikula wrote:
On
On Friday 08 May 2015 06:52 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 06:31:23PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Not sure which LDO programming sequence delay should be
Hi Chandra,
On Mon, Apr 27, 2015 at 03:47:37PM -0700, Chandra Konduru wrote:
Skylake nv12 format requires dbuf (aka. ddb) calculations
and programming for each of y and uv sub-planes. Made minor
changes to reuse current dbuf calculations and programming
for uv plane. i.e., with this change,
On Fri, 08 May 2015, Daniel Martin consume.no...@gmail.com wrote:
On 8 May 2015 at 11:26, Daniel Martin consume.no...@gmail.com wrote:
Hi,
I've just tested drm-intel-nightly, last commit:
20e7fca drm-intel-nightly: 2015y-05m-07d-16h-16m-10s UTC
integration manifest
and it makes the
On Fri, May 08, 2015 at 06:31:23PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Not sure which LDO programming sequence delay should be used for the CHV
PHY, but the spec says that 600ns
(i915_cmd_parser.c:1054)
removes any offset the original might have had.
When tested on next-20150508 (675b3fb), it passed my checks
(libva tests, vlc video, glxgears, beignet tests), and didn't
show the missing window title bar problem [0-1] in 3 attempts,
but given the intermittent nature of that I
On Fri, May 08, 2015 at 07:23:42PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently vlv_wait_port_ready() waits for all four lanes on the
appropriate channel. This no longer works on
On Thu, 07 May 2015 16:41:48 +0300
Jani Nikula jani.nik...@linux.intel.com wrote:
On Thu, 07 May 2015, Matt Roper matthew.d.ro...@intel.com wrote:
On Thu, May 07, 2015 at 12:12:18PM +0300, Jani Nikula wrote:
On Thu, 23 Apr 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
[cc'ing the
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
v2: Do forcewake before setting idle frequency (ville)
Update function
Hangcheck tries to peek into request list to see
if the ring was busy or not. But that leads to race
against the list addition in request submission.
And hangcheck saw a ring being idle, when in fact work was
just being submitted.
There is strong desire to keep hangcheck without
locks of any kind
On 05/08/2015 03:59 PM, Damien Lespiau wrote:
On Fri, May 08, 2015 at 01:02:35PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
First attempt at rotated GGTT mapping for the NV12 format.
It compiles and even does not crash on first use. But some parts are
probably
On Fri, May 08, 2015 at 11:07:30AM -0300, Paulo Zanoni wrote:
2015-05-08 4:29 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Thu, May 07, 2015 at 03:23:17PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Let's just steal the crc namespace and add this by default to
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Powergate the PHY lanes when they're not needed. For HDMI all four lanes
are needed always, but for DP we can enable only the needed lanes. And
when the port is not used
On Fri, May 08, 2015 at 01:02:35PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
First attempt at rotated GGTT mapping for the NV12 format.
It compiles and even does not crash on first use. But some parts are
probably too simplistic at the moment and need
On Wednesday 06 May 2015 02:32 PM, Daniel Vetter wrote:
On Tue, May 05, 2015 at 01:12:41PM +0530, Deepak S wrote:
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote:
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote:
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6282
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
= 0 inside this check, as it
appears to be there because the copying (i915_cmd_parser.c:1054)
removes any offset the original might have had.
When tested on next-20150508 (675b3fb), it passed my checks
(libva tests, vlc video, glxgears, beignet tests), and didn't
show the missing window
where cmdparser is disabled, batch_obj is
left dangling
Sorry! Fixed now.
This version also brings exec_start = 0 inside this check, as it
appears to be there because the copying (i915_cmd_parser.c:1054)
removes any offset the original might have had.
When tested on next-20150508 (675b3fb
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Expecting CHV power wells to be just an extended versions of the VLV
power wells, a bunch of commented out power wells were added in
anticipation when Punit folks would
On Friday 08 May 2015 06:49 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 06:24:42PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sometimes (exactly when is a bit unclear)
With commit aaecdf611a05 (drm/i915: Stop gathering error
states for CS error interrupts) we only call i915_handle_error()
on call sites where there is a stuck/hung gpu. So there is
no more need to carry around extra information into dmesg.
Emit one loud bang into dmesg with first hanging ring as
On Fri, May 08, 2015 at 04:19:13PM +0300, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 06:24:42PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently vlv_wait_port_ready() waits for all four lanes on the
appropriate channel. This no longer works on CHV when the unused
lanes may be power gated. So pass in a mask
2015-05-08 4:29 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Thu, May 07, 2015 at 03:23:17PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Let's just steal the crc namespace and add this by default to
igt_pipe_crc_collect_crc() instead of adding more calls to other
The kerneldoc for this newly added parameter was missing from the
original patch. This patch adds the appropriate kerneldoc entry.
Signed-off-by: Todd Previte tprev...@gmail.com
---
include/drm/drm_crtc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_crtc.h
Also treat it as a proper boolean.
Cc: Todd Previte tprev...@gmail.com
Cc: Paulo Zanoni paulo.r.zan...@intel.com
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_edid.c | 8
drivers/gpu/drm/i915/intel_dp.c | 2 +-
On Fri, May 08, 2015 at 06:24:42PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sometimes (exactly when is a bit unclear) DISPLAY_PHY_CONTROL appears to
get corrupted. The values I've
'available' was the name for a variable in the previous version of that
code. Also add the reason why being alloc_size is important: it's
because the result will indeed fit into plane_blocks.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1
Hi all,
New -testing cycle with cool stuff:
- skl plane scaler support (Chandra Kondru)
- enable hsw cmd parser (Daniel and fix from Rebecca Palmer)
- skl dc5/6 support (low power display modes) from SuketuSunil
- dp compliance testing patches (Todd Previte)
- dp link training optimization (Mika
On Fri, May 08, 2015 at 08:19:12PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Powergate the PHY lanes when they're not needed. For HDMI all four lanes
are needed always, but for DP we
So I've not yet went through the entire series; but I'm wondering if its
at all possible to re-use some of this work:
lkml.kernel.org/r/1428453299-19121-1-git-send-email-suka...@linux.vnet.ibm.com
That's for a Power8 HV call that can basically return an array of
values; which on a superficial
On Fri, May 08, 2015 at 08:43:10PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
On Fri, 8 May 2015 08:55:46 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Thu, May 7, 2015 at 9:40 PM, Steven Rostedt rost...@goodmis.org wrote:
Please retry with snd-hda-intel blacklisted. At least last time I
checked that was the only culprit left, i915 is just the messenger
here. The
On Fri, May 08, 2015 at 08:43:12PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to
RPe.
Punit is expecting us to operate GPU between Rpe Rp0. If we drop the
frequency to RPn, punit is
On Fri, 8 May 2015 12:18:10 -0400
Steven Rostedt rost...@goodmis.org wrote:
On Fri, 8 May 2015 12:08:31 -0400
Steven Rostedt rost...@goodmis.org wrote:
Maybe it's my bios still (it is an older box). I'll just block out
compiling in SND_HDA_INTEL, so that it doesn't break my tests (they
Lost in
commit c5ad54cf7dd8922bd1cee2d5871aebf73dc9638e
Author: Joonas Lahtinen joonas.lahti...@linux.intel.com
Date: Wed May 6 14:36:09 2015 +0300
drm/i915: Use partial view in mmap fault handler
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Signed-off-by: Daniel Vetter
From: Ville Syrjälä ville.syrj...@linux.intel.com
Currently the test expects to find 15 stereo 3D modes, however the
number of stereo modes we get from the current kernel EDID parser
is actually 13.
The extra two modes we had previously were GTF modes, which are no
longer getting added by the
On Mon, Apr 27, 2015 at 03:47:37PM -0700, Chandra Konduru wrote:
Skylake nv12 format requires dbuf (aka. ddb) calculations
and programming for each of y and uv sub-planes. Made minor
changes to reuse current dbuf calculations and programming
for uv plane. i.e., with this change, existing
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
New subtests to excercise flips from tiled to tiled and from
linear to tiled frame buffers.
These will catch display programming issues like not preserving the
tiling mode in page flips or not re-programming the watermarks.
v2: Cleanup crc object
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6353
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Fri, 8 May 2015 12:08:31 -0400
Steven Rostedt rost...@goodmis.org wrote:
Maybe it's my bios still (it is an older box). I'll just block out
compiling in SND_HDA_INTEL, so that it doesn't break my tests (they
fail on a WARNING).
Hmm, right after I posted this I triggered the Call Trace
i915_gem_execbuffer_parse returns the original batch_obj on batches
it can't check (currently, chained batches). Don't clear offset
or set I915_DISPATCH_SECURE in this case.
Fixes 17cabf571e50677d980e9ab2a43c5f11213003ae.
Signed-off-by: Rebecca Palmer rebecca_pal...@zoho.com
---
This version
On Thu, May 07, 2015 at 03:15:43PM +0100, Robert Bragg wrote:
I've changed the uapi for configuring the i915_oa specific attributes
when calling perf_event_open(2) whereby instead of cramming lots of
bitfields into the perf_event_attr config members, I'm now
daisy-chaining a
On Fri, May 08, 2015 at 08:43:11PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
It is obsered on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let it enter rc6 with a
high frequency Vnn also remains high.
I
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6354
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Like with every other feature that's not enabled by default we break
runtime pm support way too often by accident because the overall test
coverage isn't great. And it's been almost 2 years since we enabled
the power well code by default
commit bf51d5e2cda5d36d98e4b46ac7fca9461e512c41
Author:
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Friday, May 08, 2015 1:36 AM
To: Konduru, Chandra; Intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko
Subject: Re: [PATCH i-g-t 3/4] igt_kms: Do not reset plane position on
assigning
a fb
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6355
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane.
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sometimes (exactly when is a bit unclear) DISPLAY_PHY_CONTROL appears to
get corrupted. The values I've managed to read from it seem to have some
pattern but vary quite a
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
With recent hardware/firmware there don't appear to be any glitches
on the other PHY when we toggle the cmnreset for the other PHY. So
detangle the cmnlane power wells from
On Tue, Apr 21, 2015 at 5:06 PM, Daniel Stone dan...@fooishbar.org wrote:
On 21 April 2015 at 16:03, Micah Fedke micah.fe...@collabora.co.uk wrote:
+ * drm_open_any_any:
+ *
+ * Literally the worst-named function I've ever written.
And I stand by this. This is really an RFC, partly to find
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Not sure which LDO programming sequence delay should be used for the CHV
PHY, but the spec says that 600ns is Used by default for initial
bringup, and the BIOS seems to use
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6348
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Fri, May 08, 2015 at 11:04:06AM +0530, Sonika Jindal wrote:
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Set up the chv display PHY lane stagger registers according to
Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY v1.04
Signed-off-by: Ville Syrjälä
On (05/08/15 01:27), Konduru, Chandra wrote:
there are no specific steps, happens during boot and every time the screen
goes
unblank. attached dmesg, .config.
OK, I am able reproduce the mismatch scaler id log on HSW system.
Though, this log doesn't affect system functionality, but it
On 8 May 2015 at 11:26, Daniel Martin consume.no...@gmail.com wrote:
Hi,
I've just tested drm-intel-nightly, last commit:
20e7fca drm-intel-nightly: 2015y-05m-07d-16h-16m-10s UTC
integration manifest
and it makes the machine crash as soon as I plug a monitor to the
docking station or
On Thu, May 07, 2015 at 10:44:21PM +, Sanchez, AdolfoX wrote:
Which VBIOS should be used with the Baytrail-I when trying to configure two
local flat panels as eDP
The EMGD VBIOS creates a device_type 0x1004 and the i915 drivers looks for a
device_type=0x1806 so it seems that the EMGD
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
This will be needed for NV12 support.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 8
drivers/gpu/drm/i915/intel_drv.h | 2 +-
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ae551d8..cc2ed60 100644
---
On pe, 2015-05-08 at 12:46 +0100, Chris Wilson wrote:
On Fri, May 08, 2015 at 02:37:39PM +0300, Joonas Lahtinen wrote:
We do not yet support tiled objects bigger than the mappable
aperture size so reject them.
Reported-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Joonas
Adding NV12 90/270 rotation support for primary and sprite planes.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 23 ---
drivers/gpu/drm/i915/intel_sprite.c | 32 +---
2 files changed, 41
In skylake update plane functions, intel_tile_height() is called with
bits_per_pixel instead of pixel_format. Correcting it.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_sprite.c |2 +-
2 files
First attempt to enabling 90/270 rotation for NV12 format using Tvrtko's
recent rotated mapping for NV12.
Calling intel_plane_obj_offset(plane, obj, 1) is causing kernel NULL
pointer reference. Sending early out early for Tvrtko to work on the
issue.
Very first NV12 flip with 90/270 rotation
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6352
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Friday 08 May 2015 10:04 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:43:10PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx
On Friday 08 May 2015 10:09 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:43:12PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between
From: chandra konduru chandra.kond...@intel.com
This patch adds kms_nv12 test case. It covers testing NV12 in
all supported linear/tile-X/tile-Y/tile-Yf tile formats in
0 and 180 orientations. For each tiling format, it tests
various combinations of planes and scaling.
v2:
-Added 90/270 tests
On Friday 08 May 2015 09:35 PM, Ville Syrjälä wrote:
On Fri, May 08, 2015 at 08:19:12PM +0530, Deepak S wrote:
On Friday 10 April 2015 08:51 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Powergate the PHY lanes when they're not needed. For HDMI
We do not yet support tiled objects bigger than the mappable
aperture size so reject them.
Reported-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Joonas Lahtinen joonas.lahti...@linux.intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 5 +
1 file changed, 5 insertions(+)
diff --git
On Fri, May 08, 2015 at 02:37:39PM +0300, Joonas Lahtinen wrote:
We do not yet support tiled objects bigger than the mappable
aperture size so reject them.
Reported-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Joonas Lahtinen joonas.lahti...@linux.intel.com
This still turns the
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Leftover from refactoring and it serves no purpose now.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Just adding the rotated UV plane at the end of the rotated Y plane.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 47 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 1
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
First attempt at rotated GGTT mapping for the NV12 format.
It compiles and even does not crash on first use. But some parts are
probably too simplistic at the moment and need further polish.
Sending out early since Chandra needs this to complete his
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
By providing a start offset into the source array of pages, and returning the
end position in the scatter-gather table, we will be able to append the UV
plane to the rotated mapping in later patches.
Signed-off-by: Tvrtko Ursulin
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
It will be used twice with support for planar NV12.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Do we need this?
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 27 ++-
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6357
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
As we're doing throughout the code, being optimistic that platform n + 1
will mostly reuse the same things as platform n allows us to minimize
the enabling work needed.
This time, it's about the number of WM levels.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
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