Re: [Intel-gfx] [PATCH v3.5 02.5/22] drm/i915: add intel_display_suspend

On Thu, May 21, 2015 at 02:33:31PM +0200, Maarten Lankhorst wrote: > This is a function used to disable all crtc's. This makes it clearer > to distinguish between when mode needs to be preserved and when > it can be trashed. To clarify, when you talk about mode being preserved or trashed here, you

[Intel-gfx] drivers/gpu/drm/i915/i915_gem_gtt.c

I'm not sure what's happened to the drm code in linux-next - it's exploding all over the place. Did someone turn on -Werror without doing anywhere near enough testing? Anyway, I don't know how to fix this i386 build error: drivers/gpu/drm/i915/i915_gem_gtt.c: In function 'gen8_ppgtt_init': driv

Re: [Intel-gfx] [PATCH] drm/i915: Disable idle messaging before ring disable

On Fri, May 22, 2015 at 08:18:46PM +0300, Mika Kuoppala wrote: > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index d934f85..c06dc76 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -53

[Intel-gfx] [PATCH] Fix resume from suspend to RAM on IBM X30

Hi folks, this is re-submitting the intel DVO patch that closes bug #49838, namely that resuming from suspend-to-RAM on the IBM x30 leaves the laptop with a blank screen. See the attached patch for details. Please let me know what else is missing to make this patch go into the kernel. It has bee

[Intel-gfx] [PATCH] Enable dithering on the S6010 notebook and others

Hi folks, the attached patch enables dithering for the Fujitsu S6010 notebook (and others using the ns2501 DVO chip). It also uses explicit programming for *some* of the DVO registers whose functions I revealed by reverse engineering (thus, guesswork). Please let me know what is missing to i

Re: [Intel-gfx] [PATCH 08/12] drm/i915: Add NV12 support to intel_framebuffer_init

>From: Konduru, Chandra >> > >> > Hi Daniel, >> > NV12 programming is documented in bspec under display planes "Plane >> > Planar YUV programming". There it talks about aux_dist which is the >> > distance between y and uv planes expecting uv to be after y. >> >> Bspec talks about wrap-arou

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add 90/270 rotation for NV12 format.

On Fri, May 22, 2015 at 06:07:36PM +, Runyan, Arthur J wrote: > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > > >On Mon, May 18, 2015 at 07:19:19PM +, Runyan, Arthur J wrote: > >> The statement is correct - " the X offset must always be even for > >> YUV422+NV12, > >and th

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add 90/270 rotation for NV12 format.

>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >On Mon, May 18, 2015 at 07:19:19PM +, Runyan, Arthur J wrote: >> The statement is correct - " the X offset must always be even for >> YUV422+NV12, >and the Y offset must be even when rotated 90/270 degrees." > >Hmm. Can you elaborat

[Intel-gfx] Updated drm-intel-testing

Hi all, New -testing cycle with cool stuff: - cpt modeset sequence fixes from Ville - more rps boosting tuning from Chris - S3 support for skl (Damien) - a pile of w/a for bxt from various people - cleanup of primary plane pixel formats (Damien) - a big pile of small patches with fixes and cleanup

[Intel-gfx] [PATCH] drm/i915: Disable idle messaging before ring disable

According to bspec, with ring mode scheduling on gen >= 8, we need to disable ring idle message before writing zero to Ring Buffer Enable. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 2/2] drm/i915: Let hardware keep track of ctx buf read pointer

We initialize the internal read pointer to zero on init/reset, but only the reset will actually zero the write pointer. This means that on module reload we might re-read context status buffers that were written prior reload. It is safest just to let the hardware keep track of the read pointer, so

[Intel-gfx] [PATCH 1/2] drm/i915: Use masked write for Context Status Buffer Pointer

This register needs to be updated with masked writes. Cc: Damien Lespiau Cc: Thomas Daniel Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c

[Intel-gfx] [PATCH 05/21] drm/i915/gtt: Don't leak scratch page on mapping error

Free the scratch page if dma mapping fails. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c61de4a..a608b1b 100644 --- a/d

[Intel-gfx] [PATCH 20/21] drm/i915/gtt: Use nonatomic bitmap ops

There is no need for atomicity here. Convert all bitmap operations to nonatomic variants. Cc: Ville Syrjälä Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c

[Intel-gfx] [PATCH 10/21] drm/i915/gtt: Remove superfluous free_pd with gen6/7

This has slipped in somewhere but it was harmless as we check the page pointer before teardown. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index

[Intel-gfx] [PATCH 11/21] drm/i915/gtt: Introduce fill_page_dma()

When we setup page directories and tables, we point the entries to a to the next level scratch structure. Make this generic by introducing a fill_page_dma which maps and flushes. We also need 32 bit variant for legacy gens. v2: Fix flushes and handle valleyview (Ville) Signed-off-by: Mika Kuoppal

[Intel-gfx] [PATCH 19/21] drm/i915/gtt: One instance of scratch page table/directory

As we use one scratch page for all ppgtt instances, we can use one scratch page table and scratch directory across all ppgtt instances, saving 2 pages + structs per ppgtt. v2: Rebase Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 273 +++-

[Intel-gfx] [PATCH 03/21] drm/i915/gtt: Check va range against vm size

Check the allocation area against the known end of address space instead of against fixed value. v2: Return ENODEV on internal bugs (Chris) Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[Intel-gfx] [PATCH 09/21] drm/i915/gtt: Rename unmap_and_free_px to free_px

All the paging structures are now similar and mapped for dma. The unmapping is taken care of by common accessors, so don't overload the reader with such details. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++- 1 file changed, 15 inserti

[Intel-gfx] [PATCH 15/21] drm/i915/gtt: Fill scratch page

During review of dynamic page tables series, I was able to hit a lite restore bug with execlists. I assume that due to incorrect pd, the batch run out of legit address space and into the scratch page area. The ACTHD was increasing due to scratch being all zeroes (MI_NOOPs). And as gen8 address spac

[Intel-gfx] [PATCH 00/21] ppgtt cleanups / scratch merge (V2)

Hi, I have replaced patch 2 from v1 series with version that preallocates top level pdp structure with 32bit addressing on architectures that have problems with pdp tlb flushes. All issues raised with v1 should be addressed by this series. Ville also noticed that copying scratch structures means

[Intel-gfx] [PATCH 08/21] drm/i915/gtt: Introduce struct i915_page_dma

All our paging structures have struct page and dma address for that page. Add struct for page/dma address pairs and use it to make the setup and teardown for different paging structures identical. Include the page directory offset also in the struct for legacy gens. Rename it to clearly point out

[Intel-gfx] [PATCH 21/21] drm/i915/gtt: Reorder page alloc/free/init functions

Introduce base page handling functions in order of alloc, free, init. No functional changes. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 ++--- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 04/21] drm/i915/gtt: Allow >= 4GB sizes for vm.

We can have exactly 4GB sized ppgtt with 32bit system. size_t is inadequate for this. Signed-off-by: Mika Kuoppala --- drivers/char/agp/intel-gtt.c| 4 ++-- drivers/gpu/drm/i915/i915_debugfs.c | 42 ++--- drivers/gpu/drm/i915/i915_gem.c | 6 +++--- d

[Intel-gfx] [PATCH 06/21] drm/i915/gtt: Remove _single from page table allocator

We are always allocating a single page. No need to be verbose so remove the suffix. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 18/21] drm/i915/gtt: Move scratch_pd and scratch_pt into vm area

Scratch page is part of i915_address_space due to that we have only one of that. Move other scratch entities into the same struct. This is a preparatory patch for having only one instance of each scratch_pt/pd. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 51 +++

[Intel-gfx] [PATCH 01/21] drm/i915/gtt: Mark TLBS dirty for gen8+

When we touch gen8+ page maps, mark them dirty like we do with previous gens. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 13/21] drm/i915/gtt: Use macros to access dma mapped pages

Make paging structure type agnostic *_px macros to access page dma struct, the backing page and the dma address. This makes the code less cluttered on internals of i915_page_dma. v2: Superfluous const -> nonconst removed Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 37

[Intel-gfx] [PATCH 07/21] drm/i915/gtt: Introduce i915_page_dir_dma_addr

The legacy mode mm switch and the execlist context assignment needs dma address for the page directories. Introduce a function that encapsulates the scratch_pd dma fallback if no pd is found. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++ drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 02/21] drm/i915/gtt: Workaround for HW preload not flushing pdps

With BDW/SKL and 32bit addressing mode only, the hardware preloads pdps. However the TLB invalidation only has effect on levels below the pdps. This means that if pdps change, hw might access with stale pdp entry. To combat this problem, preallocate the top pdps so that hw sees them as immutable f

[Intel-gfx] [PATCH 12/21] drm/i915/gtt: Introduce kmap|kunmap for dma page

As there is flushing involved when we have done the cpu write, make functions for mapping for cpu space. Make macros to map any type of paging structure. v2: Make it clear tha flushing kunmap is only for ppgtt (Ville) Cc: Ville Syrjälä Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 16/21] drm/i915/gtt: Pin vma during virtual address allocation

Dynamic page table allocation might wake the shrinker when memory is requested for page table structures. As this happens when we try to allocate the virtual address during binding, our vma might be among the targets for eviction. We should do i915_vma_pin() and do pin early in there like Chris sug

[Intel-gfx] [PATCH 17/21] drm/i915/gtt: Cleanup page directory encoding

Write page directory entry without using superfluous indirect function. Also remove unused device parameter from the encode function. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 19 +-- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/driv

[Intel-gfx] [PATCH 14/21] drm/i915/gtt: Make scratch page i915_page_dma compatible

Lay out scratch page structure in similar manner than other paging structures. This allows us to use the same tools for setup and teardown. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 89 - drivers/gpu/drm/i915/i915_gem_gtt.h | 9 ++

Re: [Intel-gfx] [PATCH 02/20] drm/i915: Force PD restore on dirty ppGTTs

"Barbalho, Rafael" writes: >> -Original Message- >> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >> Sent: Thursday, May 21, 2015 4:08 PM >> To: Mika Kuoppala >> Cc: intel-gfx@lists.freedesktop.org; m...@iki.fi; Barbalho, Rafael >> Subject: Re: [Intel-gfx] [PATCH 02/20] drm/i

[Intel-gfx] [PATCH 02/12] drm/i915/bxt: Enable BXT DSI PLL

From: Shashank Sharma This patch adds new functions for BXT clock and PLL programming. They are: 1. configure_dsi_pll for BXT. This function does the basic math and generates the divider ratio based on requested pixclock, and program clock registers. 2. enable_dsi_pll function. This func

[Intel-gfx] [PATCH 08/12] drm/i915/bxt: DSI disable and post-disable

From: Shashank Sharma This patch contains changes to support DSI disble sequence in BXT. The changes are: 1. BXT specific changes in clear_device_ready function. 2. BXT specific changes in DSI disable and post-disable functions. 3. Add a new function to reset BXT Dphy clock and dividers (bxt_d

[Intel-gfx] [PATCH 00/12] *** MIPI DSI Support for BXT ***

This patch series adds support for MIPI DSI for BXT platform. Support for VBT v3 sequence parsing and programming is needed for panel, backlight enable and control. The same will be added as part of a different patch series. Shashank Sharma (10): drm/i915/bxt: Initialize MIPI for BXT drm/i915/

[Intel-gfx] [PATCH 12/12] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT

DSP CLK_GATE registers are specific to BYT and CHT. Avoid programming the same for BXT platform. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_dsi.c |8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/

[Intel-gfx] [PATCH 11/12] drm/i915/bxt: Modify BXT BLC according to VBT changes

From: Sunil Kamath Latest VBT mentions which set of registers will be used for BLC, as controller number field. Making use of this field in BXT BLC implementation. Also, the registers are used in case control pin indicates display DDI. Adding a check for this. According to Bspec, BLC_PWM_*_2 uses

[Intel-gfx] [PATCH 03/12] drm/i915/bxt: Disable DSI PLL for BXT

From: Shashank Sharma This patch adds two new functions: - disable_dsi_pll. BXT DSI disable sequence and registers are different from previous platforms. - intel_disable_dsi_pll wrapper function to re-use the same code for multiple platforms. It checks platform type and calls appropriat

[Intel-gfx] [PATCH 07/12] drm/i915/bxt: Program Tx Rx and Dphy clocks

From: Shashank Sharma BXT DSI clocks are different than previous platforms. So adding a new function to program following clocks and dividers: 1. Program variable divider to generate input to Tx clock divider (Output value must be < 39.5Mhz) 2. Select divide by 2 option to get < 20Mhz for Tx c

[Intel-gfx] [PATCH 06/12] drm/i915/bxt: DSI enable for BXT

From: Shashank Sharma This patch contains following changes: 1. MIPI device ready changes to support dsi_pre_enable. Changes are specific to BXT device ready sequence. Added check for ULPS mode(No effects on VLV). 2. Changes in dsi_enable to pick BXT port control register. 3. Changes in dsi

[Intel-gfx] [PATCH 10/12] drm/i915/bxt: get DSI pixelclock

From: Shashank Sharma BXT's DSI PLL is different from that of VLV. So this patch adds a new function to get the current DSI pixel clock based on the PLL divider ratio and lane count. This function is required for intel_dsi_get_config() function. Signed-off-by: Shashank Sharma Signed-off-by: Um

[Intel-gfx] [PATCH 09/12] drm/i915/bxt: get_hw_state for BXT

From: Shashank Sharma Pick appropriate port control register (BXT or VLV), based on device. Get the current hw state wrt Mipi port. Signed-off-by: Shashank Sharma Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_dsi.c |7 --- 1 file changed, 4 insertions(+), 3 deletions(-) d

[Intel-gfx] [PATCH 05/12] drm/i915/bxt: DSI encoder support in CRTC modeset

From: Shashank Sharma SKL and BXT qualifies the HAS_DDI() check, and hence haswell modeset functions are re-used for modeset sequence. But DDI interface doesn't include support for DSI. This patch adds: 1. cases for DSI encoder, in those modeset functions and allows a CRTC modeset 2. Adds call to

[Intel-gfx] [PATCH 04/12] drm/i915/bxt: DSI prepare changes for BXT

From: Shashank Sharma This patch modifies dsi_prepare() function to support the same modeset prepare sequence for BXT also. Main changes are: 1. BXT port control register is different than VLV. 2. BXT modeset sequence needs vdisplay and hdisplay programmed for transcoder. 3. BXT can select PIP

[Intel-gfx] [PATCH 01/12] drm/i915/bxt: Initialize MIPI for BXT

From: Shashank Sharma This patch contains following changes: 1. Add BXT MIPI display address base. 2. Call dsi_init from display_setup function. Signed-off-by: Shashank Sharma Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_display.c |

Re: [Intel-gfx] [PATCH intel-gpu-tools 1/3] drmtest: Add non-i915 device open helpers

Daniel, Thanks. I'm working to implement the driver name param and drm_require_driver now. The prime stuff I'll have to familiarize myself with a bit more (and maybe dredge up some hw) but your suggestions sound reasonable enough. -mf On 05/22/2015 02:17 AM, Daniel Vetter wrote: Forgotte

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Enable GTT caching on gen8

On 05/21/2015 11:10 PM, Daniel Vetter wrote: > On Thu, May 21, 2015 at 01:18:44PM -0700, Jesse Barnes wrote: >> On 05/19/2015 10:32 AM, ville.syrj...@linux.intel.com wrote: >>> From: Ville Syrjälä >>> >>> GTT caching was disabled by default on gen8 due to not working with >>> big pages. Some infor

Re: [Intel-gfx] [PATCH] drm/edid: Fix DDC probe for passive DP dongles

On 5/21/2015 1:28 AM, Jani Nikula wrote: On Thu, 21 May 2015, Todd Previte wrote: Passive DP->DVI/HDMI dongles show up to the system as HDMI devices, as they do not have a sink device in them to respond to any AUX traffic. When probing these dongles over the DDC, sometimes they will NAK the f

Re: [Intel-gfx] [PATCH 33/70] drm/i915: Use a separate slab for requests

On 07/04/2015 16:20, Chris Wilson wrote: requests are even more frequently allocated than objects and equally benefit from having a dedicated slab. v2: Rebase Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_dma.c | 12 ++ drivers/gpu/drm/i915/i915_drv.h |

Re: [Intel-gfx] [PATCH] drm/i915: Document IPS restriction with 1 plane on the pipe.

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6455 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

[Intel-gfx] [PATCH i-g-t] kms_rotation_crc: Update rotation direction for kernel changes

From: Tvrtko Ursulin commit 1e8df16778b0d8fd8102b3ee799b028f8f961089 Author: Sonika Jindal Date: Wed May 20 13:40:48 2015 +0530 drm/i915/skl: Swapping 90 and 270 to be compliant with Xrand Changed the rotation direction so IGT needs to be told. Signed-off-by: Tvrtko Ursulin Cc: Ville S

Re: [Intel-gfx] [PATCH v4 00/12] All sort of cdclk stuff

On Fri, 22 May 2015, Jani Nikula wrote: > On Fri, 22 May 2015, Mika Kahola wrote: >> This patch series rebases Ville's original cdclk patch series >> excluding the ones that are already reviewed. >> >> http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html >> >> The patche

Re: [Intel-gfx] [PATCH v4 00/12] All sort of cdclk stuff

On Fri, 22 May 2015, Mika Kahola wrote: > This patch series rebases Ville's original cdclk patch series > excluding the ones that are already reviewed. > > http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html > > The patches are rebased to the latest drm-intel-nightly an

[Intel-gfx] [PATCH v4 11/12] drm/i915: Add IS_BDW_ULX

From: Ville Syrjälä We need to tell BDW ULT and ULX apart. Signed-off-by: Ville Syrjälä v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola Author:Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/

[Intel-gfx] [PATCH v4 07/12] drm/i915: Unify ilk and hsw .get_aux_clock_divider

From: Ville Syrjälä ilk_get_aux_clock_divider() is now a subset of hsw_get_aux_clock_divider() so unify them. Signed-off-by: Ville Syrjälä v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola Author:Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c | 23 +++

[Intel-gfx] [PATCH v4 00/12] All sort of cdclk stuff

This patch series rebases Ville's original cdclk patch series excluding the ones that are already reviewed. http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html The patches are rebased to the latest drm-intel-nightly and while I was doing it I tagged the reviewed-by. Maybe Da

[Intel-gfx] [PATCH v4 02/12] drm/i915: Fix 852GM/GMV cdclk

From: Ville Syrjälä It seems 852GM/GMV uses a different HPLLCC encoding than the other 85x platforms. For 852GM/GMV cdclk is always 133MHz. Try to detect that using the PCI revision (sinc the device ID seems useless for that). I'm not at all sure this is a good idea, but according to the specs it

[Intel-gfx] [PATCH v4 04/12] drm/i915: Warn when cdclk for the platforms is not known

From: Ville Syrjälä Print a warning if we fall through the .get_display_clock_speed() function pointer setup. We end up assuming a 133MHz cdclk which should mean that at least we avoid any 0 deivisions and whatnot. But this could at least help remind people that they have to provide this function

[Intel-gfx] [PATCH v4 06/12] drm/i915: Use cached cdclk value

From: Ville Syrjälä Rather than reading out the current cdclk value use the cached value we have tucked away in dev_priv. Signed-off-by: Ville Syrjälä v2: Rebased to the latest v3: Rebased to the latest Reviewed-by: Mika Kahola Author:Ville Syrjälä --- drivers/gpu/drm/i915/intel_displ

[Intel-gfx] [PATCH v4 03/12] drm/i915: Add cdclk extraction for g33, g965gm and g4x

From: Ville Syrjälä Implement cdclk extraction for g33, 965gm and g4x platforms. The details came from configdb. Sadly there isn't anything there for other gen3/gen4 chipsets. So far I've tested this on one ELK where it gave me a HPLL VCO of 5333 MHz and cdclk of 444 MHz which seems perfectly sa

[Intel-gfx] [PATCH v4 01/12] drm/i915: Fix i855 get_display_clock_speed

From: Ville Syrjälä Actually read the HPLLCC register insted of assuming it's 0. Fix the HPLLCC bit definitions and all the missing ones from the 852GME spec. 852GME, 854 and 855 all seem to match the same HPLLC encoding even though only some of the values are valid is some of the platforms. Si

[Intel-gfx] [PATCH v4 05/12] drm/i915: Cache current cdclk frequency in dev_priv

From: Ville Syrjälä Rather that extracting the current cdclk freuqncy every time someone wants to know it, cache the current value and use that. VLV/CHV already stored a cached value there so just expand that to cover all platforms. Signed-off-by: Ville Syrjälä v2: Rebased to the latest v3: Re

[Intel-gfx] [PATCH v4 09/12] drm/i915: Don't enable IPS when pixel rate exceeds 95%

From: Ville Syrjälä Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate exceeds 95% of the core display clock. Apparently this can cause underruns. There's no similar restriction listed for HSW, so leave that one alone for now. v2: Add pipe_config_supports_ips() (Chris) v3: Compa

[Intel-gfx] [PATCH v4 12/12] drm/i915: BDW clock change support

From: Ville Syrjälä Add support for changing cdclk frequency during runtime on BDW. The procedure is quite a bit different on BDW from the one on HSW, so add a separate function for it. Also with IPS enabled the actual pixel rate mustn't exceed 95% of cdclk, so take that into account when comput

[Intel-gfx] [PATCH v4 8/8] drm/i915: Store max cdclk value in dev_priv

From: Ville Syrjälä Keep the cdclk maximum supported frequency around in dev_priv so that we can verify certain things against it before actually changing the cdclk frequency. For now only VLV/CHV have support changing cdclk frequency, so other plarforms get to assume cdclk is fixed. Signed-off

[Intel-gfx] [PATCH v4 10/12] drm/i915: HSW cdclk support

From: Ville Syrjälä Implement support for changing the cdclk frequency during runtime on HSW. VLV/CHV already have support for this, so we can follow their example for the most part. Only the actual hardware programming differs, the rest is pretty much the same. The pipe pixel rate stuff is hand

Re: [Intel-gfx] [PATCH] drm/i915: Fix IPS related flicker

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6453 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

Re: [Intel-gfx] [PATCH intel-gpu-tools 1/3] drmtest: Add non-i915 device open helpers

Forgotten to add Thomas as the igt maintainer. -Daniel On Fri, May 8, 2015 at 3:03 PM, Daniel Vetter wrote: > On Tue, Apr 21, 2015 at 5:06 PM, Daniel Stone wrote: >> On 21 April 2015 at 16:03, Micah Fedke wrote: >>> + * drm_open_any_any: >>> + * >>> + * Literally the worst-named function I've e

Re: [Intel-gfx] [PATCH] drm/i915: Fix IPS related flicker

On Thu, May 21, 2015 at 12:53:03PM -0700, Rodrigo Vivi wrote: > We cannot let IPS enabled with no plane on the pipe: > > BSpec: "IPS cannot be enabled until after at least one plane has > been enabled for at least one vertical blank." and "IPS must be > disabled while there is still at least one p

Re: [Intel-gfx] [PATCH] drm/i915: Document IPS restriction with 1 plane on the pipe.

On Thu, May 21, 2015 at 01:06:10PM -0700, Rodrigo Vivi wrote: > With this well documented we can remove that FIXME comment. > > We just need to make sure that on primary -> sprite transition there > is no vblank time where ips gets alone on the pipe with absolutelly > no plane. If this happens eve

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Introduce DRM_I915_THROTTLE_JIFFIES

On Thu, May 21, 2015 at 09:01:48PM +0100, Chris Wilson wrote: > As Daniel commented on > > commit b7ffe1362c5f468b853223acc9268804aa92afc8 > Author: Chris Wilson > Date: Mon Apr 27 13:41:24 2015 +0100 > > drm/i915: Free RPS boosts for all laggards > > it is better to be explicit when shar