On Wed, Jun 24, 2015 at 12:04 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Jun 23, 2015 at 07:45:42AM +0200, Sedat Dilek wrote:
I have seen this typo once and added an entry to codespell's dictionary.txt
file.
$ diff -uprN /usr/share/codespell/dictionary.txt.orig
On Wed, Jul 01, 2015 at 04:28:10PM +0100, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
In specific, any resource used with flat/heapless (0x-0xf000)
General State Heap or Intruction State
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
error handling code was broken, resulting in the first path not being
checked correctly. Fix this by
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
error handling code was broken, resulting in the first path not being
checked correctly. Fix this by
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6685
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
Bumping up in case anyone missed this.
-Original Message-
From: Yu, Chan KitX
Sent: Thursday, June 25, 2015 4:49 PM
To: Chris Wilson
Cc: intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] Reason for discontinuing support for Glamor
That clears everything up then. Another
Hi,
On Thu, 2015-07-02 at 09:23 +0200, Daniel Vetter wrote:
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
error handling code was broken,
On Thu, Jul 02, 2015 at 12:21:43AM +0100, Damien Lespiau wrote:
When developing, it's quite annoying that the version changes every
commit, causing the library to be rebuild and everything single binary
re-linked.
Add a config option to skip that.
I remember Ville asking for this feature
On 07/01/2015 05:30 PM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 03:54:55PM +0100, Tvrtko Ursulin wrote:
+static int i915_gem_exec_flush_object(struct drm_i915_gem_object *obj,
+ struct intel_engine_cs *ring,
+ struct
On Wed, Jul 01, 2015 at 10:12:23AM +0300, Abdiel Janulgue wrote:
Ensures that the batch buffer is executed by the resource streamer
v2: Don't skip 115 for the exec flags (Jani Nikula)
v3: Use HAS_RESOURCE_STREAMER macro for execbuf validation (Chris Wilson)
Testcase: igt/gem_exec_params
On Thu, Jul 02, 2015 at 11:42:44AM +0100, Tvrtko Ursulin wrote:
I am not super familiar with low level mapping business. But it
looks correct to me. Just one question would be if there are any
downsides to WC mapping? If in the read case it would be any
advantage not to ask for WC?
Read-side
From: John Harrison john.c.harri...@intel.com
Various projects desire a mechanism for managing dependencies between
work items asynchronously. This can also include work items across
complete different and independent systems. For example, an
application wants to retreive a frame from a video in
On 2 July 2015 at 00:21, Damien Lespiau damien.lesp...@intel.com wrote:
When developing, it's quite annoying that the version changes every
commit, causing the library to be rebuild and everything single binary
everything → every
re-linked.
Add a config option to skip that.
I remember
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6686
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Thu, Jul 02, 2015 at 11:31:57AM +0300, Ville Syrjälä wrote:
On Thu, Jul 02, 2015 at 12:21:43AM +0100, Damien Lespiau wrote:
When developing, it's quite annoying that the version changes every
commit, causing the library to be rebuild and everything single binary
re-linked.
Add a
On 7/1/2015 6:06 PM, Emil Velikov wrote:
Hi Michel,
Although I cannot comment on the exact implementation I can give you
general some tips which you might find useful.
Hi Emil,
On 1 July 2015 at 16:28, Michel Thierry michel.thie...@intel.com wrote:
Gen8+ supports 48-bit virtual addresses,
Francisco,
I have had a quick chat here with people and we are good to not upstream
our version of the MOCS. We will handle the updates that we require for
Android separately from the upstream kernel.
Thanks,
Peter.
On Wed, 1 Jul 2015, Daniel Vetter wrote:
On Wed, Jul 01, 2015 at
On 07/01/2015 05:19 PM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 04:06:49PM +0100, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c5349fa..6045749 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
Since the introduction of igt_stats and its usage in gem_exec_nop, we
need to link the tests against libm. My rebasing bot complained when
linking gem_exec_nop:
lib/igt_stats.c:492: undefined reference to `sqrt'
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
tests/Makefile.am | 2
On 07/01/2015 10:25 AM, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This will cover prime
On 07/02/2015 12:00 PM, Chris Wilson wrote:
+ /* This is a slow read/write as it tries to read from
+* and write to user memory which may result into page
+* faults
+*/
+ ret = slow_user_access(dev_priv-gtt.mappable,
On Thu, Jul 02, 2015 at 10:37:56AM +0100, Tvrtko Ursulin wrote:
On 07/01/2015 05:19 PM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 04:06:49PM +0100, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/i915_dma.c
b/drivers/gpu/drm/i915/i915_dma.c
index c5349fa..6045749 100644
---
On Thu, Jul 02, 2015 at 10:30:43AM +0100, Tvrtko Ursulin wrote:
Well.. I the meantime why duplicate it when
i915_gem_validate_context does i915_gem_context_get and deferred
create if needed. I don't see the downside. Snippet from above
becomes:
ring = dev_priv-ring[HAS_BLT(dev) ? BCS :
Hi Linus -
I hear Dave is on vacation, so please pull this first batch of Intel
fixes for v4.2 directly. (Dave, do correct me if I'm wrong!)
Almost all of it is regression fixes all around, with cc: stable, and
then there's Ander's fix for one of the warnings you reported. We're
still working
Ville noticed that the PLL HW readout code parsed the fractional
divider value as if the fractional divider was always enabled. This may
result in a port clock state check mismatch if the preceeding modeset
disabled the fractional divider, but left a non-zero divider value in
the register.
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
error handling code was broken, resulting in the first path not being
checked correctly. Fix this by
On Thu, Jul 02, 2015 at 02:01:56PM +0100, John Harrison wrote:
On 02/07/2015 12:54, Chris Wilson wrote:
On Thu, Jul 02, 2015 at 12:09:59PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Various projects desire a mechanism for managing dependencies
Hi,
On 2 Jul 2015, at 2:16 pm, Daniel Vetter daniel.vet...@ffwll.ch wrote:
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
error handling
2015-07-01 17:44 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Wed, Jul 01, 2015 at 05:15:21PM -0300, Paulo Zanoni wrote:
Looks much cleaner with the split.
+void intel_fbc_cleanup_cfb(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if
On Thu, Jul 02, 2015 at 12:27:42PM +0100, Tvrtko Ursulin wrote:
On 07/02/2015 12:00 PM, Chris Wilson wrote:
+ /* This is a slow read/write as it tries to read from
+ * and write to user memory which may result into page
+ * faults
+ */
+ ret
On Thu, Jul 02, 2015 at 10:39:05AM -0300, Paulo Zanoni wrote:
2015-07-01 17:44 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Wed, Jul 01, 2015 at 05:15:21PM -0300, Paulo Zanoni wrote:
Looks much cleaner with the split.
+void intel_fbc_cleanup_cfb(struct drm_device *dev)
+{
+
On 07/02/2015 02:37 PM, Ville Syrjälä wrote:
On Tue, Jun 30, 2015 at 10:06:27AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
We had three failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls
drm_framebuffer_remove, which grabs the struct
I just remembered that those Makefile.sources files where also
included by the Android build system, so we can't use automake's
conditionals in there.
So, we want to use GNU make's one. Unfortunately, after all those years,
GNU automake still doesn't do antying useful with GNU make's ifeq:
On Tue, Jun 30, 2015 at 10:06:27AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
We had three failure modes here:
1.
Deadlock in intelfb_alloc failure path where it calls
drm_framebuffer_remove, which grabs the struct mutex and intelfb_create
(caller of
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
error handling code was broken, resulting in the first path not being
checked correctly. Fix this by
On Thu, Jul 02, 2015 at 12:09:59PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Various projects desire a mechanism for managing dependencies between
work items asynchronously. This can also include work items across
complete different and independent
On Thu, Jul 02, 2015 at 12:54:27PM +0100, Chris Wilson wrote:
However, that equally applies to the existing request-seqno. That can
also be assigned on submission so that it always an ordered timeline, and
so can be used internally or externally.
Hmm, we need to preallocate seqno space for the
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6687
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On 02/07/2015 12:54, Chris Wilson wrote:
On Thu, Jul 02, 2015 at 12:09:59PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Various projects desire a mechanism for managing dependencies between
work items asynchronously. This can also include work items
On Thu, Jul 02, 2015 at 02:53:45PM +0100, Michel Thierry wrote:
I would have just exposed setting the flag on the execobject. That way you
still have existing userspace safe by default, can set a
bufmgr-level flag to enable 48bit support by default and then
individually turn off 48bit support
Clarify that audio enable/disable sequences are part of the modeset
sequence.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_audio.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
Add an overview of the drm/i915 hotplug handling.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
Documentation/DocBook/drm.tmpl | 5 +
drivers/gpu/drm/i915/intel_hotplug.c | 39
2 files changed, 44 insertions(+)
diff --git
On Tue, Jun 16, 2015 at 01:39:40PM +0300, Abdiel Janulgue wrote:
Adds support for enabling the resource streamer on the legacy
ringbuffer for HSW and GEN8.
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
I've run a few
On Thu, Jul 02, 2015 at 10:33:27AM -0300, Paulo Zanoni wrote:
2015-07-01 17:38 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Wed, Jul 01, 2015 at 05:15:20PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We want to move the FBC code out of i915_gem_stolen.c,
On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote:
Ville noticed that the PLL HW readout code parsed the fractional
divider value as if the fractional divider was always enabled. This may
result in a port clock state check mismatch if the preceeding modeset
disabled the fractional
On 7/2/2015 8:21 AM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 04:28:10PM +0100, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
OUT_BATCH(0);
OUT_BATCH(mocs_wb 16);
/* Surface state
Hi,
not sure if another reaction from me is required, but in case there is:
The patch as quoted below LGTM now, so unless Ville vetoes because of
his suggestion (see below) I think this is ready for inclusion in 4.2.
Thanks,
Lukas
On Tue, Jun 30, 2015 at 10:06:27AM +0100, Tvrtko Ursulin wrote:
2015-07-01 17:38 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Wed, Jul 01, 2015 at 05:15:20PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
We want to move the FBC code out of i915_gem_stolen.c, but that code
directly adds/removes stolen memory nodes. Let's
Daniel fixed the same issue for crtc states in
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
Follow suite.
Cc: Daniel Stone dani...@collabora.com
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6688
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Thu, Jul 02, 2015 at 05:43:21PM +0300, Jani Nikula wrote:
Signed-off-by: Jani Nikula jani.nik...@intel.com
25 code looks correct, but haven't crosschecked with the new OpRegion
spec, so Acked-by: Chris Wilson ch...@chris-wilson.co.uk
The others are just small cleanups, so
Reviewed-by: Chris
On Thu, Jul 02, 2015 at 02:27:30PM +0100, Daniel Stone wrote:
Hi,
On 2 Jul 2015, at 2:16 pm, Daniel Vetter daniel.vet...@ffwll.ch wrote:
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
On Wed, Jun 24, 2015 at 2:59 AM, Maarten Lankhorst
maarten.lankho...@linux.intel.com wrote:
This change updates the old_fb pointer only after acquiring the plane lock,
if there are no properties the fb cannot have been changed either, so
this works out correctly.
Found in a discussion with
This must be done in advance, and during crtc_disable all scalers
can be force disabled.
This means intel_atomic_setup_scalers is only called in 1 place now,
during crtc_check.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_atomic.c | 14
On Thu, Jul 2, 2015 at 9:16 PM, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
In
commit 9f658b7b62e7aefc1ee067136126eca3f58cabfd
Author: Daniel Stone dani...@collabora.com
Date: Fri May 22 13:34:45 2015 +0100
drm/crtc_helper: Replace open-coded CRTC state helpers
error handling code
On Thu, Jul 2, 2015 at 10:33 PM, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
Transitional drivers might not have all the state frobbing lined up
yet. But since the initial code has been merged a lot more state was
added, so we really need this.
Cc: Daniel Stone dani...@collabora.com
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 71e87abdcae7..c4756a2d77bb 100644
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
Follow the correct pipe vs port disable sequence for the PCH LVDS
ports, ie. disable the port after the pipe.
Other PCH port were already converted in the following commits:
1ea56e269e136544c0a76dc831c5edc27c47cb3c drm/i915: Disable CRT port
Make it easier to handle the extended didl. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 50 +++
1 file changed, 39 insertions(+), 11 deletions(-)
diff --git
Inluding extended didl and cpdl fields
Present since opregion version 3.0.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
On 02/07/2015 14:22, Chris Wilson wrote:
On Thu, Jul 02, 2015 at 02:01:56PM +0100, John Harrison wrote:
On 02/07/2015 12:54, Chris Wilson wrote:
On Thu, Jul 02, 2015 at 12:09:59PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Various projects desire a
Transitional drivers might not have all the state frobbing lined up
yet. But since the initial code has been merged a lot more state was
added, so we really need this.
Cc: Daniel Stone dani...@collabora.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
This allows us to get rid of the set_init_power in
modeset_update_crtc_domains. The state should be sanitized enough
after setup_hw_state to not need the init power.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 76
Perform a full readout of the state by making sure the mode is set
up correctly atomically.
Also there was a small memory leak by doing the memset, fix this
by calling __drm_atomic_helper_crtc_destroy_state first.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
Now that there's only a single path for all atomic updates we can call
intel_(pre/post)_plane_update from intel_atomic_commit directly. This
makes the intention more clear.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 17
No point in applying vblank evasion if there's nothing to evade.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
Calculate all state using a normal transition, but afterwards fudge
crtc-state-active back to its old value. This should still allow
state restore in setup_hw_state to work properly.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90396
Signed-off-by: Maarten Lankhorst
And get rid of things that are no longer true. This function is only
used for forcing a modeset when encoder properties are changed.
All the existing state is fine in this case, only setting mode_changed
will force a full recalculation here, and take all the state needed.
The previous commit
Huzzah! \o/
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_params.c | 5 -
drivers/gpu/drm/i915/intel_atomic.c | 123
This can only fail because of a bug in the code.
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 15 +--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
This should fix suspend on newer platforms.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
This is pending on fixing Daniel Stone's black laptop screen bug.
I think I understand what is causing his black screen, but I'm not
completely sure. He'll test it on monday, but I want to throw this
online for more time to review.
My bet's on 'rework primary plane stuff slightly'. If this is the
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 34d756250c76..3de855aeb2c4 100644
---
Use the atomic state instead, this allows removing plane_config
from the crtc after the full hw readout is completed.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_fbdev.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
Make sure the primary plane is set up correctly. This is done by
setting plane_state-src and plane_state-crtc.
All non-primary planes get disabled. I fear this may trigger
triggers Daniel Stone's black screen bug, so calls to
intel_update_sprite_watermarks may have to be removed.
Signed-off-by:
Instead of all the ad-hoc updating, duplicate the old state first before
reading out the hw state, then restore it.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
This can be a separate case from mode_changed, when connectors stay the
same but only the mode is different. Drivers may choose to implement specific
optimizations to prevent a full modeset for this case.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Maarten Lankhorst
Now that we read out the full atomic state we can force fastboot without
hacks. The only thing that we have to worry about is preventing unneeded
modesets. This can be easily done by calculating if the new state matches
the old state, with exception for pfit and pipe size. Because the original
This shouldn't be explicitly required here.
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 7 ---
1 file changed, 7 deletions(-)
diff --git
Instead of doing ad-hoc checks we already have a way of checking
if the state is compatible or not. Use this to force a modeset.
Only during modesets, or with PIPE_CONFIG_QUIRK_INHERITED_MODE
we should check if a full modeset is really needed.
Fastboot will allow the adjust parameter to ignore
2015-06-30 20:42 GMT-03:00 Rodrigo Vivi rodrigo.v...@intel.com:
By Spec we should only mask memup and hotplug detection
for hardware tracking cases. However we always masked
LPSP because with power well always enabled on audio
PSR was never being activated and residency was always
zeroed.
Adding support for did2, or the extended support display devices ID
list, increases the total to 15.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6693
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Wed, Jul 01, 2015 at 02:52:45PM +0200, Patrik Jakobsson wrote:
[...]
--- a/defs.h
+++ b/defs.h
@@ -266,6 +266,13 @@ struct tcb {
int u_error;/* Error code */
long scno; /* System call number */
long u_arg[MAX_ARGS]; /* System call arguments */
On Thu, Jun 25, 2015 at 03:40:00PM +0100, Dave Gordon wrote:
intel_guc_fwif.h contains the subset of the GuC interface that we
will need for submission of commands through the GuC. These MUST
be kept in sync with the definitions used by the GuC firmware, and
updates to this file will (or
CHV/BSW supports DeGamma color correction feature, which linearizes all
the non-linear color values. This will be applied before Color
Transformation.
This patch does the following:
1. Adds the core function to program DeGamma correction values for
CHV/BSW platform
2. Adds DeGamma correction
This patch adds new structures in DRM layer for Palette color correction.
These structures will be used by user space agents to configure
appropriate number of samples and Palette LUT for a platform.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Kausal Malladi
Color Manager framework defines a color correction property for color
space transformation and Gamut mapping. This property called CTM (Color
Transformation Matrix).
This patch adds a new structure in DRM layer for CTM color correction.
This structure will be used by all user space agents to
CHV/BSW supports Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into CGM (Color Gamut Mapping) registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
CHV/BSW platform
2. Adds CSC correction macros/defines
drm_property_replace_global_blob() is getting used by many wrapper
functions to replace an existing blob with new values. Because this
function was static, modules are forced to create wrapper functions in
same file. Exporting this function will remove need for such wrapper
functions.
This patch
CHV/BSW platform supports various Gamma correction modes, which are:
1. Legacy 8-bit mode
2. 10-bit CGM (Color Gamut Mapping) mode
This patch does the following:
1. Adds the core function to program Gamma correction values for CHV/BSW
platform
2. Adds Gamma correction macros/defines
From: Matt Roper matthew.d.ro...@intel.com
The intel_atomic_check() function had some simple testing to make
sure that an atomic update isn't updating more than one CRTC at a time.
The logic assumed that a plane was always being updated, so it figured
out the nuclear pipe from the first plane it
2015-6-29 下午3:58於 Jani Nikula jani.nik...@linux.intel.com寫道：
On Sat, 27 Jun 2015, Raymond Yau superquad.vort...@gmail.com wrote:
Shall we move or cc this discussion on audio driver side to ALSA
ML?
Oops I thought I had cc'ed these patches to alsa-devel as well when I
sent them.
On Wed, Jul 01, 2015 at 02:52:47PM +0200, Patrik Jakobsson wrote:
[...]
--- a/drm.c
+++ b/drm.c
@@ -35,6 +35,9 @@
#define DRM_MAX_NAME_LEN 128
+extern int drm_i915_decode_number(struct tcb *tcp, unsigned int arg);
Please rename arg to code, and ...
+extern int drm_i915_ioctl(struct
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6696
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Color Management is an extension to Kernel display framework. It allows
abstraction of hardware color correction and enhancement capabilities by
virtue of DRM properties.
This patch initializes color management framework by :
1. Introducing new pointers in DRM mode_config structure to
carry
NOTE: Re-sending the same series for more feedback, as we realized the mails
didn't reach the dri-devel and intel-gfx lists because of some problem.
This patch set adds Color Manager implementation in DRM layer. Color Manager is
an extension in DRM framework to support color
The DRM color management framework is targeting various hardware
platforms and drivers. Different platforms can have different color
correction and enhancement capabilities.
A commom user space application can query these capabilities using the
DRM property interface. Each driver can fill this
This patch does the following:
1. Adds new files intel_color_manager(.c/.h)
2. Attaches color properties to CRTC while initialization
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Kausal Malladi kausal.mall...@intel.com
---
drivers/gpu/drm/i915/Makefile |
This patch adds atomic set property interface for Intel CRTC. This
interface will be used to set color correction DRM properties.
Signed-off-by: Shashank Sharma shashank.sha...@intel.com
Signed-off-by: Kausal Malladi kausal.mall...@intel.com
---
drivers/gpu/drm/i915/intel_atomic.c | 11
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