From: Thulasimani,Sivakumar sivakumar.thulasim...@intel.com
Update the hotplug documentation to explain that hotplug storm
is not expected for Display port panels and hence is not handled
in current code.
v2: update the statements as recommended by Daniel
Signed-off-by: Sivakumar Thulasimani
Hello Arun Siluvery,
The patch 9e00084750c0: drm/i915: Update
WaFlushCoherentL3CacheLinesAtContextSwitch from Jul 3, 2015, leads
to the following static checker warning:
drivers/gpu/drm/i915/intel_lrc.c:1188 gen8_init_indirectctx_bb()
warn: unsigned 'index' is never less than
On 7/10/2015 1:34 AM, Daniel Vetter wrote:
Instead of trying to deal with this complexity we'll simply require
that the dmc firmware is available for runtime pm support. We do that
by not releasing the rpm reference we acquire when starting the
firmware loader work. Note that since we hold a
On Thu, Jul 09, 2015 at 11:44:29PM +0200, Daniel Vetter wrote:
Just so I have a user for this macro.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Ville Syrjälä ville.syrj...@linux.intel.com
With DPIO powergating active the DPLL can't be accessed unless
something else is keeping the common lane in the channel on.
That means the PPS kick procedure could fail to enable the PLL.
Power up some data lanes to force the common lane to power
On 7/10/2015 1:34 AM, Daniel Vetter wrote:
Grabbing a runtime pm reference with intel_runtime_pm_get will only
prevent device D3. But dmc firmware is required even earlier (namely
for the skl power well 2).
Hence we need to grab a rpm reference higher up in the hierarchy. For
simplicity just
On Thu, Jul 09, 2015 at 07:36:16PM +1000, Dave Airlie wrote:
Please just use
#ifdef HAS_DIRTYTRACKING_ROTATION
avoids the pain of versions.
Thanks, amended and pushed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
Intel-gfx
On Thu, Jul 09, 2015 at 05:19:27PM +0100, Michel Thierry wrote:
On 7/7/2015 4:15 PM, Michel Thierry wrote:
There are some allocations that must be only referenced by 32-bit
offsets. To limit the chances of having the first 4GB already full,
objects not requiring this workaround use
On Tue, Jul 07, 2015 at 04:14:45PM +0100, Michel Thierry wrote:
These are the rebased patches, after Mika's final ppgtt clean-up series landed
(it relies in the macros added) and Akash review comments.
In order expand the GPU address space, a 4th level translation is added, the
Page Map
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
and having VGA mode enabled causes some problems
On Wed, Jul 08, 2015 at 03:11:36AM +0300, Dmitry V. Levin wrote:
On Mon, Jul 06, 2015 at 04:40:24PM +0200, Gabriel Laskar wrote:
On Mon, 6 Jul 2015 12:35:52 +0200, Patrik Jakobsson wrote:
On Fri, Jul 03, 2015 at 03:36:09AM +0300, Dmitry V. Levin wrote:
On Wed, Jul 01, 2015 at 02:52:47PM
On Fri, Jul 10, 2015 at 02:36:38PM +0200, Patrik Jakobsson wrote:
On Wed, Jul 08, 2015 at 03:11:36AM +0300, Dmitry V. Levin wrote:
On Mon, Jul 06, 2015 at 04:40:24PM +0200, Gabriel Laskar wrote:
[...]
Anyway, SYS_FUNC(ioctl) is a bit complicated, and the handling of the
fallbacks on
VBT version 196 increased the size of common_child_dev_config. The parser
code assumed that the size of this structure would not change.
So now, instead of checking for smaller size, check that the VBT entry is
not too large and memcpy only child_dev_size amount of data, leaving any
trailing
These are required for SKL PV.
I tested these on SNB and SKL.
Antti Koskipaa (2):
drm/i915: Allow parsing of variable size child device entries from VBT
drm/i915: Per-DDI I_boost override
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_bios.c | 30
An OEM may request increased I_boost beyond the recommended values
by specifying an I_boost value to be applied to all swing entries for
a port. These override values are specified in VBT.
v2: rebase and remove unused iboost_bit variable
Issue: VIZ-5676
Signed-off-by: Antti Koskipaa
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We do the exact same steps around the disp2d/pipe A power well
enable/disable on VLV and CHV. Refactor the shared
Hi Patrik,
Please do Cc the patch author and reviewer when finding a regression,
they are superb candidates for the review, especially when they are busy
rewriting the display code.
On Wed, Jul 08, 2015 at 03:31:52PM +0200, Patrik Jakobsson wrote:
Watermark calculations depend on the
On ma, 2015-07-06 at 14:44 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Since
commit e62925567c7926e78bc8ca976cde5c28ea265a49
Author: Vandana Kannan vandana.kan...@intel.com
Date: Wed Jul 1 17:02:57 2015 +0530
drm/i915/bxt: BUNs
From: Dhanya dhanya@intel.com
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma supported.
Signed-off-by: Dhanya dhanya@intel.com
---
tests/Makefile.sources | 3 +
tests/kms_color.c | 639 +
On Fri, Jul 10, 2015 at 02:10:54PM +0300, Antti Koskipaa wrote:
VBT version 196 increased the size of common_child_dev_config. The parser
code assumed that the size of this structure would not change.
So now, instead of checking for smaller size, check that the VBT entry is
not too large and
On Mon, Jun 29, 2015 at 3:48 AM, Paul Gortmaker
paul.gortma...@windriver.com wrote:
[Re: [Intel-gfx] [v3 0/7] Crystalcove (CRC) PMIC based panel and pwm control]
On 26/06/2015 (Fri 20:47) Ville Syrjälä wrote:
On Fri, Jun 26, 2015 at 06:31:37PM +0200, Daniel Vetter wrote:
On Fri, Jun 26,
On ke, 2015-07-08 at 15:07 +0530, Kannan, Vandana wrote:
On 7/6/2015 5:14 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Since
commit e62925567c7926e78bc8ca976cde5c28ea265a49
Author: Vandana Kannan vandana.kan...@intel.com
Date:
On 7/10/2015 10:39 AM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:45PM +0100, Michel Thierry wrote:
These are the rebased patches, after Mika's final ppgtt clean-up series landed
(it relies in the macros added) and Akash review comments.
In order expand the GPU address space, a 4th
On Fri, Jul 10, 2015 at 04:02:53PM +0530, Dhanya Pillai wrote:
From: Dhanya dhanya@intel.com
This patch will verify color correction capability of a display driver.
Gamma/CSC/De-gamma supported.
Signed-off-by: Dhanya dhanya@intel.com
---
tests/Makefile.sources | 3 +
From gen7, the platform can support fb of size 3x3.
Adding this check for gen along with fb width height.
Note: IVB is gen7 but its not clear if it can support width 3 and
height 3.
This patch has been tested in Android environment.
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
---
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The pipe A power well is the disp2d well on CHV and pipe B and C wells
don't even exist. Thereforce we can remove the
On 10/07/2015 09:25, Dan Carpenter wrote:
Hello Arun Siluvery,
The patch 9e00084750c0: drm/i915: Update
WaFlushCoherentL3CacheLinesAtContextSwitch from Jul 3, 2015, leads
to the following static checker warning:
drivers/gpu/drm/i915/intel_lrc.c:1188 gen8_init_indirectctx_bb()
On Fri, Jul 10, 2015 at 12:22:51PM +0100, Damien Lespiau wrote:
Hi Patrik,
Please do Cc the patch author and reviewer when finding a regression,
they are superb candidates for the review, especially when they are busy
rewriting the display code.
Hmm, I figured they would be picked up from
On 7/1/2015 6:12 PM, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 02:50:33PM +0300, Ville Syrjälä wrote:
On Tue, Jun 30, 2015 at 12:13:37PM +0200, Daniel Vetter wrote:
On Mon, Jun 29, 2015 at 08:08:27PM +0300, Ville Syrjälä wrote:
On Mon, Jun 29, 2015 at 07:56:05PM +0300, Ville Syrjälä
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6743
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6746
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On 06/07/15 16:41, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 04:33:05PM +0200, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 02:16:54PM +0100, Dave Gordon wrote:
On 06/07/15 13:38, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
On 03/07/15 16:42, Chris
Arun Siluvery arun.siluv...@linux.intel.com writes:
This patch only enables support for Gen9, the actual WA will be
initialized in subsequent patches.
The WARN that we use to warn user if WA batch support is not available
for a particular Gen is replaced with DRM_ERROR as warning here
On 09/07/2015 19:47, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 06:03:18PM +0100, Tomas Elf wrote:
This patch series introduces the following features:
* Feature 1: TDR (Timeout Detection and Recovery) for gen8 execlist mode.
* Feature 2: Watchdog Timeout (a.k.a media engine reset) for gen8.
On 10/07/2015 16:24, Tomas Elf wrote:
On 09/07/2015 19:47, Chris Wilson wrote:
On Mon, Jun 08, 2015 at 06:03:18PM +0100, Tomas Elf wrote:
This patch series introduces the following features:
* Feature 1: TDR (Timeout Detection and Recovery) for gen8 execlist
mode.
* Feature 2: Watchdog
On Fri, Jul 10, 2015 at 04:21:27PM +0300, Ville Syrjälä wrote:
On Fri, Jul 10, 2015 at 02:18:57PM +0100, Damien Lespiau wrote:
On Fri, Jul 10, 2015 at 04:09:42PM +0300, Imre Deak wrote:
On ma, 2015-07-06 at 14:44 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 6/29/2015 5:55 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV don't use the DPLL with DSI, so just clear out the DPLL state
from the pipe_config in
From: Deepak S deepa...@intel.com
Currently we update the freq before masking the interrupts, which can
allow new interrupts to occur before the frequency has changed. These
extra interrupts might waste some cpu cycles. This patch corrects
this by masking interrupts prior to updating the
From: Tim Gore tim.g...@intel.com
In function igt_set_stop_rings, the test
igt_assert_f(flags == 0 || current == 0, ..
will fail if we are trying to force a hang but the
STOP_RINGS_ALLOW_BAN or STOP_RINGS_ALLOW_ERROR bit is set.
With the introduction of per ring resets in the driver
(in
On Fri, Jul 10, 2015 at 04:09:42PM +0300, Imre Deak wrote:
On ma, 2015-07-06 at 14:44 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Since
commit e62925567c7926e78bc8ca976cde5c28ea265a49
Author: Vandana Kannan vandana.kan...@intel.com
On Fri, Jul 10, 2015 at 02:18:57PM +0100, Damien Lespiau wrote:
On Fri, Jul 10, 2015 at 04:09:42PM +0300, Imre Deak wrote:
On ma, 2015-07-06 at 14:44 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Since
commit
From: Tim Gore tim.g...@intel.com
The tests for context banning fail when the gpu scheduler
is enabled. The test causes a hang (using an infinite loop
batch) and then queues up some work behind it on both the
hanging context and also on a second good context. On
the good context it queues up 2
Hello,
We launched Intel GPU Tools on 6 platforms: Skylake-Y, Braswell-M,
Broadwell-U, Baytrail M and T, Haswell-ULT to validate kernel 4.1 tag
drm-intel-testing-2015-07-03.
Test Environment:
Kernel 4.1 from git://anongit.freedesktop.org/drm-intel tag
These patches enabled Pooled EU support for BXT, they are implemented
by Armin Reese. I am sending these patches in its current form for comments.
These patches modify Golden batch to have a set of modification values
where we can change the commands based on Gen. The commands to enable
Pooled EU
From: Armin Reese armin.c.re...@intel.com
Golden context batch buffers now contain a set of offsets
at which contents can optionally be modified. This allows
the driver to customize the GC batch for various chipsets
in a GEN family.
v1 - Originally, the i915 driver was only allowed to
insert
From: Armin Reese armin.c.re...@intel.com
The pooled EU feature for BXT will be enabled by the GEN9
golden context BB. Pooling EUs allows more execution units
to be available for rendering operations and should result
in improved performance. The golden context batch buffer
is used to enable
Just so I have a user for this macro.
v2: Use the right macro - somehow I thought gcc should scream at me,
but list_for_each isn't really typesafe unfortunately. Spotted by
Ville.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
From: Peter Antoine peter.anto...@intel.com
This change adds the programming of the MOCS registers to the gen 9+
platforms. The set of MOCS configuration entries introduced by this
patch is intended to be minimal but sufficient to cover the needs of
current userspace - i.e. a good set of
On Fri, Jul 10, 2015 at 01:50:23PM +0530, Animesh Manna wrote:
On 7/10/2015 1:34 AM, Daniel Vetter wrote:
Instead of trying to deal with this complexity we'll simply require
that the dmc firmware is available for runtime pm support. We do that
by not releasing the rpm reference we acquire
On 10/07/2015 16:52, Mika Kuoppala wrote:
Arun Siluvery arun.siluv...@linux.intel.com writes:
This patch only enables support for Gen9, the actual WA will be
initialized in subsequent patches.
The WARN that we use to warn user if WA batch support is not available
for a particular Gen is
On Fri, Jul 10, 2015 at 01:42:09PM +0530, Animesh Manna wrote:
On 7/10/2015 1:34 AM, Daniel Vetter wrote:
Grabbing a runtime pm reference with intel_runtime_pm_get will only
prevent device D3. But dmc firmware is required even earlier (namely
for the skl power well 2).
Hence we need to
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6726
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6727
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
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