On Thu, Jul 23, 2015 at 09:38:46AM +0200, Daniel Vetter wrote:
[...]
On Thu, Jul 23, 2015 at 9:31 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
[...]
Shobhit Kumar (8):
[...]
pwm: crc: Add Crystalcove (CRC) PWM driver
Would you mind removing this from your branch? I ended up manually
Hi,
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled status should be
set on demand rather than polled. That is, there should not be a need for a
'signaled' function to be
Set active_changed to force a modeset if the panel fitter's force
enabled.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 82 +++-
drivers/gpu/drm/i915/intel_display.c | 3 ++
2 files changed, 27
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_crt.c | 2 -
drivers/gpu/drm/i915/intel_display.c | 79
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_dvo.c | 2 -
This is handled by the atomic core now, no need to check this for ourself.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git
Instead of allocating pipe_config on the stack use the old crtc_state,
it's only going to freed from this point on.
All crtc's encoders are now only checked once during modeset.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 118
-EDEADLK has special meaning in atomic, but get_fence may call
i915_find_fence_reg which can return -EDEADLK.
This has special meaning in the atomic world, so convert the error
to -EBUSY for this case.
Changes since v1:
- Add comment in the code.
Signed-off-by: Maarten Lankhorst
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 7 --
drivers/gpu/drm/i915/intel_dp_mst.c | 45 +++-
2 files changed, 44 insertions(+), 8 deletions(-)
diff --git
Now that everything's atomic, checking encoder-base.crtc is enough.
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git
The rest will be a noop anyway, since without modeset there will be
no updated dplls and no modeset state to update.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30 +++---
1 file changed, 7 insertions(+),
There are no more users, byebye!
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 37 +---
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 1 insertion(+), 37 deletions(-)
diff --git
This patch series depends on:
drm/atomic: Update legacy DPMS state during modesets, v3.
for the following 2 patches:
drm/i915: Remove connectors_active.
drm/i915: Only update mode related state if a modeset happened.
Mixed bag of fixes for -next now that the first merge happened.
Patch series
On Mon, Jul 27, 2015 at 01:07:37PM +0200, Maarten Lankhorst wrote:
Op 27-07-15 om 09:53 schreef Daniel Vetter:
On Wed, Jul 22, 2015 at 09:23:27AM -0400, Rob Clark wrote:
On Thu, Jul 16, 2015 at 10:13 AM, Maarten Lankhorst
maarten.lankho...@linux.intel.com wrote:
This removes the need to
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
Various projects desire a mechanism for managing dependencies between
work items asynchronously. This can also include work items across
complete different and independent systems. For
On Mon, Jul 27, 2015 at 02:20:43PM +0100, Tvrtko Ursulin wrote:
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled status
should be
set on demand rather than polled. That
Op 27-07-15 om 13:16 schreef Daniel Vetter:
On Mon, Jul 27, 2015 at 01:04:20PM +0200, Maarten Lankhorst wrote:
This is required for DPMS to work correctly, during a modeset
the DPMS property should be turned off, unless the state is
crtc is made active in which case it should be set to DPMS
On Mon, Jul 27, 2015 at 01:21:01PM +0200, Thierry Reding wrote:
On Thu, Jul 23, 2015 at 09:38:46AM +0200, Daniel Vetter wrote:
[...]
On Thu, Jul 23, 2015 at 9:31 AM, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
[...]
Shobhit Kumar (8):
[...]
pwm: crc: Add Crystalcove (CRC) PWM
On 07/17/2015 03:31 PM, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled status should be
set on demand rather than polled. That is, there should not be a need for a
'signaled' function to be called
On Mon, Jul 27, 2015 at 03:09:54PM +0200, Daniel Vetter wrote:
On Mon, Jul 27, 2015 at 01:21:01PM +0200, Thierry Reding wrote:
On Thu, Jul 23, 2015 at 09:38:46AM +0200, Daniel Vetter wrote:
[...]
On Thu, Jul 23, 2015 at 9:31 AM, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
[...]
Op 27-07-15 om 09:53 schreef Daniel Vetter:
On Wed, Jul 22, 2015 at 09:23:27AM -0400, Rob Clark wrote:
On Thu, Jul 16, 2015 at 10:13 AM, Maarten Lankhorst
maarten.lankho...@linux.intel.com wrote:
This removes the need to separately track fb changes i915.
Changes since v1:
- Add dri-devel to
This is required for DPMS to work correctly, during a modeset
the DPMS property should be turned off, unless the state is
crtc is made active in which case it should be set to DPMS on.
The legacy dpms handling performs its own dpms updates, so add a
property to prevent updating the legacy dpms
This is required for DPMS to work correctly, during a modeset
the DPMS property should be turned off, unless the state is
crtc is made active in which case it should be set to DPMS on.
Changes since v1:
- Set DPMS to off when a connector is removed from a crtc too.
- Update the legacy dpms
On Thu, Jul 23, 2015 at 04:34:58PM -0700, Rodrigo Vivi wrote:
By Vesa's DP 1.2 Spec this counter has 4 bits [3:0].
This mask is wrong since when the counter was introduced by myself
on commit ad9dc91b6e21266bfc6f466db4b95e10211f31ee
Author: Rodrigo Vivi rodrigo.v...@gmail.com
Date: Tue
On Fri, 2015-07-03 at 13:38 +0100, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:35:54PM +0300, Mika Kahola wrote:
It is possible the we request to have a mode that has
higher pixel clock than our HW can support. This patch
checks if requested pixel clock is lower than the one
supported
On Mon, Jul 27, 2015 at 01:24:29PM +0200, Maarten Lankhorst wrote:
This is required for DPMS to work correctly, during a modeset
the DPMS property should be turned off, unless the state is
crtc is made active in which case it should be set to DPMS on.
Changes since v1:
- Set DPMS to off
On Mon, Jul 27, 2015 at 01:04:20PM +0200, Maarten Lankhorst wrote:
This is required for DPMS to work correctly, during a modeset
the DPMS property should be turned off, unless the state is
crtc is made active in which case it should be set to DPMS on.
The legacy dpms handling performs its
Hey,
Op 27-07-15 om 13:14 schreef Daniel Vetter:
On Mon, Jul 27, 2015 at 01:07:37PM +0200, Maarten Lankhorst wrote:
Op 27-07-15 om 09:53 schreef Daniel Vetter:
On Wed, Jul 22, 2015 at 09:23:27AM -0400, Rob Clark wrote:
On Thu, Jul 16, 2015 at 10:13 AM, Maarten Lankhorst
We were not checking the return value of drm_encoder_init() which can
fail. And if it fails then we will be working with an uninitialized
encoder.
Signed-off-by: Sudip Mukherjee su...@vectorindia.org
---
drivers/gpu/drm/i915/intel_dp.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
Use goto to handle the error path to avoid duplicating the same code. In
the error path intel_dig_port is the last one to be released as it was
the first one to be allocated and ideally the error path should be the
reverse of the execution path.
Signed-off-by: Sudip Mukherjee
Connectors are updated atomically now, so the only interaction
with the encoder is through base.crtc.
If it's NULL the encoder's not part of any crtc, and if it's
not NULL then active should be equal to crtc_state-active.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
This is now done completely atomically.
Keep connectors_active for now, but make it mirror crtc_state-active.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_crt.c | 49 +-
drivers/gpu/drm/i915/intel_display.c | 99
connectors_active will be removed, so just calculate this right here.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
On Mon, Jul 27, 2015 at 02:35:30PM +0200, Maarten Lankhorst wrote:
Set active_changed to force a modeset if the panel fitter's force
enabled.
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
Hm, shouldn't our fancy fastset logic be able to detect that we've changed
pfit
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 7/27/2015 11:02 AM, Sonika Jindal wrote:
WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
DDIA HPD pin in place of DDIB.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and
On Thu, Jul 09, 2015 at 07:29:12PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we
On 7/27/2015 3:46 PM, Chris Wilson wrote:
On Mon, Jul 27, 2015 at 08:04:50PM +0530, Goel, Akash wrote:
On 7/16/2015 3:03 PM, Michel Thierry wrote:
There are some allocations that must be only referenced by 32-bit
offsets. To limit the chances of having the first 4GB already full,
objects not
On Mon, Jul 27, 2015 at 08:04:50PM +0530, Goel, Akash wrote:
On 7/16/2015 3:03 PM, Michel Thierry wrote:
There are some allocations that must be only referenced by 32-bit
offsets. To limit the chances of having the first 4GB already full,
objects not requiring this workaround use
On 7/16/2015 3:03 PM, Michel Thierry wrote:
There are some allocations that must be only referenced by 32-bit
offsets. To limit the chances of having the first 4GB already full,
objects not requiring this workaround use DRM_MM_SEARCH_BELOW/
DRM_MM_CREATE_TOP flags
In specific, any resource
On Thu, Jul 09, 2015 at 07:29:11PM +0100, Dave Gordon wrote:
Turn on interrupt steering to route necessary interrupts to GuC.
v4:
Rebased
Issue: VIZ-4884
Signed-off-by: Alex Dai yu@intel.com
Signed-off-by: Dave Gordon david.s.gor...@intel.com
---
On Thu, Jul 09, 2015 at 07:29:13PM +0100, Dave Gordon wrote:
This provides a means of reading status and counts relating
to GuC actions and submissions.
v2:
Remove surplus blank line in output [Chris Wilson]
v4:
Rebased
Signed-off-by: Dave Gordon david.s.gor...@intel.com
On Mon, 2015-07-27 at 10:31 +0200, Daniel Vetter wrote:
On Fri, Jul 24, 2015 at 04:38:56PM -0700, Rodrigo Vivi wrote:
Since active function on VLV immediately activate PSR let's give more
time for idleness. Different from core platforms where we have idle_frames
count.
Also
Thierry has noticed that this name was inconsistent with spec.
This was wrong since I had introduced with
commit ad9dc91b6e21 (drm/i915: Fix Sink CRC)
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
include/drm/drm_dp_helper.h | 2 +-
2 files
On Mon, 2015-07-27 at 10:36 +0200, Daniel Vetter wrote:
On Fri, Jul 24, 2015 at 04:42:27PM -0700, Rodrigo Vivi wrote:
Since active function on VLV immediately activate PSR let's give more
time for idleness. Different from core platforms where we have idle_frames
count.
Also
On 07/27/2015 08:57 AM, O'Rourke, Tom wrote:
On Thu, Jul 09, 2015 at 07:29:12PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be
On Thu, Jul 16, 2015 at 10:33:29AM +0100, Michel Thierry wrote:
+ if (!(entry-flags EXEC_OBJECT_SUPPORTS_48B_ADDRESS)
+ (vma-node.start + vma-node.size) = (1ULL 32))
+ return true;
gcc completely screwed this up here and used 0 for 1ULL32.
Note that we can allow
On 07/24/2015 03:31 PM, O'Rourke, Tom wrote:
[TOR:] When I see phase 1 I also look for phase 2.
A subject that better describes the change in this patch
would help.
On Thu, Jul 09, 2015 at 07:29:08PM +0100, Dave Gordon wrote:
From: Alex Dai yu@intel.com
This adds the first of the data
On Mon, Jul 27, 2015 at 03:41:31PM -0700, Yu Dai wrote:
On 07/24/2015 03:31 PM, O'Rourke, Tom wrote:
[TOR:] When I see phase 1 I also look for phase 2.
A subject that better describes the change in this patch
would help.
On Thu, Jul 09, 2015 at 07:29:08PM +0100, Dave Gordon wrote:
On 07/27/2015 04:12 PM, O'Rourke, Tom wrote:
On Mon, Jul 27, 2015 at 03:41:31PM -0700, Yu Dai wrote:
On 07/24/2015 03:31 PM, O'Rourke, Tom wrote:
[TOR:] When I see phase 1 I also look for phase 2.
A subject that better describes the change in this patch
would help.
On Thu, Jul 09,
Recently added tools / benckmarks have the same module name as
existing tests. Android does not allow duplicate modules. This
patch appends _benchmark and _tool to the module names used when
building benckmarks and tools to prevent clashes with tests of
the same name.
Signed-off-by: Derek Morton
On 7/27/2015 2:58 PM, Daniel Vetter wrote:
On Sun, Jul 26, 2015 at 02:07:10PM +0530, Uma Shankar wrote:
From: Shashank Sharma shashank.sha...@intel.com
This patch adds two new functions:
- disable_dsi_pll.
BXT DSI disable sequence and registers are
different from previous platforms.
-
On Mon, 27 Jul 2015 09:59:45 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
The tables aren't sorted, that is worth fixing.
Attached patch should do that and fix the loop. Now it boots without
errors.
Does that look okay? If so please apply.
--
Hanno Böck
http://hboeck.de/
mail/jabber:
On Monday 27 July 2015 04:51 PM, Thierry Reding wrote:
On Thu, Jul 23, 2015 at 09:38:46AM +0200, Daniel Vetter wrote:
[...]
On Thu, Jul 23, 2015 at 9:31 AM, Daniel Vetter daniel.vet...@ffwll.ch wrote:
[...]
Shobhit Kumar (8):
[...]
pwm: crc: Add Crystalcove (CRC) PWM driver
Would
Hi,
I was trying to track down an out of bounds read issue in the intel drm
driver that got reported by kasan.
It happens in the function validate_cmds_sorted (i915_cmd_parser.c),
where there are two nested loops, this is the relevant code part:
for (i = 0; i cmd_table_count; i++) {
Am Donnerstag, 23. Juli 2015, 15:16:23 schrieb Danilo Cesar Lemes de Paula:
Hi Danilo,
This series add supports for hyperlink cross-references on Docbooks and
an optional markup syntax for in-source Documentation.
Can you please give an example what you mean with the latter?
Thanks for
Hello,
Correct me if I'm wrong. From my understanding (through Googling) so far,
stolen memory is a memory that is managed under the graphics firmware but not
managed by the Linux kernel itself.
I'm wondering how I can allocate and use a stolen memory in i915. Or is memory
allocated under
On Wed, Jul 22, 2015 at 09:23:27AM -0400, Rob Clark wrote:
On Thu, Jul 16, 2015 at 10:13 AM, Maarten Lankhorst
maarten.lankho...@linux.intel.com wrote:
This removes the need to separately track fb changes i915.
Changes since v1:
- Add dri-devel to cc.
- Fix a check in intel's prepare
On Thu, 23 Jul 2015, David Henningsson david.hennings...@canonical.com wrote:
This callback will be called by the i915 driver to notify the hda
driver that HDMI has been hotplugged.
Signed-off-by: David Henningsson david.hennings...@canonical.com
---
include/drm/i915_component.h |5
On Fri, Jul 24, 2015 at 04:52:03PM +0100, Chris Wilson wrote:
On Fri, Jul 24, 2015 at 05:40:12PM +0200, Daniel Vetter wrote:
v2: Clarify that this is about fence _registers_. Also clarify that
the fence code revokes cpu ptes and not gtt ptes. Both suggested by
Chris.
Cc: Chris Wilson
On Fri, Jul 24, 2015 at 04:38:56PM -0700, Rodrigo Vivi wrote:
Since active function on VLV immediately activate PSR let's give more
time for idleness. Different from core platforms where we have idle_frames
count.
Also kms_psr_sink_crc now is automated and always get this:
On Fri, Jul 24, 2015 at 04:42:27PM -0700, Rodrigo Vivi wrote:
Since active function on VLV immediately activate PSR let's give more
time for idleness. Different from core platforms where we have idle_frames
count.
Also kms_psr_sink_crc now is automated and always get this:
On Fri, Jul 24, 2015 at 10:39:04PM -0400, Dan Williams wrote:
acpi_os_ioremap uses cached mappings, however it appears that i915
wants to read dynamic platform state. Switch to ioremap() to prevent it
reading stale state from cache.
Cc: Daniel Vetter daniel.vet...@intel.com
Cc: Jani Nikula
No need to break module and system loading due to a programming bug.
Remove the BUG_ON and replace with a gentler DRM_ERROR_ON and error
return.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 11 ---
1 file changed, 8 insertions(+), 3
i915 has a habit of using WARN_ON and spewing stacktraces into the
kernel logs and beyond. For the majority of cases, we do not care about
the stacktrace, we know precisely where and when the error occurs so
hunting down the exact instance is not a concern, we only need the
content of the error.
On Wed, Jul 22, 2015 at 07:21:48PM +0530, ankitprasad.r.sha...@intel.com wrote:
From: Chris Wilson chris at chris-wilson.co.uk
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the
Remove the leftovers, yay!
AGP for i915 kms died long ago with
commit 3bb6ce66866310f50d461b9eff949c1ce95560ce
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Wed Nov 13 22:14:16 2013 +0100
drm/i915: Kill legeacy AGP for gen3 kms
and with ums now gone to there's really no users any
On Sun, Jul 26, 2015 at 12:30:25AM +0530, Animesh Manna wrote:
Grabbing a runtime pm reference with intel_runtime_pm_get will only
prevent device D3. But dmc firmware is required even earlier (namely
for the skl power well 1). DMC is responsible to save the status of
power well 1 and shut off
On Sat, Jul 25, 2015 at 06:56:20PM -0700, Hanno Böck wrote:
Hi,
I was trying to track down an out of bounds read issue in the intel drm
driver that got reported by kasan.
It happens in the function validate_cmds_sorted (i915_cmd_parser.c),
where there are two nested loops, this is the
On Sun, Jul 26, 2015 at 02:07:10PM +0530, Uma Shankar wrote:
From: Shashank Sharma shashank.sha...@intel.com
This patch adds two new functions:
- disable_dsi_pll.
BXT DSI disable sequence and registers are
different from previous platforms.
- intel_disable_dsi_pll
wrapper function
When we shrink our working sets, we want to avoid stealing pages from
objects that likely to be reused in the near future. We first look at
inactive objects before processing active objects - but what about a
recently active object that is about to be used again. That object's
position in the
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