On Sat, 22 Aug 2015, David Ho wrote:
> REQUEST
>
> May I please request support for driver of Intel GMA 3150 for Ubuntu 14.04.3
> 32 bit (Trusty Tahr)?
>
> I installed "Intel Graphic Installer for Linux" from 01.org, but it stops at
> the very first step saying "Distribution not supported".
Rodri
On Mon, 31 Aug 2015, Jani Nikula wrote:
> On Sat, 29 Aug 2015, Lukas Wunner wrote:
>> Hi Daniel, Hi Jani,
>>
>> the patch set I've posted August 12 included 3 commits which fix bugs
>> in i915. These bugs should be fixed independently of MacBook Pro GPU
>> switching, please consider merging them:
On Mon, 31 Aug 2015, Jesse Barnes wrote:
> On 07/15/2015 04:57 AM, Lukas Wunner wrote:
>> Commit 92122789b2d6 ("drm/i915: preserve SSC if previously set v3")
>> added code to intel_modeset_gem_init to override the SSC status read
>> from VBT with the SSC status set by BIOS.
>>
>> However, intel_m
Op 28-08-15 om 15:42 schreef Ander Conselvan De Oliveira:
> On Thu, 2015-08-20 at 18:12 -0700, Matt Roper wrote:
>> Signed-off-by: Matt Roper
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 10 ++
>> drivers/gpu/drm/i915/intel_display.c | 51 ++--
>> drivers/gpu/drm/i
Op 29-08-15 om 01:57 schreef Matt Roper:
> Way back at the beginning of i915's atomic conversion I added
> intel_crtc->atomic as a temporary dumping ground for "stuff to do
> outside vblank evasion" flags since CRTC states weren't properly wired
> up and tracked at that time. We've had proper CRTC
This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. On
Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_reg.h |8
drivers/gpu/drm/i915/intel_
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28
1 file changed, 28 insertion
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i91
This patch sets default initial phase and trip to scale NV12
content. In future, if needed these can be set via properties
or other means depending on incoming stream request. Until then
defaults are fine.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_display.c |7 +++
dr
Adding NV12 90/270 rotation support for primary and sprite planes.
v2:
-For 90/270 adjust pixel boundary only in Y-direction (bspec)
v3:
-Rebased (me)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 28 +++--
drivers/gpu/drm/i915/i
This patch adds NV12 to list of supported formats for
sprite plane.
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_sprite.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/
This patch adds register definitions for skylake
display NV12 support.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fa
This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.
For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Onc
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_atomic.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
di
This patch updates max supported scaler limits for NV12.
v2:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_display.c | 13 +
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_sprite.c |
When the plane source pixel format is NV12, the CHICKEN_PIPESL
register bit 22 must be set to 1
v2:
-one wa per commit with comments, and function headers (Daniel)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_csr.c | 2
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
Signed-off-by: Chandra Konduru
---
drivers/gpu/d
This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_drv.h|1 +
drivers/gpu/drm/i915/intel_sprite.c |9 +
2 fi
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
in
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
This patch series is adding initial NV12 support for Skylake display
after rebasing on latest drm-intel-nightly. Earlier I had two patch
series one for 0/180 and another for 90/270. Some of the patches
were already merged. This is combined series to support 0/90/180/270
and removing the ones that a
On Thu, Aug 27, 2015 at 03:15:15PM +0200, Maarten Lankhorst wrote:
> Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic.
> Remove the legacy suspend/resume, to fix a warning introduced by:
>
> "drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers"
>
> and r
Extend this to SKL and BXT as it's needed for these platforms as well.
v2: Change if condition to HAS_DDI() instead of listing each platform
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
On 07/15/2015 04:57 AM, Lukas Wunner wrote:
> Commit 92122789b2d6 ("drm/i915: preserve SSC if previously set v3")
> added code to intel_modeset_gem_init to override the SSC status read
> from VBT with the SSC status set by BIOS.
>
> However, intel_modeset_gem_init is invoked *after* intel_modeset_
On Sat, 29 Aug 2015, Lukas Wunner wrote:
> Hi Daniel, Hi Jani,
>
> the patch set I've posted August 12 included 3 commits which fix bugs
> in i915. These bugs should be fixed independently of MacBook Pro GPU
> switching, please consider merging them:
>
> drm/i915: Preserve SSC earlier
> http://pat
On Mon, Aug 31, 2015 at 08:01:21PM +0100, Emil Velikov wrote:
> > Reusing bo_gem here is a little worrying as it would be very easy for
> > someone to add code to the end of the function thinking that bo_gem
> > still was the batch.
> >
> Doesn't this concert apply to drm_intel_gem_bo_exec() as wel
On 31 August 2015 at 19:26, Chris Wilson wrote:
> On Mon, Aug 31, 2015 at 07:14:12PM +0100, Emil Velikov wrote:
>> Just like we do for the original exec()
>>
>> v2: move bo_gem declaration to the top of the function.
>>
>> Cc: Chris Wilson
>> Cc: intel-gfx@lists.freedesktop.org
>> Signed-off-by:
On Mon, Aug 31, 2015 at 06:59:40PM +0200, Michał Winiarski wrote:
> On each call to gen8_alloc_va_range_3lvl we're allocating temporary
> bitmaps needed for error handling. Unfortunately, when we increase
> address space size (48b ppgtt) we do additional (512 - 4) calls to
> kcalloc, increasing lat
On Mon, Aug 31, 2015 at 07:14:12PM +0100, Emil Velikov wrote:
> Just like we do for the original exec()
>
> v2: move bo_gem declaration to the top of the function.
>
> Cc: Chris Wilson
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Emil Velikov
> ---
> intel/intel_bufmgr_gem.c | 7
On Mon, Aug 31, 2015 at 07:13:12PM +0100, Emil Velikov wrote:
> v2: keep the bo_gem declaration in exec2() within the loop (Chris)
>
> Cc: Chris Wilson
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Emil Velikov
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, Intel Open Source Techn
Just like we do for the original exec()
v2: move bo_gem declaration to the top of the function.
Cc: Chris Wilson
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Emil Velikov
---
intel/intel_bufmgr_gem.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/intel/intel_b
v2: keep the bo_gem declaration in exec2() within the loop (Chris)
Cc: Chris Wilson
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Emil Velikov
---
intel/intel_bufmgr_fake.c | 2 +-
intel/intel_bufmgr_gem.c | 7 +++
intel/intel_decode.c | 7 ++-
3 files changed, 6 insertions(+
On each call to gen8_alloc_va_range_3lvl we're allocating temporary
bitmaps needed for error handling. Unfortunately, when we increase
address space size (48b ppgtt) we do additional (512 - 4) calls to
kcalloc, increasing latency between exec and actual start of execution
on the GPU. Let's just do
On Mon, Aug 31, 2015 at 06:27:40PM +0200, Michał Winiarski wrote:
> On each call to gen8_alloc_va_range_3lvl we're allocating temporary
> bitmaps needed for error handling. Unfortunately, when we increase
> address space size (48b ppgtt) we do additional (512 - 4) calls to
> kcalloc, increasing lat
On each call to gen8_alloc_va_range_3lvl we're allocating temporary
bitmaps needed for error handling. Unfortunately, when we increase
address space size (48b ppgtt) we do additional (512 - 4) calls to
kcalloc, increasing latency between exec and actual start of execution
on the GPU. Let's just do
On Thu, 20 Aug 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We are no longer checkling the DP link status on long hpd. We used to do
> that from the .hot_plug() handler, but it was removed when MST got
> introduced.
>
> If there's no userspace we now fail to retrain the lin
On Sat, 29 Aug 2015, Mikko Rapeli wrote:
> Please, please merge this patch already. Without it hibernation poweroff
> is broken for several users. There were some doubts raised over the
> approach on lkml review but Imre as maintainer thinks this is the right
> thing to do and users like me need t
On Thu, 13 Aug 2015, Xiong Zhang wrote:
> From B spec, DDI_E port belong to PowerWell 2, but
> DDI_E share the powerwell_req/staus register bit with
> DDI_A which belong to DDI_A_E_POWER_WELL.
>
> In order to communicate with the connector on DDI-E, both
> DDI_A_E_POWER_WELL and POWER_WELL_2 must
On Sat, 08 Aug 2015, Rodrigo Vivi wrote:
> There are OEMs using DDI-E out there,
> so let's enable it.
>
> Unfortunately there is no detection bit for DDI-E
> So we need to rely on VBT for that.
>
> I also need to give credits to Xiong since before seing
> his approach to check info->support_* I w
On Mon, 17 Aug 2015, Xiong Zhang wrote:
> DDI-E doesn't have the correspondent GMBUS pin.
>
> We rely on VBT to tell us which one it being used instead.
>
> The DVI/HDMI on shared port couldn't exist.
>
> This patch isn't tested without hardware wchich has HDMI
> on DDI-E.
>
> v2: fix trailing whi
On Thu, 06 Aug 2015, Xiong Zhang wrote:
> From: Rodrigo Vivi
>
> On Skylake we have eDP-to-VGA using DDI-E and another aux.
> So let's identify it properly.
>
> Also let's remove duplicated definitions to avoid later
> confusion.
>
> Signed-off-by: Rodrigo Vivi
Pushed to drm-intel-next-fixes wi
On Thu, Aug 27, 2015 at 10:23 AM, wrote:
> From: Ville Syrjälä
>
> AUX addresses are 20 bits long. Send out the entire address instead of
> just the low 16 bits.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Signed-off-by: Ville Syrjälä
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/rade
On Thu, 2015-08-20 at 18:12 -0700, Matt Roper wrote:
> In addition to calculating final watermarks, let's also pre-calculate a
> set of intermediate watermark values at atomic check time. These
> intermediate watermarks are a combination of the watermarks for the old
> state and the new state; the
On Mon, Aug 31, 2015 at 05:23:27PM +0300, Jani Nikula wrote:
> On Thu, 27 Aug 2015, Jani Nikula wrote:
> > On Thu, 27 Aug 2015, Chris Wilson wrote:
> >> On Thu, Aug 27, 2015 at 04:23:30PM +0300, Jani Nikula wrote:
> >>> Add a common function to return "yes" or "no" string based on the
> >>> argum
On Thu, 27 Aug 2015, Jani Nikula wrote:
> On Thu, 27 Aug 2015, Chris Wilson wrote:
>> On Thu, Aug 27, 2015 at 04:23:30PM +0300, Jani Nikula wrote:
>>> Add a common function to return "yes" or "no" string based on the
>>> argument, and drop the local versions of it.
>>
>> Purely out of curiosity,
There have been many hard to track down bugs whereby userspace forgot to
flag a write buffer and then cause graphics corruption or a hung GPU
when that buffer was later purged under memory pressure (as the buffer
appeared clean, its pages would have been evicted rather than preserved
and any change
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7274
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> The full ppgtt is supported now in Intel GVT-g device model.
> Broadwell
> is allowed to use it in virtual machines.
>
> v2:
> - Keep backward compatibility on HSW with old device model (daniel)
>
> Signed-off-by: Zhiyuan Lv
> Signed-off-by:
On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> Broadwell hardware supports both ring buffer mode and execlist mode.
> When i915 runs inside a VM with Intel GVT-g, we allow execlist mode
> only.
>
> The main reason of EXECLIST only is that GVT-g does not support the
> dynamic mode switch bet
On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote:
> When i915 drivers run inside a VM with Intel GVT-g, some explicit
> notifications are needed from guest to host device model through PV
> INFO page write. The notifications include:
>
> PPGTT create
> PPGTT destroy
>
> They are use
On Wed, Aug 26, 2015 at 03:26:08PM +0200, Patrik Jakobsson wrote:
> On Tue, Aug 25, 2015 at 11:12 PM, Mike Frysinger wrote:
> > On 24 Aug 2015 14:42, Patrik Jakobsson wrote:
> >> We need to be able to store private data in the tcb across it's
> >> lifetime. To ensure proper destruction of the data
On Mon, Aug 31, 2015 at 01:04:26PM +0200, Maarten Lankhorst wrote:
> This makes the error message slightly more useful.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_drv.h| 2 ++
> drivers/gpu/drm/i915/intel_sprite.c | 6 --
> 2 files changed, 6 insertions(+), 2
Hi Chris, Daniel.
Thanks for your inputs.
I agree that we need to amend the patch. Will do following changes.
1. RPM ref count is not needed with immediate enabling of RC6, I will
remove that.
2. I will extend this to other GEN as well.
This was one of the set of optimization we implement
On Mon, Aug 31, 2015 at 11:23:28AM +0300, Ander Conselvan de Oliveira wrote:
> The DP MST encoder config function never sets ddi_pll_sel, even though
> its value is programmed in its ->pre_enable() hook. That used to work
> because a new pipe_config was kzalloc'ed at every modeset, and the value
>
This makes the error message slightly more useful.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_drv.h| 2 ++
drivers/gpu/drm/i915/intel_sprite.c | 6 --
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i9
There's already a per crtc member that can be used for it.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 9 -
drivers/gpu/drm/i915/intel_drv.h | 5 ++---
drivers/gpu/drm/i915/intel_sprite.c | 15 ---
3 files changed, 14 insertions(+), 15 d
On 08/27/2015 04:32 PM, Ville Syrjälä wrote:
On Thu, Aug 27, 2015 at 10:06:09AM +0530, Deepak wrote:
On 07/09/2015 02:16 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Add some checks that the state of the DPIO lanes is more or less what we
expect based on the overrides.
The
Commit ec9f932ed41622d120de52a5b525e4d77b9ef17e
"drm/atomic: Cleanup on error properly in the atomic ioctl."
cleaned up some error paths, but didn't fix the TEST_ONLY path.
In the check only case plane->fb shouldn't be updated, and
the vblank events should be cleared as on failure.
Changes since v
On Wed, Aug 26, 2015 at 11:42:23AM +0100, Thomas Wood wrote:
> On 24 August 2015 at 10:59, Stefan Dirsch wrote:
> > Hi
> >
> > Find a simple buildfix against current intel-gpu-tools git sources attached.
>
> I assume the compiler warning is about uninitialised values and unused
> variables? It lo
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7273
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
From: Durgadoss R
Currently, HDMI hotplug with eDP as local panel is failing
because the HDMI hpd is detected as a long hpd for eDP; and is
thus rightfully ignored. But, it should really be handled as
an interrupt on port B for HDMI (due to BXT A1 platform having
HPD pins A and B swapped). This p
The DP MST encoder config function never sets ddi_pll_sel, even though
its value is programmed in its ->pre_enable() hook. That used to work
because a new pipe_config was kzalloc'ed at every modeset, and the value
of zero selects the highest clock for the PLL. Starting with the commit
below, the va
Op 27-08-15 om 17:22 schreef Daniel Vetter:
> On Thu, Aug 27, 2015 at 03:36:09PM +0100, Daniel Stone wrote:
>> Hi,
>>
>> On 6 August 2015 at 13:49, Daniel Vetter wrote:
>>> On Thu, Aug 06, 2015 at 01:19:35PM +0200, Maarten Lankhorst wrote:
Op 06-08-15 om 11:47 schreef Daniel Stone:
> On 3
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