[Intel-gfx] [DMC_BUGFIX_V3] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

Mmio register access after dc6/dc5 entry is not allowed when DC6 power states are enabled according to bspec (bspec-id 0527), so enabling dc6 as the last call in suspend flow. v1: Initial version. v2: Based on review comment from Daniel, - created a seperate patch for csr uninitialization set

Re: [Intel-gfx] [PATCH v4 1/2] drm/dp: Store the drm_connector device pointer on the helper.

Hi Rafael, [auto build test results on v4.3-rc3 -- if it's inappropriate base, please ignore] reproduce: make htmldocs All warnings (new ones prefixed by >>): drivers/gpu/drm/i915/i915_irq.c:491: warning: No description found for parameter 'dev' drivers/gpu/drm/i915/i915_irq.c:2217:

Re: [Intel-gfx] [PATCH] drm/i915: Add hot_plug hook for hdmi encoder

On 9/28/2015 7:04 PM, Daniel Vetter wrote: On Mon, Sep 28, 2015 at 02:26:04PM +0530, Sonika Jindal wrote: This patch adds a separate probe function for HDMI EDID read over DDC channel. This function has been registered as a .hot_plug handler for HDMI encoder. The current implementation of

Re: [Intel-gfx] [PATCH 10/23] drm/i915: Add gamma correction handlers

Ok, anyways it was sounding like a good idea. Will do the changes accordingly. Regards Shashank -Original Message- From: Roper, Matthew D Sent: Tuesday, September 29, 2015 3:13 AM To: Sharma, Shashank Cc: Daniel Vetter; Bish, Jim; Bradford, Robert; Smith, Gary K;

Re: [Intel-gfx] [PATCH 10/23] drm/i915: Add gamma correction handlers

Thank you Shashank! Annie Matheson > On Sep 28, 2015, at 9:29 PM, Sharma, Shashank > wrote: > > Ok, anyways it was sounding like a good idea. > Will do the changes accordingly. > > Regards > Shashank > -Original Message- > From: Roper, Matthew D > Sent:

Re: [Intel-gfx] [BXT MIPI PATCH v4 05/14] drm/i915/bxt: DSI encoder support in CRTC modeset

>-Original Message- >From: Jani Nikula [mailto:jani.nik...@linux.intel.com] >Sent: Monday, September 28, 2015 6:58 PM >To: Shankar, Uma; intel-gfx@lists.freedesktop.org >Cc: Kumar, Shobhit; Deak, Imre; Sharma, Shashank; Shankar, Uma >Subject: Re: [BXT MIPI PATCH v4 05/14] drm/i915/bxt:

Re: [Intel-gfx] [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

On 28/09/2015 17:02, Ville Syrjälä wrote: On Mon, Sep 28, 2015 at 04:51:52PM +0100, Arun Siluvery wrote: On 25/09/2015 18:09, Ville Syrjälä wrote: On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote: Signed-off-by: Arun Siluvery ---

Re: [Intel-gfx] [RFC] Docs: drm: Move KMS properties table out to source files

On Mon, 28 Sep 2015 10:36:59 +0100 Graham Whaley wrote: > I've still not thought of a way of tweaking the kernel-doc and pandoc > processing to work around this either, as they are done as different > passes/phases that neither has knowledge about the others >

Re: [Intel-gfx] [DMC_BUGFIX_SKL_V2 3/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

You believe suspend w/ DC6 should work due to the unconditional power-well reference, or you don't know and just couldn't merge since the patch didn’t apply? Gavin Hindman Senior Program Manager SSG/OTC – Open Source Technology Center -Original Message- From: Intel-gfx

[Intel-gfx] [PATCH] drm: Enforce unlocked ioctl operation for kms driver ioctls

With the prep patches for i915 all kms drivers either have DRM_UNLOCKED on all their ioctls. Or the ioctl always directly returns with an invariant return value when in modeset mode. But that's only the case for i915 and radeon. The drm core ioctls are unfortunately too much a mess still to dare

[Intel-gfx] [PATCH] drm/doc: Update docs about device instance setup

->load is deprecated, bus functions are deprecated and everyone should use drm_dev_alloc So update the .tmpl (and pull a bunch of the overview docs into the sourcecode to increase chances that it'll stay in sync in the future) and add notes to functions which are deprecated. I didn't bother to

[Intel-gfx] [PATCH 4.1, 4.2] drm/i915: Silence DDR DVFS errors on CHV

From: Ville Syrjälä commit 58590c14d80defc94e900308a9d8fa55284de6f2 upstream. 58590c1 drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOS can't be backported as is because proper DDR DVFS support didn't even exist before 6f9c784 drm/i915: Don't do

Re: [Intel-gfx] [PATCH 2/2] drm/doc: Update docs about device instance setup

Hi On Mon, Aug 10, 2015 at 4:30 PM, Daniel Vetter wrote: > On Mon, Aug 10, 2015 at 02:34:18PM +0200, Thierry Reding wrote: >> On Mon, Aug 10, 2015 at 02:07:49PM +0200, Daniel Vetter wrote: >> > On Mon, Aug 10, 2015 at 01:59:07PM +0200, Thierry Reding wrote: >> > > On Mon, Aug

Re: [Intel-gfx] [RFC DP-typeC 0/2] Support USB typeC based DP on BXT

Hi Daniel, >-Original Message- >From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter >Sent: Monday, September 28, 2015 1:50 PM >To: R, Durgadoss >Cc: Daniel Vetter; Jani Nikula; intel-gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] [RFC DP-typeC 0/2] Support

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Use czclk_freq in vlv c0 residency calculations

On Mon, 2015-09-28 at 23:47 +0300, Imre Deak wrote: > On Thu, 2015-09-24 at 23:29 +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Replace the use of mem_freq/4 with czclk_freq in the vlv c0 residency > > calculations. > > > > Also deal

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Read czclk from CCK on vlv/chv

On Mon, Sep 28, 2015 at 10:31:49PM +0300, Imre Deak wrote: > On Thu, 2015-09-24 at 23:29 +0300, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > As with the cdclk, read out czclk from CCK as well. This gives us the > > real current value and

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Use czclk_freq in vlv c0 residency calculations

On Thu, 2015-09-24 at 23:29 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Replace the use of mem_freq/4 with czclk_freq in the vlv c0 residency > calculations. > > Also deal with VLV_COUNT_RANGE_HIGH which affects all RCx residency >

[Intel-gfx] [PATCH] drm/i915/guc: Add GuC css header parser

From: Alex Dai The size / offset information of all firmware ingredients are now caculated from header. Driver will validate the header and rsa key size. If any component is out of boundary, driver will reject the loading too. v4: Now using 'size_dw' for those defined in

Re: [Intel-gfx] [PATCH 10/23] drm/i915: Add gamma correction handlers

Yep, Daniel's right; for properties that are not specific to the driver, the core core should take care of stuffing the values provided by userspace into the state structures so that every driver that wants to use these doesn't need to replicate that logic. My bad for not catching this in my

[Intel-gfx] [PATCH v2 3/4] drm/i915: Simplify vlv/chv rc6 residency calculation

From: Ville Syrjälä We have the czclk frequency in dev_priv now, so let's just use it when converting the rc6 counters to milliseconds. This eliminates a bunch of hairy code that essentially tries to extract the czclk frequency using yet another method. v2: Fix

Re: [Intel-gfx] [RFC PATCH] drm/i915: PSR regressions on Broadwell

On Mon, Sep 28, 2015 at 10:14:04AM +0300, Jani Nikula wrote: > On Sat, 26 Sep 2015, Brian Norris wrote: > > When using PSR, I see the screen freeze after only a few frames (sometimes a > > split second; sometimes it seems like practically the first frame). > > Bisecting

Re: [Intel-gfx] [PATCH v3] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

On Mon, 28 Sep 2015, Daniel Vetter wrote: > On Mon, Sep 28, 2015 at 05:00:12PM +0300, Mika Kuoppala wrote: >> Michel Thierry writes: >> >> > A previous commit resets the Context Status Buffer (CSB) read pointer in >> > ring init >> > commit

Re: [Intel-gfx] [PATCH 07/11] drm/drm_ioctl.c: kerneldoc

Hi On Tue, Sep 8, 2015 at 1:56 PM, Daniel Vetter wrote: > As usual pull it into the drm docbook template, too. And again as > usual I've decided to only document stuff exported to drivers, so all > the old leftover markup from the shared drm repo days lost the magic > **

Re: [Intel-gfx] [PATCH 2/2] drm/doc: Update docs about device instance setup

Hi Daniel, Thank you for the patch. On Monday 10 August 2015 11:55:38 Daniel Vetter wrote: > ->load is depracated, bus functionst are deprecated and everyone s/depracated/deprecated/ s/functionst/functions/ > should use drm_dev_alloc > > So update the .tmpl (and pull a bunch of the overview

Re: [Intel-gfx] [PATCH] drm/i915: Convert WARNs during userptr revoke to SIGBUS

On Mon, Sep 28, 2015 at 02:52:30PM +0100, Chris Wilson wrote: > On Mon, Sep 28, 2015 at 03:42:22PM +0200, Daniel Vetter wrote: > > On Wed, Sep 23, 2015 at 09:07:24PM +0100, Chris Wilson wrote: > > > If the client revokes the virtual address it asked to be mapped into GPU > > > space via userptr

Re: [Intel-gfx] [PATCH v3] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

Michel Thierry writes: > A previous commit resets the Context Status Buffer (CSB) read pointer in > ring init > commit c0a03a2e4c4e ("drm/i915: Reset CSB read pointer in ring init") > > This is generally correct, but this pointer is not reset after > suspend/resume

Re: [Intel-gfx] [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

On Mon, Sep 28, 2015 at 03:28:18PM +0300, Jani Nikula wrote: > On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Rather than computing on demand, store also the aux data reg > > offsets under intel_dp. > > > > Signed-off-by:

Re: [Intel-gfx] [PATCH 10/11] drm/: Drop DRM_UNLOCKED from modeset drivers

Hi On Tue, Sep 8, 2015 at 1:56 PM, Daniel Vetter wrote: > Just one special case (since i915 lost its ums code, yay): > - radeon: Has slots for the old ums ioctls which don't have > DRM_UNLOCKED, but all filled with drm_invalid_op. So ok to drop it > everywhere. > >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Recover all available ringbuffer space following reset

Hi, Chris Wilson writes: > Having flushed all requests from all queues, we know that all > ringbuffers must now be empty. However, since we do not reclaim > all space when retiring the request (to prevent HEADs colliding > with rapid ringbuffer wraparound) the amount

Re: [Intel-gfx] [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

On 25/09/2015 18:09, Ville Syrjälä wrote: On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote: Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH v2 38/43] drm/i915: Parametrize AUX registers

From: Ville Syrjälä v2: Keep some MISSING_CASE() stuff (Jani) s/-1/-PIPE_B/ in the register macro Fix typo in patch subject Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 102

[Intel-gfx] [PATCH v2 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

From: Ville Syrjälä Rather than computing on demand, store also the aux data reg offsets under intel_dp. v2: Duplicate some code to make things less magic (Jani) Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dp.c |

Re: [Intel-gfx] [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

On Mon, Sep 28, 2015 at 04:51:52PM +0100, Arun Siluvery wrote: > On 25/09/2015 18:09, Ville Syrjälä wrote: > > On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote: > >> Signed-off-by: Arun Siluvery > >> --- > >> drivers/gpu/drm/i915/intel_pm.c | 4 >

Re: [Intel-gfx] [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

On Mon, Sep 28, 2015 at 12:21:36PM +0100, Arun Siluvery wrote: > On 25/09/2015 14:33, Arun Siluvery wrote: > >Changes that add new WA, merge WA that are applied for the same register, > >update stepping checks and remove pre-production ones . > > > >Arun Siluvery (12): > > drm/i915/gen9: Handle

Re: [Intel-gfx] [PATCH v3] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

On Mon, Sep 28, 2015 at 05:00:12PM +0300, Mika Kuoppala wrote: > Michel Thierry writes: > > > A previous commit resets the Context Status Buffer (CSB) read pointer in > > ring init > > commit c0a03a2e4c4e ("drm/i915: Reset CSB read pointer in ring init") This is in

Re: [Intel-gfx] [PATCH 09/11] drm/vmwgfx: Stop checking for DRM_UNLOCKED

Hi On Tue, Sep 8, 2015 at 1:56 PM, Daniel Vetter wrote: > drm core enforces now for DRIVER_MODESET that all ioctls are unlocked. > And all the old nasty ones from drm core aren't allowed for modern > drivers any more. Hence this is no longer needed. > > Signed-off-by:

Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating

On Mon, Sep 28, 2015 at 10:51:39AM +0100, Arun Siluvery wrote: > On 28/09/2015 09:44, Jani Nikula wrote: > >On Fri, 25 Sep 2015, Arun Siluvery wrote: > >>Dropping it because it is for pre-production stepping. > > > >Hum, why have we added a pre-pro w/a without a

Re: [Intel-gfx] [PATCH] drm: Remove __OS_HAS_AGP

Hi On Wed, Sep 9, 2015 at 4:45 PM, Daniel Vetter wrote: > We already express the drm/agp depencies correctly in Kconfig, so we > can rip this remnant from the shared drm core days. > > Aside: Pretty much all the #ifdefs in radeon/nouveau could be killed > if ttm would

Re: [Intel-gfx] [PATCH 11/11] drm: Remove dummy agp ioctl wrappers

Hi On Tue, Sep 8, 2015 at 1:56 PM, Daniel Vetter wrote: > They're only used in the drm ioctl table, and there they're excluded > when AGP support is disabled. So this is just dead code ripe for > removal. > > Signed-off-by: Daniel Vetter

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Recover all available ringbuffer space following reset

On Mon, Sep 28, 2015 at 06:25:04PM +0300, Mika Kuoppala wrote: > > Hi, > > Chris Wilson writes: > > > Having flushed all requests from all queues, we know that all > > ringbuffers must now be empty. However, since we do not reclaim > > all space when retiring the

Re: [Intel-gfx] [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn

On Fri, Sep 25, 2015 at 07:54:46PM +0300, Ville Syrjälä wrote: > On Fri, Sep 25, 2015 at 05:40:46PM +0100, Arun Siluvery wrote: > > Signed-off-by: Arun Siluvery > > Series lgtm, so > Reviewed-by: Ville Syrjälä Except for patch 5 all

[Intel-gfx] [PATCH v2 41/43] drm/i915: Model PSR AUX register selection more like the normal AUX code

From: Ville Syrjälä v2: Split up the ctl vs. data reg handling like in the normal AUX code Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_psr.c | 27 +-- 1 file changed, 21 insertions(+), 6

Re: [Intel-gfx] [PATCH 08/11] drm: Enforce unlocked ioctl operation for kms driver ioctls

Hi On Tue, Sep 8, 2015 at 1:56 PM, Daniel Vetter wrote: > With the prep patches for i915 all kms drivers either have > DRM_UNLOCKED on all their ioctls. Or the ioctl always directly returns > with an invariant return value when in modeset mode. But that's only > the case

Re: [Intel-gfx] [PATCH 10/23] drm/i915: Add gamma correction handlers

On Sat, Sep 26, 2015 at 09:18:48PM +0530, Sharma, Shashank wrote: > On 9/23/2015 1:52 PM, Sharma, Shashank wrote: > >>Since color manager properties are meant as a new standardize KMS > >>extension (we put them into the core drm_crtc_state) the get/set support > >>should also be in the core. See

Re: [Intel-gfx] [DMC_BUGFIX_SKL_V2 1/5] drm/i915/skl: Added a check for the hardware status of csr fw before loading.

On Wed, Sep 23, 2015 at 10:49:36PM +0200, Rafael J. Wysocki wrote: > On 9/23/2015 7:17 PM, Daniel Vetter wrote: > >acpi_target_system_state() seems to be almost the thing we're looking > >for, except that it's only valid in the suspend callbacks since it > >gets reset to ACPI_STATE_S0 when

Re: [Intel-gfx] [RFC PATCH] drm/i915: PSR regressions on Broadwell

On Sat, 26 Sep 2015, Brian Norris wrote: > When using PSR, I see the screen freeze after only a few frames (sometimes a > split second; sometimes it seems like practically the first frame). Bisecting > led me to commit 3301d4092106 ("drm/i915: PSR: Fix

Re: [Intel-gfx] [DMC_BUGFIX_SKL_V2 5/5] drm/i915/skl: Block disable call for pw1 if dmc firmware is present.

On Mon, Sep 07, 2015 at 04:39:19PM +0530, Sunil Kamath wrote: > On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote: > >Another interesting criteria to work dmc as expected is pw1 to be > >enabled by driver and dmc will shut it off in its execution > >sequence. If already disabled by driver

Re: [Intel-gfx] [PATCH] drm/i915: On reset/suspend disable hpd pins & cancel pending delayed work

On Fri, Sep 25, 2015 at 03:29:40PM +0300, Ville Syrjälä wrote: > On Fri, Sep 25, 2015 at 08:09:57AM +0200, Egbert Eich wrote: > > +void intel_hpd_uninit(struct drm_i915_private *dev_priv) > > +{ > > + struct drm_device *dev = dev_priv->dev; > > + int i; > > + > > +

Re: [Intel-gfx] [PATCH] drm/i915: Don't call intel_prepare_ddi when encoder list isn't yet initialized.

On Fri, 25 Sep 2015, "Vivi, Rodrigo" wrote: > On Fri, 2015-09-25 at 13:52 +0300, Jani Nikula wrote: >> On Wed, 23 Sep 2015, Rodrigo Vivi wrote: >> > In case something goes wrong with power well initialization we were >> > calling >> >

Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/guc: Fix a bug in GuC status check

On Thu, Sep 24, 2015 at 10:29:18AM +0530, Kamble, Sagar A wrote: > Reviewed-by: Sagar Arun Kamble > > On 9/23/2015 2:18 AM, yu@intel.com wrote: > >From: Alex Dai > > > >Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE > >status is

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Support NV12 in rotated GGTT mapping

On Fri, Sep 25, 2015 at 02:29:59PM +0300, Ville Syrjälä wrote: > On Fri, Sep 25, 2015 at 10:44:44AM +0100, Tvrtko Ursulin wrote: > > > > On 09/24/2015 05:35 PM, Ville Syrjälä wrote: > > > On Mon, Sep 21, 2015 at 10:45:34AM +0100, Tvrtko Ursulin wrote: > > >> From: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating

On Fri, 25 Sep 2015, Arun Siluvery wrote: > Dropping it because it is for pre-production stepping. Hum, why have we added a pre-pro w/a without a stepping check... should we backport this to stable kernels? What's the impact on production hardware with vs. without

Re: [Intel-gfx] [DMC_BUGFIX_SKL_V2 1/5] drm/i915/skl: Added a check for the hardware status of csr fw before loading.

On Mon, Sep 07, 2015 at 04:34:30PM +0530, Sunil Kamath wrote: > On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote: > >Dmc will restore the csr program except DC9, cold boot, > >warm reset, PCI function level reset, and hibernate/suspend. > > > >intel_csr_load_program() function is used to

Re: [Intel-gfx] [DMC_BUGFIX_SKL_V2 3/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

On Wed, Aug 26, 2015 at 01:36:07AM +0530, Animesh Manna wrote: > Mmio register access after dc6/dc5 entry is not allowed when > DC6 power states are enabled according to bspec (bspec-id 0527), > so enabling dc6 as the last call in suspend flow. We unconditionaly grab a power well reference for

Re: [Intel-gfx] [PATCH] drm/i915: fixup runtime PM handling v2

On Thu, Sep 24, 2015 at 09:14:15PM +0200, Rafael J. Wysocki wrote: > On Thursday, September 24, 2015 08:40:28 AM Jesse Barnes wrote: > > Forgot to cc Rafael. > > > > On 09/23/2015 02:37 PM, Jesse Barnes wrote: > > > According to the PCI docs and Rafael, we don't need to be doing explicit > > >

Re: [Intel-gfx] [PATCH] drm/i915/bxt: eDP low vswing support

On Thu, Sep 24, 2015 at 10:24:56AM +0530, Sonika Jindal wrote: > Adding voltage swing table for edp to support low vswings. > > v2: Rebased. > > Signed-off-by: Sonika Jindal > Reviewed-by: Sivakumar Thulasimani Queued for -next, thanks

Re: [Intel-gfx] [PATCH 10/23] drm/i915: Add gamma correction handlers

Matt, your opinion about this ? Regards Shashank -Original Message- From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Monday, September 28, 2015 12:14 PM To: Sharma, Shashank Cc: Daniel Vetter; Roper, Matthew D; Bish, Jim; Bradford, Robert; Smith, Gary

[Intel-gfx] Updated drm-intel-testing

Hi all, New -testing cycle with cool stuff: - fastboot by default for some systems (Maarten Lankhorts) - piles of workarounds for bxt and skl - more fbc work from Paulo - fix hdmi hotplug detection (Sonika) - first few patches from Ville to parametrize register macros, prep work for typesafe

Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc: Add GuC css header parser

On Fri, Sep 25, 2015 at 05:36:37PM +0300, Jani Nikula wrote: > On Wed, 16 Sep 2015, yu@intel.com wrote: > > From: Alex Dai > > > > By using information from GuC css header, we can eliminate some > > hard code w.r.t size of some components of firmware. > > There's a catch

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Always call the adjusted mode 'adjusted_mode'

On Tue, Sep 08, 2015 at 01:40:45PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Always name any variable pointing at the adjusted mode as > 'adjustead_mode'. This will make it much easier to identify > when we should use the crtc_ timings

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/guc: Add GuC css header parser

On Fri, Sep 25, 2015 at 09:31:52AM -0700, Yu Dai wrote: > Be note that I will use term *length* or *len* in header definition, which > is in dwords unit. This is to avoid the confusion with *size*. lenght is also generally in bytes. If you want to use separate variables to avoid confusion I'd

Re: [Intel-gfx] [RFC DP-typeC 0/2] Support USB typeC based DP on BXT

On Fri, Sep 25, 2015 at 12:22:42PM +, R, Durgadoss wrote: > Hi Daniel, > > Thanks for having a look at it.. > > >-Original Message- > >From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > >Vetter > >Sent: Wednesday, September 23, 2015 3:14 PM > >To: R, Durgadoss

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Set oscaledcompmethod to enable scale value

On Thu, Sep 24, 2015 at 02:12:02PM +0300, Imre Deak wrote: > On to, 2015-09-24 at 10:22 +0530, Sonika Jindal wrote: > > Bspec update tells that we have to enable oscaledcompmethod instead of > > ouniqetrangenmethod for enabling scale value during swing programming. > > > > v2: Adding back 'don't

Re: [Intel-gfx] [PATCH v2 04/43] drm/i915: Parametrize fence registers

On Fri, Sep 25, 2015 at 03:02:37PM +0300, Jani Nikula wrote: > On Mon, 21 Sep 2015, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > v2: Hide the 945 vs. rest of gen2/3 difference in the macro > > > > Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH] drm/i915: Don't call intel_prepare_ddi when encoder list isn't yet initialized.

On Fri, Sep 25, 2015 at 04:09:56PM +, Vivi, Rodrigo wrote: > On Fri, 2015-09-25 at 13:52 +0300, Jani Nikula wrote: > > On Wed, 23 Sep 2015, Rodrigo Vivi wrote: > > > In case something goes wrong with power well initialization we were > > > calling > > >

Re: [Intel-gfx] [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

On pe, 2015-09-25 at 14:33 +0100, Arun Siluvery wrote: > It is also applicable for B0. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_pm.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git

Re: [Intel-gfx] [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

On 25/09/2015 14:33, Arun Siluvery wrote: Changes that add new WA, merge WA that are applied for the same register, update stepping checks and remove pre-production ones . Arun Siluvery (12): drm/i915/gen9: Handle error returned by gen9_init_workarounds drm/i915/gen9: Add

Re: [Intel-gfx] [PATCH 11/43] drm/i915: Parametrize UOS_RSA_SCRATCH

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_guc_reg.h | 2 +- >

Re: [Intel-gfx] [PATCH 15/43] drm/i915: Parametrize PALETTE and LGC_PALETTE

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_reg.h | 6 +++--- >

Re: [Intel-gfx] [PATCH 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- >

Re: [Intel-gfx] [PATCH 22/43] drm/i915: s/DDI_BUF_CTL_A/DDI_BUF_CTL(PORT_A)/

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file

Re: [Intel-gfx] [PATCH 21/43] drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASE

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_reg.h | 8 +++- >

Re: [Intel-gfx] [PATCH 40/43] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[]

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Rather than computing on demand, store also the aux data reg > offsets under intel_dp. > > Signed-off-by: Ville Syrjälä > --- >

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Support NV12 in rotated GGTT mapping

On Mon, Sep 28, 2015 at 10:37:24AM +0200, Daniel Vetter wrote: > On Fri, Sep 25, 2015 at 02:29:59PM +0300, Ville Syrjälä wrote: > > On Fri, Sep 25, 2015 at 10:44:44AM +0100, Tvrtko Ursulin wrote: > > > > > > On 09/24/2015 05:35 PM, Ville Syrjälä wrote: > > > > On Mon, Sep 21, 2015 at 10:45:34AM

Re: [Intel-gfx] [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

On 28/09/2015 12:06, Imre Deak wrote: On pe, 2015-09-25 at 14:33 +0100, Arun Siluvery wrote: It is also applicable for B0. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_pm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

Re: [Intel-gfx] [PATCH 12/43] drm/i915: Add LO/HI PRIVATE_PAT registers

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 8 >

Re: [Intel-gfx] [PATCH 13/43] drm/i915: Always use GEN8_RING_PDP_{LDW, UDW} instead of hand rolling the register offsets

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--- > 1 file

Re: [Intel-gfx] [PATCH 14/43] drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSR

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- >

Re: [Intel-gfx] [PATCH v2 16/43] drm/i915: s/_CURACNTR/CURCNTR(PIPE_A)/

On Tue, 22 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > v2: Deal with _CURABASE too Yeah better, though I was happy with v1 too. :) Reviewed-by: Jani Nikula > > Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Add HDMI aspect ratio property for SDVO

Reviewed-by: Mika Kahola On Fri, 2015-09-25 at 16:39 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Handle the HDMI aspect ratio property the same way in the SDVO code > as we handle it in the HDMI code. > > v2:

[Intel-gfx] [PATCH v2] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

A previous commit resets the Context Status Buffer (CSB) read pointer in ring init commit c0a03a2e4c4e ("drm/i915: Reset CSB read pointer in ring init") This is generally correct, but this pointer is not reset after suspend/resume in some platforms (cht). In this case, the driver should read

Re: [Intel-gfx] [RFC] Docs: drm: Move KMS properties table out to source files

On Mon, Sep 28, 2015 at 10:36:59AM +0100, Graham Whaley wrote: > On Tue, 2015-09-22 at 16:03 -0300, Danilo Cesar Lemes de Paula wrote: > > On 09/22/2015 07:22 AM, Graham Whaley wrote: > > > On Wed, Sep 02, 2015 at 02:50:52PM +0100, Graham Whaley wrote: > > > > > (RFC/test - not for merging) > > >

Re: [Intel-gfx] [PATCH 38/43] drm/i915: Parametrize AUX registes

On Fri, 18 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 102 > --- >

Re: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always use crtc_ timings when dealing with adjustead_mode

Reviewed-by: Mika Kahola On Fri, 2015-09-25 at 16:38 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The adjustead_mode crtc_ timings are what we will program into the hardware, > so it's those timings we should be

Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: s/mode/adjusted_mode/ in functions that really get passed the adjusted_mode

Reviewed-by: Mika Kahola On Fri, 2015-09-25 at 16:37 +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Rename the function argument to 'adjusted_mode' whenever the function > only ever gets passed the adjusted_mode. > >

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add primary plane to mask if it's visible

On Fri, Sep 25, 2015 at 02:11:46PM +0300, Jani Nikula wrote: > On Wed, 23 Sep 2015, Maarten Lankhorst > wrote: > > This fixes the warnings like > > > > "plane A assertion failure, should be disabled but not" > > > > that on the initial modeset during boot. This

Re: [Intel-gfx] [PATCH 3/7] drm/i915: don't allocate fbcon from stolen memory if it's too big

On Wed, Sep 23, 2015 at 05:54:25PM +0100, Chris Wilson wrote: > On Wed, Sep 23, 2015 at 12:52:23PM -0300, Paulo Zanoni wrote: > > Technology has evolved and now we have eDP panels with 3200x1800 > > resolution. In the meantime, the BIOS guys didn't change the default > > 32mb for stolen memory. On

Re: [Intel-gfx] [PATCH 4/7] drm/i915: export size_is_valid() from __intel_fbc_update()

On Wed, Sep 23, 2015 at 06:09:04PM +0100, Chris Wilson wrote: > s/Export/Extract/ > > Export made me think you wanted to use it from another file. > > On Wed, Sep 23, 2015 at 12:52:24PM -0300, Paulo Zanoni wrote: > > Make the giant function a little less giant > > ...and make it a little more

Re: [Intel-gfx] [PATCH 3/7] drm/i915: don't allocate fbcon from stolen memory if it's too big

On Mon, Sep 28, 2015 at 10:54:59AM +0200, Daniel Vetter wrote: > On Wed, Sep 23, 2015 at 05:54:25PM +0100, Chris Wilson wrote: > > On Wed, Sep 23, 2015 at 12:52:23PM -0300, Paulo Zanoni wrote: > > > Technology has evolved and now we have eDP panels with 3200x1800 > > > resolution. In the meantime,

Re: [Intel-gfx] [RFC] Docs: drm: Move KMS properties table out to source files

On Tue, 2015-09-22 at 16:03 -0300, Danilo Cesar Lemes de Paula wrote: > On 09/22/2015 07:22 AM, Graham Whaley wrote: > > On Wed, Sep 02, 2015 at 02:50:52PM +0100, Graham Whaley wrote: > > > > (RFC/test - not for merging) > > > > The below is a test of moving the large HTML KMS properties > > > >

Re: [Intel-gfx] [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

On Fri, 25 Sep 2015, Ville Syrjälä wrote: > On Fri, Sep 25, 2015 at 02:33:38PM +0100, Arun Siluvery wrote: >> Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no >> name >> as they are part of same register. This will save an entry in WA

Re: [Intel-gfx] [PATCH 7/7] drm/i915: extract fbc_supported()

On Wed, Sep 23, 2015 at 06:01:15PM +0100, Chris Wilson wrote: > On Wed, Sep 23, 2015 at 12:52:27PM -0300, Paulo Zanoni wrote: > > Make it clear that we're checking whether FBC is supported or not. The > > fact that the vfunc is not NULL is just a consequence. > > > > Another name option would

[Intel-gfx] [PATCH] drm/i915: Allow DMA pagetables to use highmem

As we never need to directly access the pages we allocate for scratch and the pagetables, and always remap them into the GTT through the dma remapper, we do not need to limit the allocations to lowmem i.e. we can pass in the __GFP_HIGHMEM flag to the page allocation. For backwards compatibility,

Re: [Intel-gfx] [PATCH 2/7] drm/i915: don't use the first stolen page on Broadwell

On Wed, Sep 23, 2015 at 05:55:14PM +0100, Chris Wilson wrote: > On Wed, Sep 23, 2015 at 12:52:22PM -0300, Paulo Zanoni wrote: > > The spec says we just can't use it. > > > > v2: > > - Add WA name (Ville). > > - Add a big comment explaining that we still didn't fix the problem > > where we

[Intel-gfx] [PATCH] drm/i915: Add hot_plug hook for hdmi encoder

This patch adds a separate probe function for HDMI EDID read over DDC channel. This function has been registered as a .hot_plug handler for HDMI encoder. The current implementation of hdmi_detect() function re-sets the cached HDMI edid (in connector->detect_edid) in every detect call.This

Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating

On 28/09/2015 09:44, Jani Nikula wrote: On Fri, 25 Sep 2015, Arun Siluvery wrote: Dropping it because it is for pre-production stepping. Hum, why have we added a pre-pro w/a without a stepping check... should we backport this to stable kernels? What's the

[Intel-gfx] [PATCH v4 2/2] drm/dp: Add a drm_aux-dev module for reading/writing dpcd registers.

This module is heavily based on i2c-dev. Once loaded, it provides one dev node per DP AUX channel, named drm_dp_auxN, where N is an integer. It's possible to know which connector owns this aux channel by looking at the respective sysfs /sys/class/drm_aux_dev/drm_dp_auxN/connector, if the

[Intel-gfx] [PATCH v4 1/2] drm/dp: Store the drm_connector device pointer on the helper.

This is useful to determine which connector owns this AUX channel. Signed-off-by: Rafael Antognolli --- drivers/gpu/drm/i915/intel_dp.c | 1 + include/drm/drm_dp_helper.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c

[Intel-gfx] [PATCH v4 0/2] Add drm_dp_aux chardev support.

This series implement support to a drm_dp_aux chardev that allows reading and writing an arbitrary amount of bytes to arbitrary dpcd register addresses using regular read, write and lseek operations. v2: - lseek is used to select the register to read/write - read/write are used instead of ioctl

[Intel-gfx] [PATCH i-g-t] tests: Adding kms_dp_aux_dev test.

This new test makes some basic testing on the proposed drm_dp_aux_dev interface. If the feature is enabled and the drm_dp_aux_dev class is present, it will check for available DP aux channels and test them for: - basic seek to 0 and read 1 byte - seek to the last address and read,

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