Re: [Intel-gfx] [PATCH] igt/kms_addfb_basic: New subtest to check for fb modifier and tiling mode mismatch

Hi Tvrtko, On Wed, 7 Oct 2015 15:07:30 +0100 Tvrtko Ursulin wrote: > > Hi, > > On 07/10/15 03:35, Vivek Kasireddy wrote: > > This new subtest will validate a Y-tiled object's tiling mode > > against its associated fb modifier. > > > > Cc: Tvrtko Ursulin

[Intel-gfx] NUC5i7RYH compatibly

Hi all, I recently purchased one of these NUCs to use as a general purpose server and stream some Steam games to my living room and need some help getting setup. I heard Ubuntu was what they developed Steam for Linux on, so I started by installing Ubuntu 15.04 and then tried the Intel Graphics

[Intel-gfx] [PATCH] drm/i915: 4K audio N value incorrect at 29.97 and 23.98 refresh rate

From: Clint Taylor The TMDS_296M define was computing as 296704 but the mode->clock is 296700 as defined by EDID. Adjusted define to allow correct detection of the need to program the correct N value for 29.97 and 23.98 refresh rate. Signed-off-by: Clint Taylor

Re: [Intel-gfx] [PATCH] drm/i915/skl: Init cdclk in the driver rather than relying on pre-os

On 10/06/2015 06:55 PM, Ville Syrjälä wrote: On Tue, Oct 06, 2015 at 06:13:52PM +0530, Kumar, Shobhit wrote: On 10/06/2015 05:49 PM, Daniel Vetter wrote: On Tue, Oct 06, 2015 at 02:41:44PM +0300, Ville Syrjälä wrote: On Tue, Oct 06, 2015 at 01:19:52PM +0200, Daniel Vetter wrote: On Tue, Oct

Re: [Intel-gfx] [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset

On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote: > @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > + intel_wa_init(_priv->mmio_workarounds); > + > if

[Intel-gfx] [PATCH 1/3] drm/i915/snb: remove pre-production hardware workaround

Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_gem.c | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 52642aff1dab..1e67484fd5dc 100644 ---

[Intel-gfx] [PATCH 2/3] drm/i915/vlv: remove pre-production hardware workaround

Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_gem_gtt.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 620d57e2526b..4e328f71a454 100644 ---

[Intel-gfx] [PATCH 3/3] drm/i915/chv: remove pre-production hardware workarounds

Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_pm.c | 55 + 1 file changed, 22 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 60d120c472ab..598ee4c8d86e

Re: [Intel-gfx] [PATCH 3/5] drm/i915/kbl: Kabylake A0 is based on Skylake H0.

On Wed, 07 Oct 2015, Ben Widawsky wrote: > On Tue, Oct 06, 2015 at 08:51:13PM +, Rodrigo Vivi wrote: >> cc'ing Ben to get his opinion... >> > > Of course anything is possible wrt the delta of KBL features vs SKL. With the > knowledge we have, we can make a pretty educated

Re: [Intel-gfx] [DMC_REDESIGN_V2 07/14] drm/i915/gen9: Simplify csr loading failure printing.

On Tue, Oct 06, 2015 at 12:38:00PM -0700, Marc Herbert wrote: > On 30/09/15 07:28, Imre Deak wrote: > >On ke, 2015-08-26 at 16:58 +0530, Animesh Manna wrote: > >> > >>-void i915_firmware_load_error_print(const char *fw_path, int err) > >>-{ > >>- DRM_ERROR("failed to load firmware %s (%d)\n",

Re: [Intel-gfx] [PATCH 3/3] drm/i915: add DOC for i915_component

Hi all, Any comments? Thanks. Regards, Libin > -Original Message- > From: Yang, Libin > Sent: Thursday, October 01, 2015 5:01 PM > To: intel-gfx@lists.freedesktop.org; daniel.vet...@ffwll.ch; > jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com > Cc: Yang, Libin > Subject:

Re: [Intel-gfx] [PATCH 3/3] drm/i915: add DOC for i915_component

Hi Daniel, > -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of > Daniel Vetter > Sent: Wednesday, October 07, 2015 9:39 PM > To: Yang, Libin > Cc: intel-gfx@lists.freedesktop.org; daniel.vet...@ffwll.ch; > jani.nik...@linux.intel.com;

[Intel-gfx] [v2] drm/i915/skl: Init cdclk in the driver rather than relying on pre-os

Reuse what is programmed by pre-os, but in case there is no pre-os initialization, init the cdclk with the max value by default untill dynamic cdclk support comes. v2: Check if BIOS programmed correctly rather than always calling init - Do validation of programmed cdctl and what it is

[Intel-gfx] [PATCH v2 i-g-t] kms_rotation_crc: Exercise page flips with 90 degree rotation

From: Tvrtko Ursulin Do some page flipping on the rotated plane just to exercise that code path. v2: Actually render to flip fb and fixed flip counter. Signed-off-by: Tvrtko Ursulin Cc: Sonika Jindal Cc: Arun R

[Intel-gfx] [PATCH 3/6] drm/i915: Hook up ring workaround writes at context creation time on Gen6-7.

intel_rcs_ctx_init() emits all workaround register writes on the list to the ring, in addition to calling i915_gem_render_state_init(). The workaround list is currently empty on Gen6-7 so this shouldn't cause any functional changes. Signed-off-by: Francisco Jerez --- This

[Intel-gfx] [PATCH 2/6] drm/i915: Don't warn if the workaround list is empty.

It's not an error for the workaround list to be empty if no workarounds are needed. This will avoid spamming the logs unnecessarily on Gen6 after the workaround list is hooked up on pre-Gen8 hardware by the following commits. Signed-off-by: Francisco Jerez ---

[Intel-gfx] [PATCH 1/6] drm/i915: Implement L3 partitioning set-up from the workaround list.

This programs the L3 configuration based on the sizes given for each partition as arguments. The relevant register writes are added to the workaround list so that they are re-applied to each context while it's initialized, preventing state leaks from other userspace processes which may have

[Intel-gfx] [PATCH 5/6] drm/i915/hsw: Move L3 atomics workaround to the workaround list.

This makes sure that the workaround is not accidentally undone by some process (which is possible because the HSW_SCRATCH1 and HSW_ROW_CHICKEN3 registers are partially whitelisted), what could cause the next context to be created to hang if it wasn't expecting L3 atomics to be enabled.

[Intel-gfx] [PATCH 6/6] drm/i915/vlv: Remove WaIncreaseL3CreditsForVLVB0 from init_clock_gating.

The same work-arond is applied per-context in init_l3_partitioning_workarounds(), so the direct MMIO write of GEN7_L3SQCREG1 should be redundant now. Applying the work-around at context creation time also makes sure that the MMIO writes are not accidentally undone by userspace. Signed-off-by:

[Intel-gfx] [PATCH 4/6] drm/i915: Program the L3 configuration to hardware defaults on context init.

Use init_l3_partitioning_workarounds() to set up the L3 partitioning on context creation according to the hardware boot-up defaults for each device. Signed-off-by: Francisco Jerez --- drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++-- 1 file

Re: [Intel-gfx] [PATCH] drm: Check fb against plane size rather than CRTC mode for pageflip

On Tue, Oct 06, 2015 at 05:02:47PM -0700, Matt Roper wrote: > The legacy pageflip ioctl calls drm_crtc_check_viewport() to determine > whether the framebuffer being flipped is big enough to fill the display > it is being flipped to. However some drivers support "windowing" of > their primary

Re: [Intel-gfx] [PATCH] drm/i915: Consider plane rotation when calculating stride in skl_do_mmio_flip

On 10/7/2015 3:31 PM, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Previously rotation was ignored and wrong stride programmed into the plane registers resulting in a corrupt image on screen. Signed-off-by: Tvrtko Ursulin Cc: Sonika Jindal

[Intel-gfx] [PATCH] drm/i915: Consider plane rotation when calculating stride in skl_do_mmio_flip

From: Tvrtko Ursulin Previously rotation was ignored and wrong stride programmed into the plane registers resulting in a corrupt image on screen. Signed-off-by: Tvrtko Ursulin Cc: Sonika Jindal ---

Re: [Intel-gfx] [PATCH 1/3] drm: Track drm_mm nodes with an interval tree

Hi On Tue, Oct 6, 2015 at 1:19 PM, Chris Wilson wrote: > On Tue, Oct 06, 2015 at 01:11:56PM +0200, Daniel Vetter wrote: >> On Tue, Oct 06, 2015 at 11:53:09AM +0100, Chris Wilson wrote: >> > In addition to the last-in/first-out stack for accessing drm_mm nodes, >> > we

Re: [Intel-gfx] [PATCH] drm/i915: Consider plane rotation when calculating stride in skl_do_mmio_flip

Hi Tvrtko, [auto build test ERROR on v4.3-rc4 -- if it's inappropriate base, please ignore] config: x86_64-randconfig-x013-201540 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>):

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote: > Hi, > > This issue is still present in 4.3-rc4. > > On 9/24/15, Nick Bowler wrote: > > Testing out 4.3-rc2, first thing I notice is that the VGA output is > > not working. Specifically, the display is

Re: [Intel-gfx] [PATCH 1/1] drm/i915/bxt: Set time interval unit to 0.833us

On Tue, Oct 06, 2015 at 09:16:28PM +0300, Imre Deak wrote: > On pe, 2015-09-18 at 23:39 +0530, Sagar Arun Kamble wrote: > > From: Akash Goel > > > > Signed-off-by: Ankitprasad Sharma > > Signed-off-by: Akash Goel > >

Re: [Intel-gfx] [PATCH v2] drm/i915: set proper N/CTS in modeset

On Fri, Sep 25, 2015 at 10:11 AM, Takashi Iwai wrote: > On Fri, 25 Sep 2015 10:01:48 +0200, > Jani Nikula wrote: >> >> On Fri, 25 Sep 2015, libin.y...@intel.com wrote: >> > From: Libin Yang >> > >> > When modeset occurs and the TMDS frequency is set to some

Re: [Intel-gfx] [PATCH 1/3] drm/i915/snb: remove pre-production hardware workaround

On Wed, Oct 07, 2015 at 11:17:44AM +0300, Jani Nikula wrote: > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_gem.c | 18 +- > 1 file changed, 1 insertion(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Implement L3 partitioning set-up from the workaround list.

Chris Wilson writes: > On Wed, Oct 07, 2015 at 02:44:00PM +0300, Francisco Jerez wrote: >> This programs the L3 configuration based on the sizes given for each >> partition as arguments. The relevant register writes are added to the >> workaround list so that they are

Re: [Intel-gfx] [PATCH 3/3] drm/i915: add DOC for i915_component

On Wed, Oct 07, 2015 at 07:47:09AM +, Yang, Libin wrote: > Hi all, > > Any comments? Thanks. Was simply held up with some merge ordering troubles, I had to wait for Takashi to apply the last patch so I could do a backmerge. And then I forget about your patch series, thanks a lot for the

Re: [Intel-gfx] [PATCH] drm/i915: Consider plane rotation when calculating stride in skl_do_mmio_flip

On 07/10/15 13:10, Jindal, Sonika wrote: On 10/7/2015 3:31 PM, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Previously rotation was ignored and wrong stride programmed into the plane registers resulting in a corrupt image on screen. Signed-off-by: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH 3/3] drm/i915/chv: remove pre-production hardware workarounds

On Wed, Oct 07, 2015 at 11:17:46AM +0300, Jani Nikula wrote: > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_pm.c | 55 > + > 1 file changed, 22 insertions(+), 33 deletions(-) > > diff --git

Re: [Intel-gfx] [PATCH 1/5] drm/i915/kbl: Add Kabylake PCI ID

On Tue, Oct 06, 2015 at 05:31:30PM +, Vivi, Rodrigo wrote: > On Tue, 2015-10-06 at 12:09 +0300, Jani Nikula wrote: > > On Tue, 06 Oct 2015, Rodrigo Vivi wrote: > > > From: Deepak S > > > > > > v2: separate out device info into different GT

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Kill DRI1 cliprects

On Tue, Oct 06, 2015 at 04:37:13PM +0100, Chris Wilson wrote: > On Tue, Oct 06, 2015 at 03:19:36PM +0100, Tvrtko Ursulin wrote: > > > > On 06/10/15 11:39, Chris Wilson wrote: > > >Passing cliprects into the kernel for it to re-execute the batch buffer > > >with different CMD_DRAWRECT died out

Re: [Intel-gfx] [PATCH] igt/kms_addfb_basic: New subtest to check for fb modifier and tiling mode mismatch

Hi, On 07/10/15 03:35, Vivek Kasireddy wrote: This new subtest will validate a Y-tiled object's tiling mode against its associated fb modifier. Cc: Tvrtko Ursulin Signed-off-by: Vivek Kasireddy --- tests/kms_addfb_basic.c | 9 +

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Add a tracepoint for the shrinker

On Tue, Oct 06, 2015 at 02:16:56PM +0100, Chris Wilson wrote: > On Tue, Oct 06, 2015 at 02:54:25PM +0200, Daniel Vetter wrote: > > On Thu, Oct 01, 2015 at 12:18:26PM +0100, Chris Wilson wrote: > > > Often it is very useful to know why we suddenly purge vast tracts of > > > memory and surprisingly

Re: [Intel-gfx] [PATCH 1/1] drm/i915/bxt: Set time interval unit to 0.833us

On Wed, Oct 07, 2015 at 04:35:51PM +0300, Imre Deak wrote: > On ke, 2015-10-07 at 15:29 +0200, Daniel Vetter wrote: > > On Tue, Oct 06, 2015 at 09:16:28PM +0300, Imre Deak wrote: > > > On pe, 2015-09-18 at 23:39 +0530, Sagar Arun Kamble wrote: > > > > From: Akash Goel > > >

Re: [Intel-gfx] [PATCH 2/3] drm/i915/vlv: remove pre-production hardware workaround

On Wed, Oct 07, 2015 at 11:17:45AM +0300, Jani Nikula wrote: > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 7 --- > 1 file changed, 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c >

Re: [Intel-gfx] [PATCH 1/1] drm/i915/bxt: Set time interval unit to 0.833us

On ke, 2015-10-07 at 15:29 +0200, Daniel Vetter wrote: > On Tue, Oct 06, 2015 at 09:16:28PM +0300, Imre Deak wrote: > > On pe, 2015-09-18 at 23:39 +0530, Sagar Arun Kamble wrote: > > > From: Akash Goel > > > > > > Signed-off-by: Ankitprasad Sharma

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Avoid GPU stalls from kswapd

On Tue, Oct 06, 2015 at 02:18:34PM +0100, Chris Wilson wrote: > On Tue, Oct 06, 2015 at 03:01:45PM +0200, Daniel Vetter wrote: > > On Thu, Oct 01, 2015 at 12:18:29PM +0100, Chris Wilson wrote: > > > Exclude active GPU pages from the purview of the background shrinker > > > (kswapd), as these cause

Re: [Intel-gfx] [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset

On Wed, Oct 07, 2015 at 09:43:07AM +0100, Chris Wilson wrote: > On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote: > > @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv = dev->dev_private; > > > > +

Re: [Intel-gfx] [PATCH 1/2] drm/i915/skl: Allow universal planes to position

On Tue, Oct 06, 2015 at 07:28:10PM +0300, Ville Syrjälä wrote: > On Tue, Oct 06, 2015 at 08:16:19AM -0700, Matt Roper wrote: > > On Tue, Oct 06, 2015 at 05:42:42PM +0300, Ville Syrjälä wrote: > > > On Tue, Oct 06, 2015 at 07:29:54AM -0700, Matt Roper wrote: > > > > On Tue, Oct 06, 2015 at

Re: [Intel-gfx] [PATCH 6/9] drm/i915: driver based PASID handling

On 10/07/2015 06:00 AM, David Woodhouse wrote: > On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote: >> + >> + ret = handle_mm_fault(mm, vma, address, >> + desc.wr_req ? FAULT_FLAG_WRITE : 0); >> + if (ret & VM_FAULT_ERROR) { >> +

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote: > On 10/7/15, Ville Syrjälä wrote: > > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote: > >> On 9/24/15, Nick Bowler wrote: > >> > Testing out 4.3-rc2, first thing I notice

Re: [Intel-gfx] [PATCH] drm/i915: Set mode->crtc_clock during hardware state readout

On Wed, Oct 07, 2015 at 04:26:03PM +0200, Daniel Vetter wrote: > On Tue, Oct 06, 2015 at 09:26:31AM -0700, Matt Roper wrote: > > intel_mode_from_pipe_config() fills in a mode structure from the CRTC > > state that was read out of the hardware, but does not set the > > .crtc_clock field (it only

Re: [Intel-gfx] [PATCH 2/3] drm/i915/vlv: remove pre-production hardware workaround

On Wed, Oct 07, 2015 at 04:30:06PM +0200, Daniel Vetter wrote: > On Wed, Oct 07, 2015 at 04:27:24PM +0300, Ville Syrjälä wrote: > > On Wed, Oct 07, 2015 at 11:17:45AM +0300, Jani Nikula wrote: > > > Signed-off-by: Jani Nikula > > > --- > > >

Re: [Intel-gfx] [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset

On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote: > From: Mika Kuoppala > > Rewrite everything in mmio workaround list right after > gpu reset. This ensures that we start the reinitialization > with proper mmio workarounds in place, before we > start the

Re: [Intel-gfx] [PATCH 07/12] drm/i915: Write mmio workarounds after gpu reset

On Wed, Oct 07, 2015 at 04:52:54PM +0300, Ville Syrjälä wrote: > On Wed, Oct 07, 2015 at 09:43:07AM +0100, Chris Wilson wrote: > > On Tue, Oct 06, 2015 at 05:26:48PM +0300, Mika Kuoppala wrote: > > > @@ -6973,8 +6989,12 @@ void intel_init_clock_gating(struct drm_device > > > *dev) > > > { > > >

Re: [Intel-gfx] [PATCH] drm/i915: Set mode->crtc_clock during hardware state readout

On Tue, Oct 06, 2015 at 09:26:31AM -0700, Matt Roper wrote: > intel_mode_from_pipe_config() fills in a mode structure from the CRTC > state that was read out of the hardware, but does not set the > .crtc_clock field (it only sets the .clock). This causes the subsequent > call to

Re: [Intel-gfx] [PATCH 2/3] drm/i915/vlv: remove pre-production hardware workaround

On Wed, Oct 07, 2015 at 04:27:24PM +0300, Ville Syrjälä wrote: > On Wed, Oct 07, 2015 at 11:17:45AM +0300, Jani Nikula wrote: > > Signed-off-by: Jani Nikula > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 7 --- > > 1 file changed, 7 deletions(-) > > > > diff --git

Re: [Intel-gfx] [PATCH 1/5] drm/i915/kbl: Add Kabylake PCI ID

On Wed, Oct 07, 2015 at 03:55:31PM +0200, Daniel Vetter wrote: > On Tue, Oct 06, 2015 at 05:31:30PM +, Vivi, Rodrigo wrote: > > On Tue, 2015-10-06 at 12:09 +0300, Jani Nikula wrote: > > > On Tue, 06 Oct 2015, Rodrigo Vivi wrote: > > > > From: Deepak S

Re: [Intel-gfx] [PATCH] drm/i915: Resurrect golden context on gen6/7

On Thu, Oct 01, 2015 at 07:13:11PM +0300, Francisco Jerez wrote: > Daniel Vetter writes: > > > In > > > > commit 8f0e2b9d95a88ca5d8349deef2375644faf184ae > > Author: Daniel Vetter > > Date: Tue Dec 2 16:19:07 2014 +0100 > > > > drm/i915:

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Don't warn if the workaround list is empty.

On Wed, Oct 07, 2015 at 02:44:01PM +0300, Francisco Jerez wrote: > It's not an error for the workaround list to be empty if no > workarounds are needed. This will avoid spamming the logs > unnecessarily on Gen6 after the workaround list is hooked up on > pre-Gen8 hardware by the following

Re: [Intel-gfx] [PATCH 3/3] drm/i915/chv: remove pre-production hardware workarounds

On Wed, Oct 07, 2015 at 04:28:48PM +0300, Ville Syrjälä wrote: > On Wed, Oct 07, 2015 at 11:17:46AM +0300, Jani Nikula wrote: > > Signed-off-by: Jani Nikula > > --- > > drivers/gpu/drm/i915/intel_pm.c | 55 > > + > > 1 file changed,

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Hook up ring workaround writes at context creation time on Gen6-7.

On Wed, Oct 07, 2015 at 02:44:02PM +0300, Francisco Jerez wrote: > intel_rcs_ctx_init() emits all workaround register writes on the list > to the ring, in addition to calling i915_gem_render_state_init(). The > workaround list is currently empty on Gen6-7 so this shouldn't cause > any functional

Re: [Intel-gfx] [PATCH 6/9] drm/i915: driver based PASID handling

On 10/07/2015 10:17 AM, David Woodhouse wrote: > On Wed, 2015-10-07 at 09:28 -0700, Jesse Barnes wrote: >> On 10/07/2015 09:14 AM, Daniel Vetter wrote: >>> On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote: On 10/07/2015 06:00 AM, David Woodhouse wrote: > On Fri, 2015-09-04 at

Re: [Intel-gfx] [PATCH i-g-t] lib/core: Fix docs for igt_assert_lt(e)

Hi, On 2 October 2015 at 11:56, Daniel Vetter wrote: > Logical negation is hard. > > Cc: "Morton, Derek J" > Signed-off-by: Daniel Vetter Almost identical to what I had locally. s/second integers/second integer/ and:

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Unify execlist and legacy request life-cycles

On Tue, Oct 06, 2015 at 03:52:01PM +0100, Nick Hoath wrote: > There is a desire to simplify the i915 driver by reducing the number of > different code paths introduced by the LRC / execlists support. As the > execlists request is now part of the gem request it is possible and > desirable to unify

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Improve dynamic management/eviction of lrc backing objects

On Tue, Oct 06, 2015 at 03:52:02PM +0100, Nick Hoath wrote: > Shovel all context related objects through the active queue and obj > management. > > - Added callback in vma_(un)bind to add CPU (un)mapping at same time > if desired > - Inserted LRC hw context & ringbuf to vma active list > >

[Intel-gfx] periodic wakeup from DPMS suspend

Hi, I have a NEC EA244WMi monitor connected to an Asus P8H77-V mainboard with Ivy Bridge Core i5-3550 via DVI. If DPMS suspend is enabled (by xscreensaver, or for testing by "xset dpms force off/suspend/standby"), the monitor enters standby mode but wakes up every 10...30 seconds for 6 seconds to

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Drop i915_gem_obj_is_pinned() from set-cache-level

Hi, On 06/10/15 11:39, Chris Wilson wrote: Since the remove of the pin-ioctl, we only care about not changing the cache level on buffers pinned to the hardware as indicated by obj->pin_display. So we can safely replace i915_gem_object_is_pinned() i915_gem_obj_is_pinned here with a plain

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Add the CPU mapping of the hw context to the pinned items.

On Tue, Oct 06, 2015 at 03:52:03PM +0100, Nick Hoath wrote: > Pin the hw ctx mapping so that it is not mapped/unmapped per bb > when doing GuC submission. > > Issue: VIZ-4277 > Cc: David Gordon > Signed-off-by: Nick Hoath > --- >

[Intel-gfx] [PULL] drm-intel-next

Hi Dave, drm-intel-next-2015-09-28: - fastboot by default for some systems (Maarten Lankhorts) - piles of workarounds for bxt and skl - more fbc work from Paulo - fix hdmi hotplug detection (Sonika) - first few patches from Ville to parametrize register macros, prep work for typesafe mmio

Re: [Intel-gfx] periodic wakeup from DPMS suspend

On Tue, Oct 06, 2015 at 11:04:53PM -0400, Alex Deucher wrote: > On Tue, Oct 6, 2015 at 11:10 AM, Johannes Stezenbach wrote: > > > > I have a NEC EA244WMi monitor connected to an Asus P8H77-V > > mainboard with Ivy Bridge Core i5-3550 via DVI. > > If DPMS suspend is enabled (by

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

On 10/7/15, Nick Bowler wrote: > On 10/7/15, Ville Syrjälä wrote: >> On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote: >>> On 10/7/15, Ville Syrjälä wrote: >>> > On Tue, Oct 06, 2015 at 11:42:33AM

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

On 10/7/15, Ville Syrjälä wrote: > On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote: >> On 10/7/15, Ville Syrjälä wrote: >> > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote: >> >> On 9/24/15, Nick Bowler

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

On 10/7/15, Ville Syrjälä wrote: > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote: >> On 9/24/15, Nick Bowler wrote: >> > Testing out 4.3-rc2, first thing I notice is that the VGA output is >> > not working. Specifically, the

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Drop i915_gem_obj_is_pinned() from set-cache-level

On Wed, Oct 07, 2015 at 04:57:25PM +0100, Tvrtko Ursulin wrote: > > Hi, > > On 06/10/15 11:39, Chris Wilson wrote: > >Since the remove of the pin-ioctl, we only care about not changing the > >cache level on buffers pinned to the hardware as indicated by > >obj->pin_display. So we can safely

Re: [Intel-gfx] [PATCH i-g-t] lib/core: Fix docs for igt_assert_lt(e)

On Wed, Oct 07, 2015 at 04:52:46PM +0100, Daniel Stone wrote: > Hi, > > On 2 October 2015 at 11:56, Daniel Vetter wrote: > > Logical negation is hard. > > > > Cc: "Morton, Derek J" > > Signed-off-by: Daniel Vetter > >

Re: [Intel-gfx] [PATCH 6/9] drm/i915: driver based PASID handling

On 10/07/2015 09:14 AM, Daniel Vetter wrote: > On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote: >> On 10/07/2015 06:00 AM, David Woodhouse wrote: >>> On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote: + + ret = handle_mm_fault(mm, vma, address, +

Re: [Intel-gfx] [PATCH 6/9] drm/i915: driver based PASID handling

On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote: > On 10/07/2015 06:00 AM, David Woodhouse wrote: > > On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote: > >> + > >> + ret = handle_mm_fault(mm, vma, address, > >> + desc.wr_req ? FAULT_FLAG_WRITE :

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

On 10/7/15, Ville Syrjälä wrote: > On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote: >> On 10/7/15, Ville Syrjälä wrote: >> > On Tue, Oct 06, 2015 at 11:42:33AM -0400, Nick Bowler wrote: >> >> On 9/24/15, Nick Bowler

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

On Wed, Oct 07, 2015 at 02:50:34PM -0400, Nick Bowler wrote: > On 10/7/15, Ville Syrjälä wrote: > > On Wed, Oct 07, 2015 at 10:29:22AM -0400, Nick Bowler wrote: > >> On 10/7/15, Ville Syrjälä wrote: > >> > On Tue, Oct 06, 2015 at

[Intel-gfx] [PATCH 2/2] drm/i915: Enable DPLL VGA mode before P1/P2 divider write

From: Ville Syrjälä Apparently writing the DPLL register P1/P2 divider fields won't trigger an actual change in the DPLL output unless VGA mode is enabled for prior to the register write that changes the P1/P2 dividers. The write with the new P1/P2 divider can

[Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4

From: Ville Syrjälä We accidentally lost the initial DPLL register write in 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M The "three times for luck" hack probably saved us from a total disaster. But anyway, bring the initial write back so that the code

[Intel-gfx] [PATCH] drm/i915: Pin the ifbdev for the info->system_base GGTT mmapping

From: Chris Wilson A long time ago (before 3.14) we relied on a permanent pinning of the ifbdev to lock the fb in place inside the GGTT. However, the introduction of stealing the BIOS framebuffer and reusing its address in the GGTT for the fbdev has muddied waters and

Re: [Intel-gfx] [PATCH 6/9] drm/i915: driver based PASID handling

On Wed, 2015-10-07 at 09:28 -0700, Jesse Barnes wrote: > On 10/07/2015 09:14 AM, Daniel Vetter wrote: > > On Wed, Oct 07, 2015 at 08:16:42AM -0700, Jesse Barnes wrote: > > > On 10/07/2015 06:00 AM, David Woodhouse wrote: > > > > On Fri, 2015-09-04 at 09:59 -0700, Jesse Barnes wrote: > > > > > + >