[Intel-gfx] [PATCH v2] drm/i915/skl/kbl: Add support for pipe fusing

On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply decrease info->num_pipes if we find a valid fused out config. v2: Don't store the pipe disabled mask in device info (Damien) Signed-off-by: Patrik

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

On Monday, January 18, 2016 02:31:00 PM Ankitprasad Sharma wrote: > On Fri, 2016-01-15 at 15:51 +0100, Rafael J. Wysocki wrote: > > On Thursday, January 14, 2016 11:46:46 AM ankitprasad.r.sha...@intel.com > > wrote: > > > From: Ankitprasad Sharma > > > > > > Some

Re: [Intel-gfx] [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback

Hi guys, On 15/01/16 10:59, Nick Hoath wrote: > On 14/01/2016 12:37, Nick Hoath wrote: >> On 14/01/2016 12:31, Chris Wilson wrote: >>> On Thu, Jan 14, 2016 at 11:56:07AM +, Nick Hoath wrote: On 14/01/2016 11:36, Chris Wilson wrote: > On Wed, Jan 13, 2016 at 04:19:45PM +, Nick

Re: [Intel-gfx] [PATCH] drm/i915: skl_update_scaler() wants a rotation bitmask instead of bit number

On Fri, Jan 15, 2016 at 03:15:00PM -0800, Matt Roper wrote: > On Fri, Jan 15, 2016 at 08:48:26PM +0200, Ville Syrjälä wrote: > > On Thu, Oct 15, 2015 at 05:01:58PM +0300, ville.syrj...@linux.intel.com > > wrote: > > > From: Ville Syrjälä > > > > > > Pass

Re: [Intel-gfx] [PATCH] drm/i915: Don't reject primayr plane windowing with color keying enabled on SKL+

On Fri, Jan 15, 2016 at 03:22:08PM -0800, Matt Roper wrote: > On Fri, Jan 15, 2016 at 08:46:53PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > On SKL+ plane scaling is mutually exclusive with color keying. The code > > check for this,

Re: [Intel-gfx] [PATCH] drm/i915: Don't reject primayr plane windowing with color keying enabled on SKL+

On Mon, Jan 18, 2016 at 04:20:29PM +0200, Ville Syrjälä wrote: > On Fri, Jan 15, 2016 at 03:22:08PM -0800, Matt Roper wrote: > > On Fri, Jan 15, 2016 at 08:46:53PM +0200, ville.syrj...@linux.intel.com > > wrote: > > > From: Ville Syrjälä > > > > > > On SKL+ plane

Re: [Intel-gfx] [PATCH] drm/i915: Drop ilk_wm_max_level()

On Mon, Dec 21, 2015 at 11:32:50AM -0800, Matt Roper wrote: > Storing the max_level in dev_priv as VLV/CHV already do is a bit simpler > than calling this standalone function, especially since some of the > callsites need to special-case the call to check whether they're running > on VLV/CHV. > >

[Intel-gfx] ✗ Fi.CI.BAT: failure for Fixing sink count related detection over (rev8)

== Summary == HEAD is now at 2dd73be drm-intel-nightly: 2016y-01m-18d-09h-59m-27s UTC integration manifest Applying: drm/i915: Splitting intel_dp_detect Applying: drm/i915: Cleaning up intel_dp_hpd_pulse Applying: drm/i915: Splitting intel_dp_check_link_status Applying: drm/i915: Save sink_count

Re: [Intel-gfx] [BXT DSI timing fixes v1 3/3] drm/i915/bxt: Fixed dsi enc disable and blank at bootup

I applied this patch for testing BXT-M I received this error message [ 16.276906] Hardware name: Intel Corp. Broxton M/RVP, BIOS BXTM_IFWI_X64_R_2015_49_2_03 11/25/2015 [ 16.286793] task: 8801795a2640 ti: 88017830 task.ti: 88017830 [ 16.295047] RIP: 0010:[] []

Re: [Intel-gfx] [BXT DSI timing fixes v1 2/3] drm/i915/bxt: Get pipe timing for BXT DSI

On Mon, 2015-10-12 at 22:55 +0530, Uma Shankar wrote: > For BXT DSI, vtotal, vactive, hactive registers are different. > Making changes to intel_crtc_mode_get() and get_pipe_timings(), > to read the correct registers for BXT DSI. > Tested-by: Mika Kahola > Signed-off-by:

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Remove intel_crtc->atomic.disable_ips.

Hi, On 18 January 2016 at 12:10, Maarten Lankhorst wrote: > Op 13-01-16 om 14:02 schreef Ville Syrjälä: >> Also I'm not sure it isn't a step backwards. Based on the spec we should >> be able to keep IPS enabled as long as one plane (possibly referring to >>

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Don't reject primayr plane windowing with color keying enabled on SKL+

On Sat, Jan 16, 2016 at 08:20:49AM -, Patchwork wrote: > == Summary == > > Built on 0ea9000bcb6f394edde5111494a92b0607214cfa drm-intel-nightly: > 2016y-01m-15d-19h-09m-45s UTC integration manifest > > Test gem_storedw_loop: > Subgroup basic-render: > dmesg-warn ->

[Intel-gfx] [PATCH] drm/i915/skl/kbl: Add support for pipe fusing

On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are several registers that can contain fuse settings so to simplify things we keep around a mask in device info with bits for each disabled pipe. This will also

[Intel-gfx] [PATCH] i915/guc: Add Kabylake GuC Loading

This patch added the loading of the GuC for Kabylake. It loads a 2.4 firmware. Signed-off-by: Peter Antoine Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_guc_loader.c | 6 ++ 1 file changed, 6 insertions(+) diff --git

Re: [Intel-gfx] [PATCH 5/6] drm/i915: read sink_count dpcd always

On Mon, 2016-01-18 at 18:14 +0530, Shubhangi Shrivastava wrote: > > On Thursday 14 January 2016 06:34 PM, Ander Conselvan De Oliveira wrote: > > On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote: > > > This patch reads sink_count dpcd always and removes its > > > read operation based

Re: [Intel-gfx] [PATCH v2 4/6] drm/i915: Harden detection of missed interrupts

Chris Wilson writes: > Only declare a missed interrupt if we find that the GPU is idle with > waiters and a hangcheck interval has passed in which no new user > interrupts have been raised. > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/guc: Add Kabylake GuC Loading

== Summary == Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: pass -> DMESG-WARN (skl-i5k-2) UNSTABLE dmesg-warn -> PASS

Re: [Intel-gfx] [PATCH v2 4/6] drm/i915: Harden detection of missed interrupts

On Mon, Jan 18, 2016 at 03:07:16PM +0200, Mika Kuoppala wrote: > Chris Wilson writes: > > > Only declare a missed interrupt if we find that the GPU is idle with > > waiters and a hangcheck interval has passed in which no new user > > interrupts have been raised. > > > >

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/skl/kbl: Add support for pipe fusing (rev2)

== Summary == Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest Test gem_ctx_basic: pass -> FAIL (bdw-ultra) Test gem_storedw_loop: Subgroup basic-render: pass ->

[Intel-gfx] [PATCH] drm/i915: fix itnull.cocci warnings (fwd)

List_for_each entry binds its first argument to an offset from the list pointer, so this should not be NULL. Generated by: scripts/coccinelle/iterators/itnull.cocci Signed-off-by: Fengguang Wu --- Please take the patch only if it's a positive warning. Thanks!

[Intel-gfx] ✗ Fi.CI.BAT: failure for Support blending modes of display planes

== Summary == HEAD is now at 9fe57ae drm-intel-nightly: 2016y-01m-18d-06h-56m-50s UTC integration manifest Applying: drm: Introduce the blend-func property Applying: drm/i915/skl: Add blend_func to SKL/BXT sprite planes Applying: drm: Introduce DRM_MODE_COLOR() Applying: drm: Add an blend_color

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Do not call API requiring struct_mutex where it is not available (rev3)

On 16/01/16 07:49, Patchwork wrote: == Summary == Built on 0ea9000bcb6f394edde5111494a92b0607214cfa drm-intel-nightly: 2016y-01m-15d-19h-09m-45s UTC integration manifest Test gem_ctx_basic: pass -> FAIL (bdw-ultra) Test gem_storedw_loop: Subgroup

Re: [Intel-gfx] [PATCH] magic-clflush-fix

On Mon, Jan 18, 2016 at 08:58:01AM +, Chris Wilson wrote: Nothing to see here, please move along. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org

[Intel-gfx] [PATCH] drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists

Broadwell and later currently use the same unordered command sequence to update the seqno in the HWS status page and then assert the user interrupt. We should apply the w/a from legacy (where we do an mmio read to delay the seqno read after the interrupt), but this is not enough to enforce

Re: [Intel-gfx] [PATCH] drm/i915: Don't do pre plane update on disabled crtcs

Op 14-01-16 om 17:52 schreef Ville Syrjälä: > On Thu, Jan 14, 2016 at 06:32:10PM +0200, Mika Kuoppala wrote: >> CI/Bat got following (shortened) trace on byt and also >> on bsw: >> >> [ cut here ]--- >> Unclaimed register detected before reading register 0x186500 >> Call Trace:

[Intel-gfx] [PATCH] magic-clflush-fix

--- drivers/gpu/drm/i915/i915_gem.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6b37cdd7d2e3..cbcbb0c2b8e3 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c

Re: [Intel-gfx] [PATCH] drm/i915: Don't reject primayr plane windowing with color keying enabled on SKL+

Op 15-01-16 om 19:46 schreef ville.syrj...@linux.intel.com: > From: Ville Syrjälä > > On SKL+ plane scaling is mutually exclusive with color keying. The code > check for this, but during some refactoring the code got changed to > also reject primary plane windowing

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ (rev8)

== Summary == HEAD is now at 8114b00 drm-intel-nightly: 2016y-01m-18d-08h-02m-22s UTC integration manifest Applying: drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+ Applying: drm/i915: Separate out the seqno-barrier from engine->get_seqno Repository lacks necessary blobs

[Intel-gfx] [PATCH] drm/i915: Splitting intel_dp_check_link_status

When created originally intel_dp_check_link_status() was supposed to handle only link training for short pulse but has grown into handler for short pulse itself. This patch cleans up this function by splitting it into two halves. First intel_dp_short_pulse() is called, which will be entry point

[Intel-gfx] ✗ Fi.CI.BAT: warning for Fixing sink count related detection over (rev6)

== Summary == Built on 2dd73bef9cf525196545f96aa8cb42053620f2e6 drm-intel-nightly: 2016y-01m-18d-09h-59m-27s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: pass -> DMESG-WARN (bdw-nuci7) UNSTABLE Test kms_pipe_crc_basic: Subgroup

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

On Fri, 2016-01-15 at 15:51 +0100, Rafael J. Wysocki wrote: > On Thursday, January 14, 2016 11:46:46 AM ankitprasad.r.sha...@intel.com > wrote: > > From: Ankitprasad Sharma > > > > Some modules, like i915.ko, needs to detect when certain ACPI features > > are

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Fix a memory leak where guc->execbuf_client is not freed

On 13/01/16 19:11, Dave Gordon wrote: On 13/01/16 19:01, yu@intel.com wrote: From: Alex Dai During driver unloading, the guc_client created for command submission needs to be released to avoid memory leak. The struct_mutex needs to be held before tearing down GuC. v1:

[Intel-gfx] [PATCH] drm/i915: Splitting intel_dp_detect

intel_dp_detect() is called for not just detection but during modes enumeration as well. Repeating the whole sequence during each of these calls is wasteful and time consuming. This patch moves probing for panel, DPCD read etc done in intel_dp_detect() to a new function intel_dp_long_pulse(). Note

Re: [Intel-gfx] [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback

On 18/01/16 16:53, Chris Wilson wrote: On Mon, Jan 18, 2016 at 03:02:25PM +, Tvrtko Ursulin wrote: - while (!list_empty(>request_list)) { - struct drm_i915_gem_request *request; - - request = list_first_entry(>request_list, -

[Intel-gfx] [PATCH] libdrm_intel: Fix return from drm_intel_gem_bo_busy

From: Tvrtko Ursulin Return path from this function got confused in: commit 02f93c21e6e1c3dad9d99349989daa84a8c0b5fb Author: Eric Anholt Date: Wed Jan 15 00:38:39 2014 -0800 intel: Track whether a buffer is idle to avoid trips to the

Re: [Intel-gfx] [PATCH] drm/i915: fix itnull.cocci warnings (fwd)

I expect this is the script she mentions: https://github.com/coccinelle/coccinellery/blob/master/itnull/itnull.cocci Julia is one of the authors of Coccinelle, and the author of that script :) On 18/01/16 17:20, Daniel Vetter wrote: > On Mon, Jan 18, 2016 at 04:49:06PM +0100, Julia Lawall

Re: [Intel-gfx] [PATCH 21/22] drm/vc4: Nuke preclose hook

Daniel Vetter writes: > Again since the drm core takes care of event unlinking/disarming this > is now just needless code. > > v2: Fixup misplaced hunk. > > Cc: Eric Anholt > Acked-by: Daniel Stone > Reviewed-by: Alex Deucher

Re: [Intel-gfx] [PATCH] drm/i915: fix itnull.cocci warnings (fwd)

On Mon, Jan 18, 2016 at 04:49:06PM +0100, Julia Lawall wrote: > List_for_each entry binds its first argument to an offset from the list > pointer, so this should not be NULL. > > Generated by: scripts/coccinelle/iterators/itnull.cocci > > Signed-off-by: Fengguang Wu >

Re: [Intel-gfx] [PATCH] drm/i915: fix itnull.cocci warnings (fwd)

On Mon, Jan 18, 2016 at 05:42:24PM +, Eric Engestrom wrote: > I expect this is the script she mentions: > https://github.com/coccinelle/coccinellery/blob/master/itnull/itnull.cocci > > Julia is one of the authors of Coccinelle, and the author of that script :) I get how these patches get

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

Hi, On Mon, Jan 18, 2016 at 03:57:29PM +0100, Rafael J. Wysocki wrote: > On Monday, January 18, 2016 02:31:00 PM Ankitprasad Sharma wrote: > > On Fri, 2016-01-15 at 15:51 +0100, Rafael J. Wysocki wrote: > > > On Thursday, January 14, 2016 11:46:46 AM ankitprasad.r.sha...@intel.com > > > wrote: >

[Intel-gfx] ✗ Fi.CI.BAT: failure for Fixing sink count related detection over (rev7)

== Summary == HEAD is now at 2dd73be drm-intel-nightly: 2016y-01m-18d-09h-59m-27s UTC integration manifest Applying: drm/i915: Splitting intel_dp_detect Applying: drm/i915: Cleaning up intel_dp_hpd_pulse Applying: drm/i915: Splitting intel_dp_check_link_status Applying: drm/i915: Save sink_count

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Remove intel_crtc->atomic.disable_ips.

Op 13-01-16 om 14:02 schreef Ville Syrjälä: > On Mon, Jan 11, 2016 at 01:27:43PM +0100, Maarten Lankhorst wrote: >> This is a revert of commit 066cf55b9ce3 "drm/i915: Fix IPS related flicker". >> intel_pre_disable_primary already handles this, and now everything >> goes through the atomic path

Re: [Intel-gfx] [PATCH 5/6] drm/i915: read sink_count dpcd always

On Thursday 14 January 2016 06:34 PM, Ander Conselvan De Oliveira wrote: On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote: This patch reads sink_count dpcd always and removes its read operation based on values in downstream port dpcd. SINK_COUNT dpcd is not dependent on

[Intel-gfx] [PATCH] drm/i915: Save sink_count for tracking changes to it and read sink_count dpcd always

Sink count can change between short pulse hpd hence this patch adds a member variable to intel_dp so we can track any changes between short pulse interrupts. This patch reads sink_count dpcd always and removes its read operation based on values in downstream port dpcd. SINK_COUNT dpcd is not

Re: [Intel-gfx] [PATCH 5/6] drm/i915: read sink_count dpcd always

On Monday 18 January 2016 06:14 PM, Shubhangi Shrivastava wrote: On Thursday 14 January 2016 06:34 PM, Ander Conselvan De Oliveira wrote: On Tue, 2016-01-05 at 18:20 +0530, Shubhangi Shrivastava wrote: This patch reads sink_count dpcd always and removes its read operation based on values

Re: [Intel-gfx] [PATCH] drm/i915/skl/kbl: Add support for pipe fusing

On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote: > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are > several registers that can contain fuse settings so to simplify things > we keep

[Intel-gfx] [PATCH] drm/i915/skl: Tune down DC6 already enabled warning

For unknown reasons the DMC firmware overwrites our DC5/6 bits in the DC_STATE_EN register. This happens from time to time during the igt@kms_flip@basic-flip-vs-dpms test. We manually fix up the register when this occurs and so far that seems to work. This patch demotes the warning to a debug

Re: [Intel-gfx] [PATCH] drm/i915/skl/kbl: Add support for pipe fusing

On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote: > On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote: > > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The > > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are > > several

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915: tidy up a few leftovers

On 07/01/2016 10:20, Dave Gordon wrote: There are a few bits of code which the transformations implemented by the previous patch reveal to be suboptimal, once the notion of a per- ring default context has gone away. So this tidies up the leftovers. It could have been squashed into the previous

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC

== Summary == Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: pass -> DMESG-WARN (skl-i5k-2) UNSTABLE pass -> DMESG-WARN

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/skl: Tune down DC6 already enabled warning

== Summary == Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest Test gem_ctx_basic: pass -> FAIL (bdw-ultra) Test gem_storedw_loop: Subgroup basic-render: pass ->

Re: [Intel-gfx] [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback

On Mon, Jan 18, 2016 at 03:02:25PM +, Tvrtko Ursulin wrote: > - while (!list_empty(>request_list)) { > - struct drm_i915_gem_request *request; > - > - request = list_first_entry(>request_list, > - struct

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915: abolish separate per-ring default_context pointers

On 07/01/2016 10:20, Dave Gordon wrote: Now that we've eliminated a lot of uses of ring->default_context, we can eliminate the pointer itself. All the engines share the same default intel_context, so we can just keep a single reference to it in the dev_priv structure rather than one in each of

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC

On 18/01/2016 16:20, Patchwork wrote: == Summary == Built on 98ee62c2326e0b6881eb0f427895aab745febf6f drm-intel-nightly: 2016y-01m-18d-14h-18m-27s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: pass -> DMESG-WARN (skl-i5k-2) UNSTABLE

[Intel-gfx] [PATCH] drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC

In GuC submission mode, driver has to provide a list of registers to be save/restored during gpu reset, make the max no. of registers value consistent with that of the value defined in FW. If they are not in sync then register save/restore during gpu reset won't work as expected. Cc: Alex Dai

[Intel-gfx] [PATCH 1/5 v2] drm/i915: use hlist_for_each_entry

Use hlist_for_each_entry() instead of hlist_for_each() to simplify the code. Signed-off-by: Geliang Tang --- Changes in v2: - Keep head = >buckets[handle & eb->and] --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-)

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: simplify allocation of driver-internal requests

On 07/01/2016 10:20, Dave Gordon wrote: There are a number of places where the driver needs a request, but isn't working on behalf of any specific user or in a specific context. At present, we associate them with the per-engine default context. A future patch will abolish those per-engine

Re: [Intel-gfx] [PATCH 1/5 v2] drm/i915: use hlist_for_each_entry

On Mon, Jan 18, 2016 at 11:54:20PM +0800, Geliang Tang wrote: > Use hlist_for_each_entry() instead of hlist_for_each() to simplify > the code. > > Signed-off-by: Geliang Tang > --- > Changes in v2: > - Keep head = >buckets[handle & eb->and] Queued for -next, thanks for the

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

On Tuesday, January 19, 2016 12:00:47 AM Lukas Wunner wrote: > Hi, > > On Mon, Jan 18, 2016 at 11:46:18PM +0100, Rafael J. Wysocki wrote: > > On Monday, January 18, 2016 11:39:07 PM Lukas Wunner wrote: [cut] > > > > > If you want to check if the device ir present at all, you cen use > > > > >

Re: [Intel-gfx] [PATCH] drm/i915: Splitting intel_dp_check_link_status

On 1/19/2016 2:35 AM, Lukas Wunner wrote: Hi, On Mon, Jan 18, 2016 at 04:22:19PM +0530, Shubhangi Shrivastava wrote: When created originally intel_dp_check_link_status() was supposed to handle only link training for short pulse but has grown into handler for short pulse itself. This patch

Re: [Intel-gfx] [PATCH v10] drm/i915: Extend LRC pinning to cover GPU context writeback

On Mon, Jan 18, 2016 at 05:14:26PM +, Tvrtko Ursulin wrote: > > On 18/01/16 16:53, Chris Wilson wrote: > >On Mon, Jan 18, 2016 at 03:02:25PM +, Tvrtko Ursulin wrote: > >>- while (!list_empty(>request_list)) { > >>- struct drm_i915_gem_request *request; > >>- > >>-

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

Hi, On Mon, Jan 18, 2016 at 11:46:18PM +0100, Rafael J. Wysocki wrote: > On Monday, January 18, 2016 11:39:07 PM Lukas Wunner wrote: > > Hi, > > > > On Mon, Jan 18, 2016 at 11:28:27PM +0100, Rafael J. Wysocki wrote: > > > On Monday, January 18, 2016 03:57:29 PM Rafael J. Wysocki wrote: > > > >

Re: [Intel-gfx] [PATCH] drm/i915: fix itnull.cocci warnings (fwd)

On Mon, 18 Jan 2016, Daniel Vetter wrote: > On Mon, Jan 18, 2016 at 04:49:06PM +0100, Julia Lawall wrote: > > List_for_each entry binds its first argument to an offset from the list > > pointer, so this should not be NULL. > > > > Generated by: scripts/coccinelle/iterators/itnull.cocci > > >

Re: [Intel-gfx] [PATCH] drm/i915: Splitting intel_dp_check_link_status

Hi, On Mon, Jan 18, 2016 at 04:22:19PM +0530, Shubhangi Shrivastava wrote: > When created originally intel_dp_check_link_status() > was supposed to handle only link training for short > pulse but has grown into handler for short pulse itself. > This patch cleans up this function by splitting it

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

On Monday, January 18, 2016 03:57:29 PM Rafael J. Wysocki wrote: > On Monday, January 18, 2016 02:31:00 PM Ankitprasad Sharma wrote: > > On Fri, 2016-01-15 at 15:51 +0100, Rafael J. Wysocki wrote: > > > On Thursday, January 14, 2016 11:46:46 AM ankitprasad.r.sha...@intel.com > > > wrote: > > > >

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

Hi, On Mon, Jan 18, 2016 at 11:28:27PM +0100, Rafael J. Wysocki wrote: > On Monday, January 18, 2016 03:57:29 PM Rafael J. Wysocki wrote: > > On Monday, January 18, 2016 02:31:00 PM Ankitprasad Sharma wrote: > > > On Fri, 2016-01-15 at 15:51 +0100, Rafael J. Wysocki wrote: > > > > On Thursday,

Re: [Intel-gfx] [PATCH 10/11] acpi: Export acpi_bus_type

On Monday, January 18, 2016 11:39:07 PM Lukas Wunner wrote: > Hi, > > On Mon, Jan 18, 2016 at 11:28:27PM +0100, Rafael J. Wysocki wrote: > > On Monday, January 18, 2016 03:57:29 PM Rafael J. Wysocki wrote: > > > On Monday, January 18, 2016 02:31:00 PM Ankitprasad Sharma wrote: > > > > On Fri,