Re: [Intel-gfx] [PATCH v8 1/1] drm/i915/bxt: Check BIOS RC6 setup before enabling RC6

On la, 2016-02-06 at 00:13 +0530, Sagar Arun Kamble wrote: > RC6 setup is shared between BIOS and Driver. BIOS sets up subset of > RC6 > setup registers. If those are not setup Driver should not enable RC6. > For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values > to know if BIOS

Re: [Intel-gfx] [PATCH] drm/i915: Protect fbdev across slow or failed initialisation

Hi Chris, On Fri, Feb 05, 2016 at 11:09:27AM +, Chris Wilson wrote: > On Fri, Feb 05, 2016 at 01:27:10AM +0100, Lukas Wunner wrote: > > On Thu, Feb 04, 2016 at 09:21:17AM +, Li, Weinan Z wrote: > > > We still need this patch. Seems 54632abe8ca3 ("drm/i915: Fix oops caused > > > by fbdev

[Intel-gfx] [PATCH v5 07/11] drm/i915: tidy initialisation failure paths (legacy, part 3)

intel_cleanup_ring_buffer() contains one low-level register access, which is not really appropriate for its level of abstraction. It calls intel_stop_ring_buffer() which then calls stop_ring() -- which is the level that deals with h/w registers -- then reads a GEN-specific register to see whether

[Intel-gfx] [PATCH v5 08/11] drm/i915: two small moves towards more consistency

From: Nick Hoath Rename i915_gem_cleanup_ringbuffer() to i915_gem_cleanup_engines(), to relect what it actually does (clean up all the engines, not a single ringbuffer). The name is probably a legacy from the days when there was only one "ring" (i.e. engine) and one

[Intel-gfx] [PATCH v5 00/11] A collection of cleanups, revisited

Various things can go wrong during initialisation and teardown, but they usually don't, so the error-handling paths go largely untested. This collection of patches fixes some things I recently noticed. Some might lead to a kernel OOPS, but mostly they're leaks and other inconsistencies. Includes

[Intel-gfx] [PATCH v5 03/11] drm/i915: remove useless copypasted code

There's some unreachable code in intel_logical_ring_cleanup(), presumably copypasted from the legacy ringbuffer version at creation. Let's delete it :) Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/intel_lrc.c | 10 ++ 1 file changed, 2 insertions(+), 8

[Intel-gfx] [PATCH v5 04/11] drm/i915: tidy up initialisation failure paths (GEM)

Add call to i915_gem_context_fini() to deallocate the default context if the call to init_rings() fails, so that we don't leak the allocated memory in that situation. Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/i915_gem.c | 5 - 1 file changed, 4

[Intel-gfx] [PATCH v5 06/11] drm/i915: tidy initialisation failure paths (legacy, part 2)

After the last patch, there is only one caller of the trivial function intel_destroy_ringbuffer_obj(), so we might as well fold it into the caller. v3: Don't bother to clear a pointer in an object about to be freed. [Chris Wilson] v4: Don't bother to check for NULL pointer, as

[Intel-gfx] [PATCH v5 11/11] drm/i915: make LRC status page teardown code a bit more robust

Having recently fixed a few ordering/lifetime bugs in this area, it seems worthwhile putting a few more checks and warnings here, to provide early detection of any future code changes that cause problems; especially as we hope to rework the pinning/refcounting of the kernel context soon.

[Intel-gfx] [PATCH v5 10/11] drm/i915: interchange context/engine cleanup order

From: Nick Hoath Swap the order of context & engine cleanup, so that contexts are cleaned up first, and *then* engines. This is a more sensible order anyway, but in particular has become necessary since the 'intel_ring_initialized() must be simple and inline' patch,

Re: [Intel-gfx] [PATCH] list-workarounds: Extend the script to Mesa

> -Original Message- > From: Lespiau, Damien > Sent: Friday, February 05, 2016 4:16 AM > To: Kibey, Sameer > Cc: intel-gfx@lists.freedesktop.org; mesa-...@lists.freedesktop.org; Sharp, > Sarah A; Widawsky, Benjamin > Subject: Re: [PATCH] list-workarounds: Extend the script to Mesa > > On

[Intel-gfx] [PATCH v5 09/11] drm/i915: tear down hardware status page mappings earlier

This has to be done before the containing object is freed, otherwise the mapping ends up pointing to no-longer-allocated memory :( Signed-off-by: Dave Gordon Cc: Mika Kuoppala Cc: Chris Wilson ---

[Intel-gfx] [PATCH v5 01/11] drm/i915: unmap the correct page in intel_logical_ring_cleanup()

The kunmap() call here didn't match the corresponding kmap(). The kmap()ing was changed with the introduction of the GuC-compatible layout of context objects and the introduction of "LRC_PPHWSP_PN", in d167519 drm/i915: Integrate GuC-based command submission but the corresponding kunmap()

[Intel-gfx] [PATCH v5 05/11] drm/i915: tidy initialisation failure paths (legacy, part 1)

Make sure intel_unpin_ringbuffer_obj() can handle the case where the ringbuffer has been allocated but map-and-pin failed. Return early if the ringbuffer isn't mapped [Chris Wilson]. That allows us to simplify the cleanup path in intel_init_ring_buffer(), as it can just take the error exit and

[Intel-gfx] [PATCH v5 02/11] drm/i915: consolidate LRC mode HWSP setup & teardown

In legacy ringbuffer mode, the HWSP is a separate GEM object with its own pinning and reference counts. In LRC mode, however, it's not; instead its part of the default context object. The LRC-mode setup & teardown code therefore needs to handle this specially; the presence of the two bugs fixed in

[Intel-gfx] [PATCH v8 1/1] drm/i915/bxt: Check BIOS RC6 setup before enabling RC6

RC6 setup is shared between BIOS and Driver. BIOS sets up subset of RC6 setup registers. If those are not setup Driver should not enable RC6. For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values to know if BIOS has enabled HW/SW RC6. This will also enable user to control RC6 using

[Intel-gfx] [PATCH v1 1/1] drm/i915: Hold RPM reference while setting freq limits through sysfs

Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_sysfs.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index c6188dd..bb2fd78 100644 ---

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Set invert bit for hpd based on VBT

On Fri, 05 Feb 2016, "Thulasimani, Sivakumar" wrote: > On 2/4/2016 5:59 PM, Jani Nikula wrote: >> On Thu, 04 Feb 2016, Shubhangi Shrivastava >> wrote: >>> This patch sets the invert bit for hpd detection for each port >>> based

[Intel-gfx] [PATCH v2] drm/i915: Reject invalid-pad for context-destroy and -create ioctls

Unknown parameters, especially structure padding, are expected to invoke rejection with -EINVAL. v2: similar issue exists for context-create Testcase: igt/gem_ctx_create/invalid-pad Testcase: igt/gem_ctx_bad_destroy/invalid-pad Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89602

[Intel-gfx] [PATCH v3] drm/i915/execlists: Move WA_TAIL_DWORDS to callee

From: Chris Wilson Currently emit-request starts writing to the ring and reserves space for a workaround to be emitted later whilst submitting the request. It is easier to read if the caller only allocates sufficient space for its access (then the reader can quickly

Re: [Intel-gfx] [PATCH v3] drm/i915/execlists: Move WA_TAIL_DWORDS to callee

On Fri, Feb 5, 2016 at 11:31 AM, Dave Gordon wrote: > From: Chris Wilson > > Currently emit-request starts writing to the ring and reserves space > for a workaround to be emitted later whilst submitting the request. It > is easier to read if

[Intel-gfx] [PATCH v2 i-g-t] igt/list-workarounds: Extend the script to Mesa

Updated the list-workarounds script so that it can parse Mesa directory if provided. Moved the common code to a separate function to allow reuse for both kernel and mesa. The new command line is: Usage: list-workarounds [options] path-to-kernel -k path-to-kernel -m path-to-mesa The legacy

[Intel-gfx] [PATCH 2/2] drm/i915/dp: reduce missing TPS3 support errors to debug logging

Per spec, TPS3 support is mandatory for downstream devices that support HBR2. We've therefore logged errors on HBR2 without TPS3 since commit 1da7d7131c35cde83f1bab8ec732b57b69bef814 Author: Jani Nikula Date: Thu Sep 3 11:16:08 2015 +0300 drm/i915: ignore link rate

Re: [Intel-gfx] [PATCH:xf86-intel-video] Add NULL checking for drawable in sna_dri2_flip_event

On Fri, Feb 05, 2016 at 04:50:22PM +0800, Lim Siew Hoon wrote: > The last flip complete signal may happen after the > sna_dri2_destroy_window function has been called. This > leads to calling frame_swap_complete with a null flip > drawable. So check for that and handle accordingly. Treating the

[Intel-gfx] [PATCH RESEND 3/5] drm/i915: move VBT based eDP port check to intel_bios.c

Hide knowledge about VBT child devices in intel_bios.c. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 33 + drivers/gpu/drm/i915/intel_dp.c | 21 + 3 files

Re: [Intel-gfx] [RFC 02/29] drm/i915: Introduce host graphics memory balloon for gvt

Hi Joonas, Thanks much for the review! We will incorporate those review comments! Meanwhile, is it good enough to do the host ballooning like below? The pros is that it is very simple, especially consider that guest ballooning logic has been there. Thanks! Regards, -Zhiyuan On Thu, Feb 04,

[Intel-gfx] [PATCH RESEND 4/5] drm/i915: move VBT based DSI presence check to intel_bios.c

Hide knowledge about VBT child devices in intel_bios.c. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_bios.c | 33 - drivers/gpu/drm/i915/intel_dsi.c | 23 ++- 3

[Intel-gfx] [PATCH RESEND 5/5] drm/i915/panel: setup pwm backlight based on connector type

Use the connector type instead of VBT directly to decide which backlight mechanism to use on VLV/CHV. (Indirectly, this is the same thing, but hides the VBT use.) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_panel.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH RESEND 1/5] drm/i915: move VBT based TV presence check to intel_bios.c

Hide knowledge about VBT child devices in intel_bios.c. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 38 ++ drivers/gpu/drm/i915/intel_tv.c | 43

[Intel-gfx] [PATCH RESEND 2/5] drm/i915: move VBT based LVDS presence check to intel_bios.c

Hide knowledge about VBT child devices in intel_bios.c. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_bios.c | 50 drivers/gpu/drm/i915/intel_lvds.c | 53

Re: [Intel-gfx] [PATCH] drm/i915: Protect fbdev across slow or failed initialisation

On Fri, Feb 05, 2016 at 01:27:10AM +0100, Lukas Wunner wrote: > Hi, > > On Thu, Feb 04, 2016 at 09:21:17AM +, Li, Weinan Z wrote: > > We still need this patch. Seems 54632abe8ca3 ("drm/i915: Fix oops caused by > > fbdev initialization > > failure") as well as 366e39b4d2c5 ("drm/i915: Tear

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Skip DDI PLL selection for DSI

== Summary == Series 3122v1 drm/i915: Skip DDI PLL selection for DSI http://patchwork.freedesktop.org/api/1.0/series/3122/revisions/1/mbox/ Test gem_sync: Subgroup basic-blt: pass -> INCOMPLETE (skl-i5k-2) Test kms_flip: Subgroup basic-flip-vs-dpms:

[Intel-gfx] [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v6)

This patch adds support for eDP backlight control using DPCD registers to backlight hooks in intel_panel. It checks for backlight control over AUX channel capability and sets up function pointers to get and set the backlight brightness level if supported. v2: Moved backlight functions from

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: reduce missing TPS3 support errors to debug logging

Reviewed-by: Sivakumar Thulasimani On 2/5/2016 3:46 PM, Jani Nikula wrote: Per spec, TPS3 support is mandatory for downstream devices that support HBR2. We've therefore logged errors on HBR2 without TPS3 since commit 1da7d7131c35cde83f1bab8ec732b57b69bef814

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: abstract training pattern selection

On Fri, 05 Feb 2016, "Thulasimani, Sivakumar" wrote: > Reviewed-by: Sivakumar Thulasimani Both pushed to drm-intel-next-queued, thanks for the review. BR, Jani. > > On 2/5/2016 3:46 PM, Jani Nikula wrote: >> Make it cleaner

[Intel-gfx] [PATCH] drm/i915: Skip DDI PLL selection for DSI

Skip DDI PLL selection if display type is DSI/MIPI. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_display.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

Re: [Intel-gfx] [PATCH] list-workarounds: Extend the script to Mesa

On Thu, Feb 04, 2016 at 06:14:02PM +, Kibey, Sameer wrote: > Updated the list-workarounds script so that it > can parse Mesa directory if provided. Moved the > common code to a separate function to allow > reuse for both kernel and mesa. > > The new command line is: > Usage: list-workarounds

[Intel-gfx] [PATCH v3] drm/i915/skl: Add missing SKL ids

Used by production devices: Intel(R) Iris Graphics 540 (Skylake GT3e) Intel(R) Iris Graphics 550 (Skylake GT3e) v2: More ids v3: Less ids (GT1 got duplicated) Cc: Mika Kuoppala Signed-off-by: Michał Winiarski Reviewed-by: Mika

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [RESEND,1/5] drm/i915: move VBT based TV presence check to intel_bios.c

== Summary == Series 3121v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/3121/revisions/1/mbox/ Test drv_module_reload_basic: pass -> DMESG-WARN (ilk-hp8440p) Test gem_mmap_gtt: Subgroup basic-small-bo: pass ->

[Intel-gfx] [PATCH 0/2] DPCD Backlight Control

These patches add support for Backlight Control using DPCD registers on eDP displays. - Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h A copy of this patch has also been sent to dri-devel list. - Patch 2 Implements functionaly for DPCD Backlight Control Yetunde

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: abstract training pattern selection

Reviewed-by: Sivakumar Thulasimani On 2/5/2016 3:46 PM, Jani Nikula wrote: Make it cleaner to add more checks in the function. No functional changes. Cc: Ander Conselvan de Oliveira Cc: Sivakumar Thulasimani

[Intel-gfx] [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size

This is used when reading Display Control capability Registers on the sink device. cc: Jani Nikula Signed-off-by: Yetunde Adebisi --- include/drm/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/drm_dp_helper.h

[Intel-gfx] ✓ Fi.CI.BAT: success for DPCD Backlight Control (rev3)

== Summary == Series 1864v3 DPCD Backlight Control http://patchwork.freedesktop.org/api/1.0/series/1864/revisions/3/mbox/ Test kms_flip: Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE bdw-nuci7total:161 pass:152 dwarn:0

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/skl: Add missing SKL GT3 id (rev3)

== Summary == Series 2919v3 drm/i915/skl: Add missing SKL GT3 id http://patchwork.freedesktop.org/api/1.0/series/2919/revisions/3/mbox/ Test kms_flip: Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE Test kms_force_connector_basic:

Re: [Intel-gfx] [RFC 02/29] drm/i915: Introduce host graphics memory balloon for gvt

Hi, On pe, 2016-02-05 at 18:03 +0800, Zhiyuan Lv wrote: > Hi Joonas, > > Thanks much for the review! We will incorporate those review comments! > > Meanwhile, is it good enough to do the host ballooning like below? The > pros is that it is very simple, especially consider that guest >

[Intel-gfx] [PATCH:xf86-intel-video] Add NULL checking for drawable in sna_dri2_flip_event

The last flip complete signal may happen after the sna_dri2_destroy_window function has been called. This leads to calling frame_swap_complete with a null flip drawable. So check for that and handle accordingly. Signed-off-by: Lim Siew Hoon Reviewed-by: Bob Paauwe

[Intel-gfx] [PATCH 1/2] drm/i915/dp: abstract training pattern selection

Make it cleaner to add more checks in the function. No functional changes. Cc: Ander Conselvan de Oliveira Cc: Sivakumar Thulasimani Cc: drm-intel-fi...@lists.freedesktop.org # dependency on the next patch Signed-off-by: Jani Nikula

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: abstract training pattern selection

== Summary == Series 3120v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/3120/revisions/1/mbox/ Test kms_flip: Subgroup basic-flip-vs-dpms: dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE Test pm_rpm: Subgroup basic-pci-d3-state:

Re: [Intel-gfx] [RFC 02/29] drm/i915: Introduce host graphics memory balloon for gvt

Hi Joonas, On Fri, Feb 05, 2016 at 03:40:49PM +0200, Joonas Lahtinen wrote: > Hi, > > On pe, 2016-02-05 at 18:03 +0800, Zhiyuan Lv wrote: > > Hi Joonas, > > > > Thanks much for the review! We will incorporate those review comments! > > > > Meanwhile, is it good enough to do the host ballooning

Re: [Intel-gfx] [v2 1/6] drm/i915/skl+: Use plane size for relative data rate calculation

On Wed, Jan 27, 2016 at 09:39:58PM +0530, Shobhit Kumar wrote: > From: "Kumar, Mahesh" > > Use plane size for relative data rate calculation. don't always use > pipe source width & height. > adjust height & width according to rotation. > use plane size for watermark

Re: [Intel-gfx] [v2 2/6] drm/i915/skl+: calculate ddb minimum allocation

On Wed, Jan 27, 2016 at 09:39:59PM +0530, Shobhit Kumar wrote: > From: "Kumar, Mahesh" > > don't always use 8 ddb as minimum, instead calculate using proper > algorithm. > > v2: optimizations as per Matt's comments. > > Cc: matthew.d.ro...@intel.com > Signed-off-by:

[Intel-gfx] [PATCH] drm/i915: Check for get_pages instead of shmem (filp)

This behavior of checking for a shmem backed GEM object was introduced here: commit 4c914c0c7c787b8f730128a8cdcca9c50b0784ab Author: Brad Volkin Date: Tue Feb 18 10:15:45 2014 -0800 drm/i915: Refactor shmem pread setup It is possible for an object to not be a

Re: [Intel-gfx] [PATCH v2 i-g-t] igt/list-workarounds: Extend the script to Mesa

On Fri, Feb 05, 2016 at 01:55:19PM -0800, Sameer Kibey wrote: > Updated the list-workarounds script so that it > can parse Mesa directory if provided. Moved the > common code to a separate function to allow > reuse for both kernel and mesa. > > The new command line is: > Usage: list-workarounds