Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Tue, Mar 15, 2016 at 04:14:19PM -0500, Pierre-Louis Bossart wrote: > On 3/15/16 11:21 AM, Vinod Koul wrote: > >On Tue, Mar 15, 2016 at 03:35:45PM +0200, Ville Syrjälä wrote: > I understand the benefits of a parent/child device/subdevice model. What I > don't see is whether we need the

Re: [Intel-gfx] Video freezes continue to plague me

On Tue, 2016-03-15 at 19:17 -0400, Felix Miata wrote: > Chris composed on 2016-03-15 17:43 (UTC-0500): > > > On Tue, 2016-03-15 at 16:37 -0400, Felix Miata wrote: > > >> Chris composed on 2016-03-15 14:50 (UTC-0500): > > >> > My system is a Dell Optiplex 780. > > >> Which? Tower? Desktop? SFF?

[Intel-gfx] [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit

For BXT, Polarity of PORT_PLL_REF_SEL is reversed in its description in Bspec. This bit should be set for "Non-SSC". Signed-off-by: Dongwon Kim --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Intel-gfx] Video freezes continue to plague me

Chris composed on 2016-03-15 17:43 (UTC-0500): On Tue, 2016-03-15 at 16:37 -0400, Felix Miata wrote: Chris composed on 2016-03-15 14:50 (UTC-0500): > My system is a Dell Optiplex 780. Which? Tower? Desktop? SFF? USFF? Sorry, it's a desktop > I've filed several bug reports both >

Re: [Intel-gfx] Video freezes continue to plague me

On Tue, 2016-03-15 at 16:37 -0400, Felix Miata wrote: > Chris composed on 2016-03-15 14:50 (UTC-0500): > > > My system is a Dell Optiplex 780. > > Which? Tower? Desktop? SFF? USFF? Sorry, it's a desktop > > > I've filed several bug reports both > > with the Intel Graphics Bugzilla and the

[Intel-gfx] [PATCH V11] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

From: Clint Taylor WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected to DDI1 the system will hard hang during a cold boot. Occurs when DDI1 is enabled when the cdclk is less then required. DP connected to DDI2 and HPD on either port works

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On 3/15/16 11:21 AM, Vinod Koul wrote: On Tue, Mar 15, 2016 at 03:35:45PM +0200, Ville Syrjälä wrote: I understand the benefits of a parent/child device/subdevice model. What I don't see is whether we need the component framework at all here? It was used in the case of HDaudio since both i915

Re: [Intel-gfx] [PATCH i-g-t] igt/gem_pipe_control_store_loop: Add qword write tests

On Tue, Mar 15, 2016 at 06:54:01PM +0100, Michał Winiarski wrote: > Starting from gen8 it's possible to use PIPE_CONTROL writing qword > instead of dword, let's add new *-qword-write tests to check coherency > of qword writes. It's always been possible to do either qword or dword writes using

Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina?MacBook Pro

Hi Alex, On Tue, Mar 15, 2016 at 02:33:56PM -0400, Alex Deucher wrote: > On Tue, Mar 15, 2016 at 1:54 PM, Lukas Wunner wrote: > > On Sat, Mar 05, 2016 at 01:10:56PM -0500, Alex Deucher wrote: > >> Is there any reason to make use of the mux? > > > > Performance (lower latency =>

Re: [Intel-gfx] Video freezes continue to plague me

Chris composed on 2016-03-15 14:50 (UTC-0500): My system is a Dell Optiplex 780. Which? Tower? Desktop? SFF? USFF? I've filed several bug reports both with the Intel Graphics Bugzilla and the Ubuntu Launchpad pages. Initially back when this started in 2014 every 'freeze' would result in an

[Intel-gfx] [RFC PATCH 07/10] drm/i915: abstract get config for cpu transcoder

Makes it neater to add the same for DSI transcoder. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 83 1 file changed, 47 insertions(+), 36 deletions(-) diff --git

[Intel-gfx] [RFC PATCH 01/10] drm/i915: add for_each_port_masked macro

Same as for_each_dsi_port, but for general use. Leave the for_each_dsi_port version around as an "alias" for now to not cause too much churn. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 4 drivers/gpu/drm/i915/intel_dsi.h

[Intel-gfx] [RFC PATCH 06/10] drm/i915: split set pipeconf to pipe and transcoder parts

Prep work for DSI transcoders. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [RFC PATCH 09/10] drm/i915/dsi: use the BIT macro for clarity

No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dsi.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 47fd0296a05a..a249549a1d86

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Nuke fbc members from intel_crtc->atomic, v4.

Em Qua, 2016-03-09 às 10:35 +0100, Maarten Lankhorst escreveu: > Whenever there's an update to the primary plane, > fbc_pre_update and fbc_post_update are called. Kill off > intel_crtc->atomic.update_fbc and now that intel_crtc->atomic > is empty, kill it off too. > > Changes since v1: > - Add a

[Intel-gfx] [RFC PATCH 10/10] drm/i915/bxt: allow dsi on any pipe

BXT isn't as limited as BYT and CHT regarding DSI pipes and ports. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index

[Intel-gfx] [RFC PATCH 02/10] drm/i915: make transcoder_name return a string

Nicer for eDP (actually "eDP" instead of "D"), and makes future expansion for DSI transcoders easier. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h| 17 - drivers/gpu/drm/i915/intel_display.c | 4 ++--

[Intel-gfx] [RFC PATCH 08/10] drm/i915/bxt: add dsi transcoders

The BXT display connections have DSI transcoders A and C that can be muxed to any pipe, not unlike the eDP transcoder. Add the notion of DSI transcoders. The "normal" transcoders A, B and C are not used with BXT DSI, so care must be taken to avoid accessing those registers with DSI transcoders in

[Intel-gfx] [RFC PATCH 05/10] drm/i915: split get/set pipe timings to pipe and transcoder parts

Prep work for DSI transcoders. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 27 +++ 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [RFC PATCH 00/10] drm/i915/bxt: add dsi transcoders

Here's my first attempt at adding bxt dsi transcoder support. Patch 8 is the real deal, everything else is almost trivial. It was painful to try ensure we really aren't indexing any regular transcoder registers with the dsi transcoder enumerations, but I think I got them all. It's fairly

[Intel-gfx] [RFC PATCH 03/10] drm/i915/dsi: refactor dsi get hw state readout

Make the code easier to read and update. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dsi.c | 37 +++-- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c

[Intel-gfx] [RFC PATCH 04/10] drm/i915/bxt: fix dsi hw state pipe readout

BXT isn't as limited as BYT and CHT regarding DSI pipes and ports. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dsi.c | 14 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] Video freezes continue to plague me

My system is a Dell Optiplex 780. I've filed several bug reports both with the Intel Graphics Bugzilla and the Ubuntu Launchpad pages. Initially back when this started in 2014 every 'freeze' would result in an error of [drm:i915_hangcheck_elapsed [i915]] *ERROR* Hangcheck timer elapsed... render

Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina?MacBook Pro

On Tue, Mar 15, 2016 at 1:54 PM, Lukas Wunner wrote: > Hi Alex, > > On Sat, Mar 05, 2016 at 01:10:56PM -0500, Alex Deucher wrote: >> Is there any reason to make use of the mux? > > Performance (lower latency => no need for framebuffer writes over PCIe), > improved battery life

[Intel-gfx] [PATCH RESEND FOR CI] drm/i915/bxt: Fix off-by-one error in Broxton PLL IDs

After the commit below the Broxton PLL IDs had an off-by-one error, so fix this up. Also add a missing brace at intel_shared_dpll_init(), it happened to compile only due to the way the IS_BROXTON macro is defined. v2: - remove debugging left-over Fixes: a3c988ea068c ("drm/i915: Make SKL/KBL

[Intel-gfx] [PATCH i-g-t] igt/gem_pipe_control_store_loop: Add qword write tests

Starting from gen8 it's possible to use PIPE_CONTROL writing qword instead of dword, let's add new *-qword-write tests to check coherency of qword writes. Signed-off-by: Michał Winiarski --- tests/gem_pipe_control_store_loop.c | 49

Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina?MacBook Pro

Hi Alex, On Sat, Mar 05, 2016 at 01:10:56PM -0500, Alex Deucher wrote: > Is there any reason to make use of the mux? Performance (lower latency => no need for framebuffer writes over PCIe), improved battery life (no need to use 2 GPUs simultaneously). Technically you can't just ignore that the

[Intel-gfx] [PATCH v3] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords. When we're using older 5-dword variant it's possible to observe inconsistent values written by 6-dword PIPE_CONTROL with Post Sync Operation from user batches. v2: Fix BAT failures v3: Comments on alignment and thrashing

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: unify partial/normal page insertion loops

== Series Details == Series: drm/i915: unify partial/normal page insertion loops URL : https://patchwork.freedesktop.org/series/4476/ State : failure == Summary == Series 4476v1 drm/i915: unify partial/normal page insertion loops

Re: [Intel-gfx] [PATCH] drm/i915: unify partial/normal page insertion loops

On Tue, Mar 15, 2016 at 04:05:58PM +, Matthew Auld wrote: > Cc: Joonas Lahtinen > Signed-off-by: Matthew Auld I know I sent patches to make this even simpler than what you present here, and that *fix* *actual* *bugs* in the partial

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Tue, Mar 15, 2016 at 03:35:45PM +0200, Ville Syrjälä wrote: > > > I understand the benefits of a parent/child device/subdevice model. What I > > > don't see is whether we need the component framework at all here? > > > It was used in the case of HDaudio since both i915 and HDaudio controllers >

[Intel-gfx] [PATCH] drm/i915: unify partial/normal page insertion loops

Cc: Joonas Lahtinen Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem.c | 40 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly

== Series Details == Series: drm/i915: DSI and DPLL stuff for VLV/CHV mostly URL : https://patchwork.freedesktop.org/series/4472/ State : failure == Summary == Series 4472v1 drm/i915: DSI and DPLL stuff for VLV/CHV mostly http://patchwork.freedesktop.org/api/1.0/series/4472/revisions/1/mbox/

[Intel-gfx] [PATCH v3] drm/i915: add module param "enable_dp_mst"

Adds an (unsafe; auto-kernel-tainting) boolean module parameter to the i915 drm driver: "enable_dp_mst", which is enabled by default. Disabling the parameter forces newly connected DisplayPort sinks to report as not supporting multi-stream transport (MST), thus "forcing" the use of single-stream

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Update VBT fields for child devices

On Tue, Mar 15, 2016 at 06:43:53PM +0530, Shubhangi Shrivastava wrote: > This patch adds new fields that are not yet added in drm code > in child devices struct > > Signed-off-by: Sivakumar Thulasimani > Signed-off-by: Durgadoss R >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Set invert bit for hpd based on VBT

On Tue, Mar 15, 2016 at 06:43:54PM +0530, Shubhangi Shrivastava wrote: > This patch sets the invert bit for hpd detection for each port > based on VBT configuration. Since each AOB can be designed to > depend on invert bit or not, it is expected if an AOB requires > invert bit, the user will set

[Intel-gfx] [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex

From: Ville Syrjälä pgm_ratios in stored as a register value in pipe config, so let's dump this one as hex as well. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll()

From: Ville Syrjälä Fold the DSI PLL configuration functions into the DSI PLL enable functions since they are small and not called from anywhere else. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dsi_pll.c | 28

[Intel-gfx] [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config()

From: Ville Syrjälä Compute the DSI PLL parameters during .compute_config() rather than .pre_pll_enable() so that we can fail gracefully if we can't find suitable parameters. In order to do that we need to store the DSI PLL parameters in pipe_config. v2: Handle

[Intel-gfx] [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll()

From: Ville Syrjälä Supposedly the power sequencer still locks out the DPLL registers on CHV, so let's issue a warning if it's still locked when enabling the DPLL. Also drop the redundant IS_MOBILE() check for VLV when we check the same thing. Signed-off-by:

[Intel-gfx] [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it

From: Ville Syrjälä On VLV at least, the BIOS may leave the DSI PLL enabled in some wonky state where it just refuses to lock. Simply disabling the PLL before reconfiguring it is not enough to fix it, but power gating the PLL prior to reconfiguring does work. This

[Intel-gfx] [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv

From: Ville Syrjälä DPLL_MD(PIPE_C) is AWOL on CHV. Instead of fixing it someone added chicken bits to propagate the pixel multiplier from DPLL_MD(PIPE_B) to either pipe B or C. So do that to make pixel repeat work on pipes B and C. Pipe A is fine without any

[Intel-gfx] [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly

From: Ville Syrjälä Here's a pile of pending VLV/CHV DSI and DPLL patches I had lying around. Most of these have been posted before. Would be nice to finally get them in. I've tried to rebase things to account for BXT as well, but obviously that part is not

[Intel-gfx] [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms

From: Ville Syrjälä We don't have a LVDS_BORDER_ENABLE type of bit for either eDP or DSI, and just trying to frob the display timings to include borders results in a corrupted picture. So reject the 'Center' scaling mode on GMCH platforms for eDP and DSI. TODO:

[Intel-gfx] [PATCH 15/16] drm/i915: Hook up pfit for DSI

From: Ville Syrjälä Add the scaling mode property to DSI connectors, handle changes in the property value, and compute the panel fitter state during .compute_config(). v2: Handle BXT as well Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 07/16] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV

From: Ville Syrjälä Set up DPLL and DPLL_MD even when driving DSI output on VLV/CHV. While the DPLL isn't used to provide the clock we still need the refclock, and it appears that the pixel repeat factor also has an effect on DSI output. So set up eveyrhing in DPLL

[Intel-gfx] [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout

From: Ville Syrjälä Use the proper refclock frequency (100MHz) when reading out the current DSI clock on CHV. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +- 1 file changed, 1 insertion(+), 1

[Intel-gfx] [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll()

From: Ville Syrjälä VLV DPLL is somewhat sane and doesn't run on luck. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 11 --- 1 file changed, 11 deletions(-) diff --git

Re: [Intel-gfx] [PATCH v4] drm/i915/mocs: Program MOCS for all engines on init

Chris, Testcases are underway, validation are working on them. Peter. On Tue, 15 Mar 2016, Chris Wilson wrote: On Mon, Mar 14, 2016 at 03:11:02PM +, Peter Antoine wrote: Allow for the MOCS to be programmed for all engines. Currently we program the MOCS when the first render batch goes

[Intel-gfx] [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll()

From: Ville Syrjälä Avoid redundant crtc->pipe lookups by giving vlv_enable_pll() a local pipe variable. Also makes it look more like the corresponding CHV code. While at is change the CHV code to enum pipe from int, Signed-off-by: Ville Syrjälä

[Intel-gfx] [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled

From: Ville Syrjälä Check whether the DPLL is even enabled before readoing out the dividers and trying to derive port_clock on CHV. We already did this on VLV. Also remove the comment "MIPI" comment from the VLV code since we call this function whenever the pipe

[Intel-gfx] [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar

From: Ville Syrjälä The VLV and CHV DPLL disable and update are almost identical in how the DPLL/DPLL_MD registers need to be set up. But the code looks more different than it really is. Try to bring them into line. v2: s/chv_update_pll/chv_compute_dpll/

[Intel-gfx] [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16

From: Ville Syrjälä All the values in the DSI PLL LFSR seed table fit into 9bits, so change the type to u16 from u32 to save a bit of space. drivers/gpu/drm/i915/i915.ko: -.rodata90824 +.rodata90760 Signed-off-by:

[Intel-gfx] [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions

From: Ville Syrjälä These BUGs don't serve any purpose IMO. Throw them out. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 9 - 1 file changed, 9 deletions(-) diff --git

Re: [Intel-gfx] [PATCH v3] drm/i915: Add fault injection support

On Tue, Mar 15, 2016 at 04:01:14PM +0200, Imre Deak wrote: > I'm not sure if you want to check all failure paths, I think for that > the existing failslab etc. mechanisms are better suited. This new > option would be used at relatively few well defined places. The option > is a mask since Chris

Re: [Intel-gfx] [PATCH v3] drm/i915: Add fault injection support

On ti, 2016-03-15 at 10:34 +0200, Joonas Lahtinen wrote: > On ma, 2016-03-14 at 16:59 +0200, Imre Deak wrote: > > Add support for forcing an error at selected places in the driver. > > As > > an > > example add 4 options to fail during driver loading. > > > > Requested by Chris. > > > > v2: > >

Re: [Intel-gfx] [PATCH v3] drm/i915: Add fault injection support

On ti, 2016-03-15 at 09:56 +0100, Daniel Vetter wrote: > On Mon, Mar 14, 2016 at 04:59:20PM +0200, Imre Deak wrote: > > Add support for forcing an error at selected places in the driver. > > As an > > example add 4 options to fail during driver loading. > > > > Requested by Chris. > > > > v2: >

Re: [Intel-gfx] [maintainer-tools PATCH 3/4] dim: run checkpatch on committed patches on apply

On Tue, Mar 15, 2016 at 03:29:01PM +0200, Jani Nikula wrote: > On Tue, 15 Mar 2016, Daniel Vetter wrote: > > [snip] > > >> While at it, drop the obsolete check for drm_i915_private_t. We'll now > >> get a build fail for that. > > [snip] > > >> - $cmd | grep

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Tue, Mar 15, 2016 at 03:35:45PM +0200, Ville Syrjälä wrote: > On Tue, Mar 15, 2016 at 09:39:48AM +0100, Daniel Vetter wrote: > > On Mon, Mar 14, 2016 at 12:27:51PM -0500, Pierre-Louis Bossart wrote: > > > On 3/14/16 10:30 AM, Ville Syrjälä wrote: > > > >On Mon, Mar 14, 2016 at 05:21:54PM +0200,

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Tue, Mar 15, 2016 at 09:39:48AM +0100, Daniel Vetter wrote: > On Mon, Mar 14, 2016 at 12:27:51PM -0500, Pierre-Louis Bossart wrote: > > On 3/14/16 10:30 AM, Ville Syrjälä wrote: > > >On Mon, Mar 14, 2016 at 05:21:54PM +0200, Ville Syrjälä wrote: > > >>On Mon, Mar 14, 2016 at 10:13:58AM -0500,

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Tue, Mar 15, 2016 at 09:35:26AM +0100, Daniel Vetter wrote: > On Mon, Mar 14, 2016 at 04:20:19PM +0200, Ville Syrjälä wrote: > > On Mon, Mar 14, 2016 at 10:04:00AM +0100, Daniel Vetter wrote: > > > On Fri, Mar 11, 2016 at 09:09:12PM +0200, Ville Syrjälä wrote: > > > > On Fri, Mar 11, 2016 at

Re: [Intel-gfx] [maintainer-tools PATCH 3/4] dim: run checkpatch on committed patches on apply

On Tue, 15 Mar 2016, Daniel Vetter wrote: [snip] >> While at it, drop the obsolete check for drm_i915_private_t. We'll now >> get a build fail for that. [snip] >> -$cmd | grep '^\+.*drm_i915_private_t' > /dev/null && echo "WARNING: New >> drm_i915_private_t added" ||

Re: [Intel-gfx] [PATCH] drm/i915: Add delay on DPCD reads

On Tue, Mar 15, 2016 at 01:38:58PM +0200, Mika Kahola wrote: > Additional 50 ms delay is needed between DPCD reads on HP Bizlink 1326 > DP to VGA adapter. Having said that, I haven't noticed a need for > additional delay between DPCD reads on other DP-VGA dongles. > > While at it, let's replace

Re: [Intel-gfx] [maintainer-tools PATCH 4/4] dim: unify repo clean checks to a single assert_repo_clean helper

On Tue, Mar 15, 2016 at 11:20:38AM +0200, Jani Nikula wrote: > Moreover, 'git diff-index --quiet HEAD' kept failing on me even though > the repo was clean (merely running 'git status' always fixed this). So > use the other one. > > Signed-off-by: Jani Nikula Oh nice find,

Re: [Intel-gfx] [maintainer-tools PATCH 3/4] dim: run checkpatch on committed patches on apply

On Tue, Mar 15, 2016 at 11:20:37AM +0200, Jani Nikula wrote: > The input messages may have base64 encoding and whatnot, and > checkpatch.pl can't cope with them. Just let 'git am' handle that. The > upside is that checkpatch will now catch e.g. duplicate signed-off-bys. > > This is a partial

Re: [Intel-gfx] [PATCH v3] drm/i915: Add fault injection support

On Tue, Mar 15, 2016 at 09:28:34AM +, Chris Wilson wrote: > On Tue, Mar 15, 2016 at 10:34:02AM +0200, Joonas Lahtinen wrote: > > On ma, 2016-03-14 at 16:59 +0200, Imre Deak wrote: > > > +module_param_named(inject_load_failure, i915.inject_load_failure, > > > uint, 0600); > > > > This most

[Intel-gfx] [PATCH 2/2] drm/i915: Set invert bit for hpd based on VBT

This patch sets the invert bit for hpd detection for each port based on VBT configuration. Since each AOB can be designed to depend on invert bit or not, it is expected if an AOB requires invert bit, the user will set respective bit in VBT. v2: Separated VBT parsing from the rest of the logic.

[Intel-gfx] [PATCH 1/2] drm/i915: Update VBT fields for child devices

This patch adds new fields that are not yet added in drm code in child devices struct Signed-off-by: Sivakumar Thulasimani Signed-off-by: Durgadoss R Signed-off-by: Shubhangi Shrivastava ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add delay on DPCD reads

== Series Details == Series: drm/i915: Add delay on DPCD reads URL : https://patchwork.freedesktop.org/series/4462/ State : failure == Summary == Series 4462v1 drm/i915: Add delay on DPCD reads http://patchwork.freedesktop.org/api/1.0/series/4462/revisions/1/mbox/ Test

Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina?MacBook Pro

On Tue, 2016-03-15 at 21:10 +1000, Dave Airlie wrote: > > > > > > I guess that's only useful until we get runtime PM support. > For the discrete GPUs on regular laptops we have runtime PM support > for > powerdown already. Some newer laptops need a bit of work in the PCIE > layer > but for most

[Intel-gfx] [PATCH] drm/i915: Add delay on DPCD reads

Additional 50 ms delay is needed between DPCD reads on HP Bizlink 1326 DP to VGA adapter. Having said that, I haven't noticed a need for additional delay between DPCD reads on other DP-VGA dongles. While at it, let's replace mdelay() with usleep_range() routine. Signed-off-by: Mika Kahola

Re: [Intel-gfx] [PATCH] lib/igt_kms: Add COMMIT_ATOMIC to igt_display_commit2()

Op 11-03-16 om 09:25 schreef Mayuresh Gharpure: > Co-Author : Marius Vlad > Co-Author : Pratik Vishwakarma > > So far we have had only two commit styles, COMMIT_LEGACY > and COMMIT_UNIVERSAL. This patch adds another commit style >

Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina?MacBook Pro

> > I guess that's only useful until we get runtime PM support. For the discrete GPUs on regular laptops we have runtime PM support for powerdown already. Some newer laptops need a bit of work in the PCIE layer but for most things we have it covered. The known broken ones are Apple laptops. If

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2)

== Series Details == Series: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write (rev2) URL : https://patchwork.freedesktop.org/series/4446/ State : warning == Summary == Series 4446v2 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

Re: [Intel-gfx] [PATCH v5 27/35] drm/i915: Added debug state dump facilities to scheduler

Hi, On pe, 2016-03-11 at 16:38 +, John Harrison wrote: > The intention of the state dump code is not really for it to be a user  > accessible debugfs entry (although one of the later patches does add a  > debugfs interface). It is more intended for debugging lock ups and  > unexpected

Re: [Intel-gfx] [PATCH v4] drm/i915/mocs: Program MOCS for all engines on init

On Mon, Mar 14, 2016 at 03:11:02PM +, Peter Antoine wrote: > Allow for the MOCS to be programmed for all engines. > Currently we program the MOCS when the first render batch > goes through. This works on most platforms but fails on > platforms that do not run a render batch early, > i.e.

Re: [Intel-gfx] [PATCH v2] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

On Tue, Mar 15, 2016 at 10:20:09AM +0100, Michał Winiarski wrote: > On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords. But gen8/gen9 still respect 5 for a dword write instead of a qword write. Please include an explanation of the impact. -Chris -- Chris Wilson, Intel

Re: [Intel-gfx] [PATCH v3] drm/i915: Add fault injection support

On Tue, Mar 15, 2016 at 10:34:02AM +0200, Joonas Lahtinen wrote: > On ma, 2016-03-14 at 16:59 +0200, Imre Deak wrote: > > +module_param_named(inject_load_failure, i915.inject_load_failure, > > uint, 0600); > > This most definitely should be module_param_named_unsafe. > > I think I'd also hope to

Re: [Intel-gfx] [PATCH v2] drm/i915/bxt: Fix off-by-one error in Broxton PLL IDs

On ti, 2016-03-15 at 09:50 +0200, Ander Conselvan De Oliveira wrote: > On Mon, 2016-03-14 at 19:55 +0200, Imre Deak wrote: > > After the commit below the Broxton PLL IDs had an off-by-one error, > > so > > fix this up. Also add a missing brace at intel_shared_dpll_init(), > > it > > happened to

[Intel-gfx] [PATCH v2] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords. v2: Fix BAT failures Cc: Chris Wilson Signed-off-by: Michał Winiarski --- drivers/gpu/drm/i915/intel_lrc.c | 6 -- 1 file changed, 4 insertions(+), 2

[Intel-gfx] [maintainer-tools PATCH 4/4] dim: unify repo clean checks to a single assert_repo_clean helper

Moreover, 'git diff-index --quiet HEAD' kept failing on me even though the repo was clean (merely running 'git status' always fixed this). So use the other one. Signed-off-by: Jani Nikula --- dim | 27 +++ 1 file changed, 11 insertions(+), 16

[Intel-gfx] [maintainer-tools PATCH 2/4] dim: have update-branches also fetch origin and drm upstream repos

Convenient in many cases, but not as intrusive as full remote update. Signed-off-by: Jani Nikula --- dim | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/dim b/dim index e3fca75bc5e6..a287c9126047 100755 --- a/dim +++ b/dim @@ -991,7 +991,9 @@

[Intel-gfx] [maintainer-tools PATCH 1/4] dim: update for-next branches as part of nightly rebuild

Currently the for-linux-next-fixes and for-linux-next branches only get updated after the nightly rebuild after pushing branches. If the nightly rebuild fails at that point, the for-next branches won't get updated until the next time something is pushed, not upon nightly rebuild. Fix this by

[Intel-gfx] [maintainer-tools PATCH 3/4] dim: run checkpatch on committed patches on apply

The input messages may have base64 encoding and whatnot, and checkpatch.pl can't cope with them. Just let 'git am' handle that. The upside is that checkpatch will now catch e.g. duplicate signed-off-bys. This is a partial revert of commit a913db697bb063d374229e5e806e514fa44985d0 Author: Daniel

Re: [Intel-gfx] [PATCH v3] drm/i915: Add fault injection support

On Mon, Mar 14, 2016 at 04:59:20PM +0200, Imre Deak wrote: > Add support for forcing an error at selected places in the driver. As an > example add 4 options to fail during driver loading. > > Requested by Chris. > > v2: > - Add fault point for modeset initialization > - Print debug message when

Re: [Intel-gfx] [PATCH v4 17/17] drm/i915: Split out load time interface registration

On Mon, Mar 14, 2016 at 01:00:41PM +0200, Imre Deak wrote: > According to the new init phases scheme we should register the device > making it available via some kernel internal or user space interface as > the last step in the init sequence, so move the corresponding code to a > separate

Re: [Intel-gfx] [PATCH] [i915] add module param "enable_dp_mst"

On Mon, Mar 14, 2016 at 11:36:29AM -0500, Nathan Schulte wrote: > Adds an (unsafe; auto-kernel-tainting) boolean module parameter to the i915 > drm driver: "enable_dp_mst", which is enabled by default. Disabling the > parameter forces newly connected DisplayPort sinks to report as not >

Re: [Intel-gfx] [PATCH v5] intel: New libdrm interface to create unbound wc user mappings for objects

On Mon, Mar 14, 2016 at 06:51:54PM +0200, Martin Peres wrote: > On 10/03/16 10:39, Martin Peres wrote: > >On 09/03/16 11:09, akash.g...@intel.com wrote: > >>From: Akash Goel > >> > >>A new libdrm interface 'drm_intel_gem_bo_map_wc' is provided by this > >>patch. Through this

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Mon, Mar 14, 2016 at 12:27:51PM -0500, Pierre-Louis Bossart wrote: > On 3/14/16 10:30 AM, Ville Syrjälä wrote: > >On Mon, Mar 14, 2016 at 05:21:54PM +0200, Ville Syrjälä wrote: > >>On Mon, Mar 14, 2016 at 10:13:58AM -0500, Pierre-Louis Bossart wrote: > >>>On 3/11/16 1:09 PM, Ville Syrjälä

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Mon, Mar 14, 2016 at 10:04:00AM +0100, Daniel Vetter wrote: > On Fri, Mar 11, 2016 at 09:09:12PM +0200, Ville Syrjälä wrote: > > On Fri, Mar 11, 2016 at 11:27:13AM -0600, Pierre-Louis Bossart wrote: > > > Thanks for the review Ville > > > > > > [snip] > > > > > > > Kinda hard to see where

Re: [Intel-gfx] [RFC 04/15] drm/i915: Add headers for non-HDAudio HDMI interface

On Mon, Mar 14, 2016 at 04:20:19PM +0200, Ville Syrjälä wrote: > On Mon, Mar 14, 2016 at 10:04:00AM +0100, Daniel Vetter wrote: > > On Fri, Mar 11, 2016 at 09:09:12PM +0200, Ville Syrjälä wrote: > > > On Fri, Mar 11, 2016 at 11:27:13AM -0600, Pierre-Louis Bossart wrote: > > > > Thanks for the

Re: [Intel-gfx] [PATCH v3] drm/i915: Add fault injection support

On ma, 2016-03-14 at 16:59 +0200, Imre Deak wrote: > Add support for forcing an error at selected places in the driver. As > an > example add 4 options to fail during driver loading. > > Requested by Chris. > > v2: > - Add fault point for modeset initialization > - Print debug message when

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: i915: remove intel_hdmi variable declaration

== Series Details == Series: drm: i915: remove intel_hdmi variable declaration URL : https://patchwork.freedesktop.org/series/4452/ State : failure == Summary == Series 4452v1 drm: i915: remove intel_hdmi variable declaration

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

== Series Details == Series: drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write URL : https://patchwork.freedesktop.org/series/4446/ State : failure == Summary == Series 4446v1 drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

Re: [Intel-gfx] [PATCH v5 00/12] Enable GPU switching on pre-retina?MacBook Pro

On Mon, Mar 14, 2016 at 02:37:44PM +0100, Bastien Nocera wrote: > Do you have references for the i915 runtime PM support, a bugzilla or > mailing-list thread? i915.ko has runtime PM support, it's just not yet enabled by default due to some funky corner cases. If you enable it you might hit a

Re: [Intel-gfx] [PATCH v2] drm/i915/bxt: Fix off-by-one error in Broxton PLL IDs

On Mon, 2016-03-14 at 19:55 +0200, Imre Deak wrote: > After the commit below the Broxton PLL IDs had an off-by-one error, so > fix this up. Also add a missing brace at intel_shared_dpll_init(), it > happened to compile only due to the way the IS_BROXTON macro is defined. > > v2: > - remove

Re: [Intel-gfx] [PATCH v2 01/17] Fix MCHBAR cleanup on the driver init error path

On Fri, Mar 11, 2016 at 06:31:26PM +0200, Imre Deak wrote: > MCHBAR is cleaned up in i915_mmio_cleanup(), so the separate call in > i915_driver_load() is incorrect. > > CC: David Weinehall > Fixes: ad5c3d3ffbb2 ("drm/i915: Move MCHBAR setup earlier during init") >