Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

Regards Shashank On 10/21/2016 12:50 AM, Imre Deak wrote: On Thu, 2016-10-20 at 21:20 +0300, Jani Nikula wrote: On Thu, 20 Oct 2016, Imre Deak wrote: On my APL the LSPCON firmware resumes in PCON mode as opposed to the expected LS mode. It also appears to be in a state

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: GVT-g driver depends on 64BIT kernel

== Series Details == Series: drm/i915: GVT-g driver depends on 64BIT kernel URL : https://patchwork.freedesktop.org/series/14143/ State : warning == Summary == Series 14143v1 drm/i915: GVT-g driver depends on 64BIT kernel

[Intel-gfx] [PATCH] drm/i915: GVT-g driver depends on 64BIT kernel

We currently don't support GVT-g driver on i386 kernel. Add explicit dependence on 64bit kernel. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig

Re: [Intel-gfx] [PATCH] drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate

On 2016.10.20 17:20:04 +0200, Arkadiusz Hiler wrote: > On Thu, Oct 20, 2016 at 05:29:36PM +0300, Mika Kuoppala wrote: > > Arkadiusz Hiler writes: > > > > > When invalidating RCS TLB the device can enter RC6 state interrupting > > > the process, therefore the need for

[Intel-gfx] [PATCH v3] Idleness DRRS test

From: Ramalingam C Idleness DRRS: By default the DRRS state will be at DRRS_HIGH_RR. When a Display content is Idle for more than 1Sec Idleness will be declared and DRRS_LOW_RR will be invoked, changing the refresh rate to the lower most

Re: [Intel-gfx] linux-next: Tree for Oct 20 (gpu/drm/i915)

On 2016.10.20 21:25:03 +0300, Jani Nikula wrote: > On Thu, 20 Oct 2016, Daniel Vetter wrote: > > On Thu, Oct 20, 2016 at 7:37 PM, Randy Dunlap wrote: > >> On 10/19/16 20:20, Stephen Rothwell wrote: > >>> Hi all, > >>> > >>> Changes since 20161019: > >>> >

[Intel-gfx] Redo a modeset on link training failure

Hi Ville, I have implemented the code that we discussed where if the link training fails, it would validate the modes on the new constraints and call an atomic helper like drm_atomic_helper_connector_modeset() to redo a modeset for the same mode. The two patches for this implemnetation is are:

Re: [Intel-gfx] [i-g-t PATCH v2] igt/tools: Update intel_watermark with SKL support

Cc'ing reviewers On Tue, 2016-10-18 at 17:05 -0700, Dhinakaran Pandiyan wrote: > Added support to print SKL watermark and DDB registers. > > v2: Printed raw register data, renamed planes and combined two printf()'s > (Ville) > > Signed-off-by: Dhinakaran Pandiyan

Re: [Intel-gfx] [PATCH] drm/i915/dp: Increase cdclk when DP audio is enabled with 4 lanes and HBR2

On Mon, 2016-10-17 at 11:33 +0300, Ville Syrjälä wrote: > On Fri, Oct 14, 2016 at 08:33:37PM +, Pandiyan, Dhinakaran wrote: > > On Thu, 2016-10-13 at 21:44 +0300, Ville Syrjälä wrote: > > > On Thu, Oct 13, 2016 at 11:04:19AM -0700, Dhinakaran Pandiyan wrote: > > > > According to BSpec, cdclk

Re: [Intel-gfx] [PATCH 8/8] drm/i915/gen9+: Preserve old allocation from crtc_state.

On Wed, Oct 12, 2016 at 03:28:21PM +0200, Maarten Lankhorst wrote: > This is the last bit required for making nonblocking modesets work > correctly. The state in intel_crtc->hw_ddb is not updated until > somewhere in atomic commit, while the previous crtc state should be > accurate if the ddb

Re: [Intel-gfx] [PATCH v6 06/11] drm/i915: Enable i915 perf stream for Haswell OA unit

On Thu, Oct 20, 2016 at 10:19:05PM +0100, Robert Bragg wrote: > +int i915_gem_context_pin_legacy_rcs_state(struct drm_i915_private *dev_priv, > + struct i915_gem_context *ctx, > + u64 flags) This is still no. > +static

Re: [Intel-gfx] [PATCH 7/8] drm/i915/gen9+: Program watermarks as a separate step during evasion

On Wed, Oct 12, 2016 at 03:28:20PM +0200, Maarten Lankhorst wrote: > Instead of running the watermark updates from the callbacks run > them from a separate hook atomic_evade_watermarks. The commit message here is a bit terse. I'd clarify that the change we're making is that watermark register

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Clean up DDI DDC/AUX CH sanitation

I meant DON't suspect On Thu, Oct 20, 2016 at 11:53 PM, Maarten Maathuis wrote: > Also tested v3 on top of 4.8.3 (mainline git is a mess right now for > booting). > > I did encounter a seemingly unrelated message during boot (including a > WARN_ON): >

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Clean up DDI DDC/AUX CH sanitation

Also tested v3 on top of 4.8.3 (mainline git is a mess right now for booting). I did encounter a seemingly unrelated message during boot (including a WARN_ON): [drm:skylake_pfit_enable [i915]] *ERROR* Requesting pfit without getting a scaler first I suspect any causal relation with these

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v6,01/11] drm/i915: Add i915 perf infrastructure

== Series Details == Series: series starting with [v6,01/11] drm/i915: Add i915 perf infrastructure URL : https://patchwork.freedesktop.org/series/14135/ State : failure == Summary == Series 14135v1 Series without cover letter

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On Thu, 2016-10-20 at 23:50 +0300, Jani Nikula wrote: > On Thu, 20 Oct 2016, Imre Deak wrote: > > On Thu, 2016-10-20 at 22:24 +0300, Jani Nikula wrote: > > > On Thu, 20 Oct 2016, Jani Nikula wrote: > > > > On Thu, 20 Oct 2016, Imre Deak

Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/kms_sysfs_edid_timing: Convert sh script to C version.

On Thu, Oct 20, 2016 at 10:36:49PM +0300, Marius Vlad wrote: > While at it, make available time macros to other users. > > Signed-off-by: Marius Vlad > --- > benchmarks/gem_syslatency.c | 4 --- > lib/igt_core.c| 3 -- > lib/igt_core.h

[Intel-gfx] [PATCH v6 11/11] drm/i915: Add a kerneldoc summary for i915_perf.c

In particular this tries to capture for posterity some of the early challenges we had with using the core perf infrastructure in case we ever want to revisit adapting perf for device metrics. Cc: Chris Wilson Signed-off-by: Robert Bragg

[Intel-gfx] [PATCH v6 07/11] drm/i915: advertise available metrics via sysfs

Each metric set is given a sysfs entry like: /sys/class/drm/card0/metrics//id This allows userspace to enumerate the specific sets that are available for the current system. The 'id' file contains an unsigned integer that can be used to open the associated metric set via

[Intel-gfx] [PATCH v6 08/11] drm/i915: Add dev.i915.perf_stream_paranoid sysctl option

Consistent with the kernel.perf_event_paranoid sysctl option that can allow non-root users to access system wide cpu metrics, this can optionally allow non-root users to access system wide OA counter metrics from Gen graphics hardware. Signed-off-by: Robert Bragg

[Intel-gfx] [PATCH v6 06/11] drm/i915: Enable i915 perf stream for Haswell OA unit

Gen graphics hardware can be set up to periodically write snapshots of performance counters into a circular buffer via its Observation Architecture and this patch exposes that capability to userspace via the i915 perf interface. v2: Make sure to initialize ->specific_ctx_id when opening,

[Intel-gfx] [PATCH v6 09/11] drm/i915: add oa_event_min_timer_exponent sysctl

The minimal sampling period is now configurable via a dev.i915.oa_min_timer_exponent sysctl parameter. Following the precedent set by perf, the default is the minimum that won't (on its own) exceed the default kernel.perf_event_max_sample_rate default of 10 samples/s. Signed-off-by: Robert

[Intel-gfx] [PATCH v6 10/11] drm/i915: Add more Haswell OA metric sets

This adds 'compute', 'compute extended', 'memory reads', 'memory writes' and 'sampler balance' metric sets for Haswell. The code is auto generated from an XML description of metric sets, currently maintained in gputop, ref: https://github.com/rib/gputop > gputop-data/oa-*.xml >

[Intel-gfx] [PATCH v6 05/11] drm/i915: Add 'render basic' Haswell OA unit config

Adds a static OA unit, MUX + B Counter configuration for basic render metrics on Haswell. This is auto generated from an XML description of metric sets, currently maintained in gputop, ref: https://github.com/rib/gputop > gputop-data/oa-*.xml > scripts/i915-perf-kernelgen.py $ make -C

[Intel-gfx] [PATCH v6 01/11] drm/i915: Add i915 perf infrastructure

Adds base i915 perf infrastructure for Gen performance metrics. This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64 properties to configure a stream of metrics and returns a new fd usable with standard VFS system calls including read() to read typed and sized records; ioctl()

[Intel-gfx] [PATCH v6 02/11] drm/i915: rename OACONTROL GEN7_OACONTROL

OACONTROL changes quite a bit for gen8, with some bits split out into a per-context OACTXCONTROL register. Rename now before adding more gen7 OA registers Signed-off-by: Robert Bragg Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/gvt/handlers.c

[Intel-gfx] [PATCH v6 04/11] drm/i915: don't whitelist oacontrol in cmd parser

Being able to program OACONTROL from a non-privileged batch buffer is not sufficient to be able to configure the OA unit. This was originally allowed to help enable Mesa to expose OA counters via the INTEL_performance_query extension, but the current implementation based on programming OACONTROL

[Intel-gfx] [PATCH v6 03/11] drm/i915: return EACCES for check_cmd() failures

check_cmd() is checking whether a command adheres to certain restrictions that ensure it's safe to execute within a privileged batch buffer. Returning false implies a privilege problem, not that the command is invalid. The distinction makes the difference between allowing the buffer to be

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On Thu, 20 Oct 2016, Imre Deak wrote: > On Thu, 2016-10-20 at 21:20 +0300, Jani Nikula wrote: >> On Thu, 20 Oct 2016, Imre Deak wrote: >> > + bool desc_valid; >> > + struct intel_dp_desc desc; >> >> I guess we could cache the desc in intel_dp

Re: [Intel-gfx] [PATCH i-g-t 0/3] Convert sh scripts to C variants.

On Thu, 20 Oct 2016, Marius Vlad wrote: > This series adds some library support to help converting sh > scripts to C version. Converted drv_module_reload_basic and > kms_sysfs_edid_timing. > 18 files changed, 600 insertions(+), 180 deletions(-) Someone please justify

Re: [Intel-gfx] [PATCH 12/41] drm/i915: Introduce an internal allocator for disposable private objects

On Thu, Oct 20, 2016 at 05:22:23PM +0100, Tvrtko Ursulin wrote: > > On 20/10/2016 16:03, Chris Wilson wrote: > >Quite a few of our objects used for internal hardware programming do not > >benefit from being swappable or from being zero initialised. As such > >they do not benefit from using a

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On Thu, 20 Oct 2016, Imre Deak wrote: > On Thu, 2016-10-20 at 22:24 +0300, Jani Nikula wrote: >> On Thu, 20 Oct 2016, Jani Nikula wrote: >> > On Thu, 20 Oct 2016, Imre Deak wrote: >> > > On my APL the LSPCON firmware resumes in

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Move down skl/kbl ddi iboost and n_edp_entires fixup

On Fri, Sep 30, 2016 at 11:05:56AM -0700, Rodrigo Vivi wrote: > No functional change. > Only moving this fixup block out of ddi_translation definitions > so we can split skl and kbl cleanly. > > Cc: Manasi Navare > Signed-off-by: Rodrigo Vivi

Re: [Intel-gfx] [PATCH i-g-t 1/3] lib/{igt_sysfs, igt_aux}: Make available to other users kick_fbcon() (unbind_fbcon()), and added helpers to igt_aux.

On Thu, Oct 20, 2016 at 10:36:47PM +0300, Marius Vlad wrote: > +int > +igt_pkill(int sig, const char *comm) > +{ > + int err = 0, try = 5; > + PROCTAB *proc; > + proc_t *proc_info; > + > + proc = openproc(PROC_FILLCOM | PROC_FILLSTAT | PROC_FILLARG); > + igt_assert(proc !=

Re: [Intel-gfx] [PATCH i-g-t 2/3] tests/drv_module_reload_basic: Convert sh script to C version.

On Thu, Oct 20, 2016 at 10:36:48PM +0300, Marius Vlad wrote: > +static const char *tests[] = { > + "gem_alive", "gem_exec_store" > +}; gem_alive is just a single ioctl query, simpler and move obvious to do it inline. Then remove tests/gem_alive.c, but it may live on as tools/gem_alive.c (or

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On Thu, 2016-10-20 at 22:24 +0300, Jani Nikula wrote: > On Thu, 20 Oct 2016, Jani Nikula wrote: > > On Thu, 20 Oct 2016, Imre Deak wrote: > > > On my APL the LSPCON firmware resumes in PCON mode as opposed to the > > > expected LS mode. It also appears

[Intel-gfx] [PATCH i-g-t 1/3] lib/{igt_sysfs, igt_aux}: Make available to other users kick_fbcon() (unbind_fbcon()), and added helpers to igt_aux.

Previously under unbind_fbcon(), disable/enable framebuffer console. lib/igt_aux: Added helpers to help convert sh scripts to C version. libkmod and procps interface. Signed-off-by: Marius Vlad --- configure.ac| 2 + lib/Makefile.am | 2 + lib/igt_aux.c | 278

[Intel-gfx] [PATCH i-g-t 0/3] Convert sh scripts to C variants.

This series adds some library support to help converting sh scripts to C version. Converted drv_module_reload_basic and kms_sysfs_edid_timing. Marius Vlad (3): lib/igt_sysfs: Make available to other users kick_fbcon() function (previously under unbind_fbcon()), to disable/enable framebuffer

[Intel-gfx] [PATCH i-g-t 3/3] tests/kms_sysfs_edid_timing: Convert sh script to C version.

While at it, make available time macros to other users. Signed-off-by: Marius Vlad --- benchmarks/gem_syslatency.c | 4 --- lib/igt_core.c| 3 -- lib/igt_core.h| 3 ++ tests/Makefile.sources| 2 +- tests/drv_hangman.c

[Intel-gfx] [PATCH i-g-t 2/3] tests/drv_module_reload_basic: Convert sh script to C version.

Signed-off-by: Marius Vlad --- tests/Makefile.sources | 2 +- tests/drv_module_reload_basic | 97 --- tests/drv_module_reload_basic.c | 166 3 files changed, 167 insertions(+), 98 deletions(-)

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On Thu, 2016-10-20 at 21:20 +0300, Jani Nikula wrote: > On Thu, 20 Oct 2016, Imre Deak wrote: > > On my APL the LSPCON firmware resumes in PCON mode as opposed to the > > expected LS mode. It also appears to be in a state where AUX DPCD reads > > will succeed but return

Re: [Intel-gfx] [PATCH 00/10] mm: adjust get_user_pages* functions to explicitly pass FOLL_* flags

On Wed 19-10-16 10:23:55, Dave Hansen wrote: > On 10/19/2016 10:01 AM, Michal Hocko wrote: > > The question I had earlier was whether this has to be an explicit FOLL > > flag used by g-u-p users or we can just use it internally when mm != > > current->mm > > The reason I chose not to do that was

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On Thu, 20 Oct 2016, Jani Nikula wrote: > On Thu, 20 Oct 2016, Imre Deak wrote: >> On my APL the LSPCON firmware resumes in PCON mode as opposed to the >> expected LS mode. It also appears to be in a state where AUX DPCD reads >> will succeed but

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Print full branch/sink descriptor for all outputs

On Thu, 2016-10-20 at 21:06 +0300, Jani Nikula wrote: > On Thu, 20 Oct 2016, Imre Deak wrote: > > Extend the branch/sink descriptor info with the missing device ID > > field and print this info for eDP and LSPCON connectors too. > > > > Signed-off-by: Imre Deak

Re: [Intel-gfx] linux-next: Tree for Oct 20 (gpu/drm/i915)

On Thu, 20 Oct 2016, Daniel Vetter wrote: > On Thu, Oct 20, 2016 at 7:37 PM, Randy Dunlap wrote: >> On 10/19/16 20:20, Stephen Rothwell wrote: >>> Hi all, >>> >>> Changes since 20161019: >>> >> >> on i386: when CONFIG_ACPI is not enabled: > > Adding

Re: [Intel-gfx] [PATCH 7/8] drm/i915/gen9+: Program watermarks as a separate step during evasion

On Wed, Oct 12, 2016 at 03:28:20PM +0200, Maarten Lankhorst wrote: > Instead of running the watermark updates from the callbacks run > them from a separate hook atomic_evade_watermarks. > > This also gets rid of the global skl_results, which was required for > keeping track of the current atomic

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On Thu, 20 Oct 2016, Imre Deak wrote: > On my APL the LSPCON firmware resumes in PCON mode as opposed to the > expected LS mode. It also appears to be in a state where AUX DPCD reads > will succeed but return garbage recovering only after a few hundreds of > milliseconds.

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Print full branch/sink descriptor for all outputs

On Thu, 20 Oct 2016, Imre Deak wrote: > Extend the branch/sink descriptor info with the missing device ID > field and print this info for eDP and LSPCON connectors too. > > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_dp.c | 83 >

Re: [Intel-gfx] [PATCH 6/8] drm/i915/gen9+: Use the watermarks from crtc_state for everything.

Em Qua, 2016-10-12 às 15:28 +0200, Maarten Lankhorst escreveu: > There's no need to keep a duplicate skl_pipe_wm around any more, > everything can be discovered from crtc_state, which we pass around > correctly now even in case of plane disable. > > Signed-off-by: Maarten Lankhorst

Re: [Intel-gfx] [PATCH 6/8] drm/i915/gen9+: Use the watermarks from crtc_state for everything.

On Wed, Oct 12, 2016 at 03:28:19PM +0200, Maarten Lankhorst wrote: > There's no need to keep a duplicate skl_pipe_wm around any more, > everything can be discovered from crtc_state, which we pass around > correctly now even in case of plane disable. You might want to add some clarification that

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Add a atomic evasion step to watermark programming.

Em Qua, 2016-10-12 às 15:28 +0200, Maarten Lankhorst escreveu: > Allow the driver to write watermarks during atomic evasion. > This will make it possible to write the watermarks in a cleaner > way on gen9+. > > Signed-off-by: Maarten Lankhorst > --- >  

Re: [Intel-gfx] [PATCH 4/8] drm/i915/skl+: Clean up minimum allocations.

Em Qua, 2016-10-12 às 15:28 +0200, Maarten Lankhorst escreveu: > Move calculating minimum allocations to a helper, which cleans up the > code some more. The cursor is still allocated in advance because it > doesn't count towards data rate and should always be reserved. > > Signed-off-by: Maarten

Re: [Intel-gfx] linux-next: Tree for Oct 20 (gpu/drm/i915)

On Thu, Oct 20, 2016 at 7:37 PM, Randy Dunlap wrote: > On 10/19/16 20:20, Stephen Rothwell wrote: >> Hi all, >> >> Changes since 20161019: >> > > on i386: when CONFIG_ACPI is not enabled: Adding Zhenyu. Might be good to have a fix just for this that I directly pick up,

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: Print full branch/sink descriptor for all outputs

== Series Details == Series: series starting with [1/2] drm/i915/dp: Print full branch/sink descriptor for all outputs URL : https://patchwork.freedesktop.org/series/14123/ State : success == Summary == Series 14123v1 Series without cover letter

Re: [Intel-gfx] linux-next: Tree for Oct 20 (gpu/drm/i915)

On 10/19/16 20:20, Stephen Rothwell wrote: > Hi all, > > Changes since 20161019: > on i386: when CONFIG_ACPI is not enabled: ../drivers/gpu/drm/i915/gvt/opregion.c: In function 'intel_gvt_init_opregion': ../drivers/gpu/drm/i915/gvt/opregion.c:183:2: error: implicit declaration of function

Re: [Intel-gfx] [PATCH 2/8] drm/i915/skl+: Remove data_rate from watermark struct.

Em Qui, 2016-10-20 às 15:18 -0200, Paulo Zanoni escreveu: > Em Qua, 2016-10-19 às 15:13 -0700, Matt Roper escreveu: > > > > On Wed, Oct 12, 2016 at 03:28:15PM +0200, Maarten Lankhorst wrote: > > > > > > > > > It's only used in one function, and can be calculated without > > > caching it > > >

Re: [Intel-gfx] [PATCH 3/8] drm/i915/skl+: Remove minimum block allocation from crtc state.

Em Qua, 2016-10-19 às 15:13 -0700, Matt Roper escreveu: > On Wed, Oct 12, 2016 at 03:28:16PM +0200, Maarten Lankhorst wrote: > > > > This is not required any more now that we get fresh state from > > drm_atomic_crtc_state_for_each_plane_state. Zero all state > > in advance. > > > >

Re: [Intel-gfx] [PATCH 2/8] drm/i915/skl+: Remove data_rate from watermark struct.

Em Qua, 2016-10-19 às 15:13 -0700, Matt Roper escreveu: > On Wed, Oct 12, 2016 at 03:28:15PM +0200, Maarten Lankhorst wrote: > > > > It's only used in one function, and can be calculated without > > caching it > > in the global struct by using > > drm_atomic_crtc_state_for_each_plane_state. > >

[Intel-gfx] [PATCH 2/2] drm/i915/lspcon: Add workaround for resuming in PCON mode

On my APL the LSPCON firmware resumes in PCON mode as opposed to the expected LS mode. It also appears to be in a state where AUX DPCD reads will succeed but return garbage recovering only after a few hundreds of milliseconds. After the recovery time DPCD reads will result in the correct values

[Intel-gfx] [PATCH 1/2] drm/i915/dp: Print full branch/sink descriptor for all outputs

Extend the branch/sink descriptor info with the missing device ID field and print this info for eDP and LSPCON connectors too. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_dp.c | 83 +++-- drivers/gpu/drm/i915/intel_drv.h|

Re: [Intel-gfx] [PATCH] rtc: cmos: Don't enable interrupts in the middle of the interrupt handler

On 19/10/2016 at 21:02:04 +0300, ville.syrj...@linux.intel.com wrote : > From: Ville Syrjälä > > Using spin_lock_irq()/spin_unlock_irq() from within the interrupt > handler is a no-no. Let's save/restore the flags to avoid turning on > interrupts prematurely. > >

Re: [Intel-gfx] [PATCH 12/41] drm/i915: Introduce an internal allocator for disposable private objects

On 20/10/2016 16:03, Chris Wilson wrote: Quite a few of our objects used for internal hardware programming do not benefit from being swappable or from being zero initialised. As such they do not benefit from using a shmemfs backing storage and since they are internal and never directly exposed

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7 (rev2)

== Series Details == Series: drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7 (rev2) URL : https://patchwork.freedesktop.org/series/13949/ State : warning == Summary == Series 13949v2 drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7

Re: [Intel-gfx] [PATCH 15/41] drm/i915: Use a radixtree for random access to the object's backing storage

On 20/10/2016 16:03, Chris Wilson wrote: A while ago we switched from a contiguous array of pages into an sglist, for that was both more convenient for mapping to hardware and avoided the requirement for a vmalloc array of pages on every object. However, certain GEM API calls (like pwrite,

Re: [Intel-gfx] [PATCH 08/41] drm/i915: Remove superfluous wait_for_error() from throttle-ioctl

On to, 2016-10-20 at 16:03 +0100, Chris Wilson wrote: > Reviewed-by: Joonas Lahtinen " at the end of line. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx

Re: [Intel-gfx] [PATCH 39/41] drm/i915: Enable multiple timelines

On Thu, Oct 20, 2016 at 06:26:04PM +0300, Joonas Lahtinen wrote: > On pe, 2016-10-14 at 13:18 +0100, Chris Wilson wrote: > > With the infrastructure converted over to tracking multiple timelines in > > the GEM API whilst preserving the efficiency of using a single execution > > timeline

[Intel-gfx] [PATCH RESEND v2] drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7

Dropping WA because it was for early steppings. It is fixed in newer preproduction and all production revisions. v2: add references, updated commit message References: HSD#2126385, HSD#2131381, BSID#0764 Cc: Mika Kuoppala Cc: Chris Wilson Cc:

Re: [Intel-gfx] [PATCH 39/41] drm/i915: Enable multiple timelines

On pe, 2016-10-14 at 13:18 +0100, Chris Wilson wrote: > With the infrastructure converted over to tracking multiple timelines in > the GEM API whilst preserving the efficiency of using a single execution > timeline internally, we can now assign a separate timeline to every > context with

Re: [Intel-gfx] [PATCH 16/18] drm/i915: Enable multiple timelines

On to, 2016-10-20 at 13:49 +0100, Chris Wilson wrote: > On Mon, Sep 19, 2016 at 06:52:13PM +0300, Joonas Lahtinen wrote: > > > > On ke, 2016-09-14 at 07:52 +0100, Chris Wilson wrote: > > > > > > @@ -315,17 +304,42 @@ submit_notify(struct i915_sw_fence *fence, enum > > > i915_sw_fence_notify

[Intel-gfx] [PATCH 22/41] drm/i915: Implement pwrite without struct-mutex

We only need struct_mutex within pwrite for a brief window where we need to serialise with rendering and control our cache domains. Elsewhere we can rely on the backing storage being pinned, and forgive userspace any races against us. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 13/41] drm/i915: Reuse the active golden render state batch

The golden render state is constant, but we recreate the batch setting it up for every new context. If we keep that batch in a volatile cache we can safely reuse it whenever we need to initialise a new context. We mark the pages as purgeable and use the shrinker to recover pages from the batch

[Intel-gfx] [PATCH 23/41] drm/i915: Acquire the backing storage outside of struct_mutex in set-domain

As we can locklessly (well struct_mutex-lessly) acquire the backing storage, do so in set-domain-ioctl to reduce the contention on the struct_mutex. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen ---

Re: [Intel-gfx] [PATCH] drm/i915: Add i915 perf infrastructure

On ke, 2016-10-19 at 17:35 +0100, Robert Bragg wrote: > I'll add a default: with MISSING_CASE as that looks like an i915- > specific convention; though it seems like a real shame to defer > missing case issues to runtime errors instead of taking advantage of > the compiler complaining at build

Re: [Intel-gfx] [PATCH] drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate

On Thu, Oct 20, 2016 at 05:29:36PM +0300, Mika Kuoppala wrote: > Arkadiusz Hiler writes: > > > When invalidating RCS TLB the device can enter RC6 state interrupting > > the process, therefore the need for render forcewake for the whole > > procedure. > > > > This WA is

Re: [Intel-gfx] [PATCH 1/2] shmem: Support for registration of Driver/file owner specific ops

On ke, 2016-10-19 at 20:41 +0530, akash goel wrote: > On Thu, Mar 24, 2016 at 5:41 PM, Joonas Lahtinen > > wrote: > > On ke, 2016-03-23 at 11:39 +0530, akash.g...@intel.com wrote: > > > @@ -34,11 +34,28 @@ struct shmem_sb_info { > > >   struct mempolicy *mpol; 

[Intel-gfx] [PATCH 38/41] drm/i915: Defer setting of global seqno on request to submission

Defer the assignment of the global seqno on a request to its submission. In the next patch, we will only allocate the global seqno at that time, here we are just enabling the wait-for-submission before wait-for-seqno paths. Signed-off-by: Chris Wilson Reviewed-by:

Re: [Intel-gfx] [PATCH] drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidate

On Thu, Oct 20, 2016 at 12:57:31PM +0200, Arkadiusz Hiler wrote: > When invalidating RCS TLB the device can enter RC6 state interrupting > the process, therefore the need for render forcewake for the whole > procedure. > > This WA is needed for all production SKL SKUs. > > References:

Re: [Intel-gfx] [PATCH] drm: Complete CEA modedb(VIC 1-107)

Regards Shashank On 10/20/2016 8:00 PM, Alex Deucher wrote: On Thu, Oct 20, 2016 at 6:28 AM, Shashank Sharma wrote: CEA-861-F specs defines new 4k video modes to be used with HDMI 2.0 EDIDs. These modes start at VIC=93 and go all the way till VIC=107. Our

[Intel-gfx] [PATCH 32/41] drm/i915: Rename ->emit_request to ->emit_breadcrumb

Now that the emission of the request tail and its submission to hardware are two separate steps, engine->emit_request() is confusing. engine->emit_request() is called to emit the breadcrumb commands for the request into the ring, name it such (engine->emit_breadcrumb). Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 40/41] drm/i915: Enable userspace to opt-out of implicit fencing

Userspace is faced with a dilemma. The kernel requires implicit fencing to manage resource usage (we always must wait for the GPU to finish before releasing its PTE) and for third parties. However, userspace may wish to avoid this serialisation if it is either using explicit fencing between

[Intel-gfx] [PATCH 39/41] drm/i915: Enable multiple timelines

With the infrastructure converted over to tracking multiple timelines in the GEM API whilst preserving the efficiency of using a single execution timeline internally, we can now assign a separate timeline to every context with full-ppgtt. v2: Add a comment to indicate the xfer between timelines

[Intel-gfx] [PATCH 25/41] drm/i915: Use lockless object free

Having moved the locked phase of freeing an object to a separate worker, we can now declare to the core that we only need the unlocked variant of driver->gem_free_object, and can use the simple unreference internally. Signed-off-by: Chris Wilson Reviewed-by: Joonas

[Intel-gfx] [PATCH 26/41] drm/i915: Move GEM activity tracking into a common struct reservation_object

In preparation to support many distinct timelines, we need to expand the activity tracking on the GEM object to handle more than just a request per engine. We already use the struct reservation_object on the dma-buf to handle many fence contexts, so integrating that into the GEM object itself is

[Intel-gfx] [PATCH 14/41] drm/i915: Markup GEM API with lockdep asserts

Add lockdep_assert_held(struct_mutex) to the API preamble of the internal GEM interfaces. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 2 ++

[Intel-gfx] [PATCH 21/41] drm/i915: Implement pread without struct-mutex

We only need struct_mutex within pread for a brief window where we need to serialise with rendering and control our cache domains. Elsewhere we can rely on the backing storage being pinned, and forgive userspace any races against us. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 37/41] drm/i915: Reserve space in the global seqno during request allocation

A restriction on our global seqno is that they cannot wrap, and that we cannot use the value 0. This allows us to detect when a request has not yet been submitted, its global seqno is still 0, and ensures that hardware semaphores are monotonic as required by older hardware. To meet these

[Intel-gfx] [PATCH 27/41] drm/i915: Restore nonblocking awaits for modesetting

After combining the dma-buf reservation object and the GEM reservation object, we lost the ability to do a nonblocking wait on the i915 request (as we blocked upon the reservation object during prepare_fb). We can instead convert the reservation object into a fence upon which we can asynchronously

[Intel-gfx] [PATCH 33/41] drm/i915: Record space required for breadcrumb emission

In the next patch, we will use deferred breadcrumb emission. That requires reserving sufficient space in the ringbuffer to emit the breadcrumb, which first requires us to know how large the breadcrumb is. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen

[Intel-gfx] [PATCH 41/41] drm/i915: Support explicit fencing for execbuf

Now that the user can opt-out of implicit fencing, we need to give them back control over the fencing. We employ sync_file to wrap our drm_i915_gem_request and provide an fd that userspace can merge with other sync_file fds and pass back to the kernel to wait upon before future execution.

[Intel-gfx] [PATCH 30/41] drm/i915: Wait first for submission, before waiting for request completion

In future patches, we will no longer be able to wait on a static global seqno and instead have to break our wait up into phases. First we wait for the global seqno assignment (upon submission to hardware), and once submitted we wait for the hardware to complete. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 31/41] drm/i915: Introduce a global_seqno for each request

Though we will have multiple timelines, we still have a single timeline of execution. This we can use to provide an execution and retirement order of requests. This keeps tracking execution of requests simple, and vital for preserving a single waiter (i.e. so that we can order the waiters so that

[Intel-gfx] [PATCH 18/41] drm/i915: Pass around sg_table to get_pages/put_pages backend

The plan is to move obj->pages out from under the struct_mutex into its own per-object lock. We need to prune any assumption of the struct_mutex from the get_pages/put_pages backends, and to make it easier we pass around the sg_table to operate on rather than indirectly via the obj.

[Intel-gfx] [PATCH 36/41] drm/i915: Create a unique name for the context

This will be used for communicating issues with this context to userspace, so we want to identify the parent process and the individual context. Note that the name isn't quite unique, it makes the presumption of there only being a single device fd per process. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 12/41] drm/i915: Introduce an internal allocator for disposable private objects

Quite a few of our objects used for internal hardware programming do not benefit from being swappable or from being zero initialised. As such they do not benefit from using a shmemfs backing storage and since they are internal and never directly exposed to the user, we do not need to worry about

[Intel-gfx] [PATCH 28/41] drm/i915: Combine seqno + tracking into a global timeline struct

Our timelines are more than just a seqno. They also provide an ordered list of requests to be executed. Due to the restriction of handling individual address spaces, we are limited to a timeline per address space but we use a fence context per engine within. Our first step to introducing

[Intel-gfx] [PATCH 24/41] drm/i915: Move object release to a freelist + worker

We want to hide the latency of releasing objects and their backing storage from the submission, so we move the actual free to a worker. This allows us to switch to struct_mutex freeing of the object in the next patch. Furthermore, if we know that the object we are dereferencing remains valid for

[Intel-gfx] [PATCH 19/41] drm/i915: Move object backing storage manipulation to its own locking

Break the allocation of the backing storage away from struct_mutex into a per-object lock. This allows parallel page allocation, provided we can do so outside of struct_mutex (i.e. set-domain-ioctl, pwrite, GTT fault), i.e. before execbuf! The increased cost of the atomic counters are hidden

[Intel-gfx] [PATCH 20/41] drm/i915/dmabuf: Acquire the backing storage outside of struct_mutex

Use the per-object mm.lock to allocate the backing storage (and hold a reference to it across the dmabuf access) without resorting to struct_mutex. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen ---

[Intel-gfx] [PATCH 34/41] drm/i915: Defer breadcrumb emission

Move the actual emission of the breadcrumb for closing the request from i915_add_request() to the submit callback. (It can be moved later when required.) This allows us to defer the allocation of the global_seqno from request construction to actual submission, allowing us to emit the requests out

[Intel-gfx] [PATCH 29/41] drm/i915: Queue the idling context switch after all other timelines

Before suspend, we wait for the switch to the kernel context. In order for all the other context images to be complete upon suspend, that switch must be the last operation by the GPU (i.e. this idling request must not overtake any pending requests). To make this request execute last, we make it

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