Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/2] PCI / PM: Add needs_resume flag to avoid suspend complete optimization

This is excellent, Imre! Check results for extendedlist: http://intel-gfx-ci.fi.intel.com/archive/results/CI_IGT_test/ The majority previously "failed" or "dmesg-warn" after: igt@kms_fbcon_fbt@fbc-suspend, are now passing for BDW, SKL and KBL. That is hundreds of passing tests. >

Re: [Intel-gfx] [RFC PATCH 5/6] drm/i915/gvt: dmabuf support for GVT-g

Hi Chis, do you have any comments for this problem? >> +static struct sg_table * >> +intel_vgpu_create_sg_pages(struct drm_device *dev, u32 start, u32 >> +num_pages) { >> +struct drm_i915_private *dev_priv = dev->dev_private; >> +struct sg_table *st; >> +struct scatterlist *sg; >> +

Re: [Intel-gfx] [RFC PATCH 6/6] drm/i915/gvt: support QEMU getting the dmabuf

Hi Alex, do you have any comments for this interface? >-Original Message- >From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On >Behalf Of Chen, Xiaoguang >Sent: Wednesday, May 03, 2017 9:39 AM >To: Gerd Hoffmann >Cc: Tian, Kevin

[Intel-gfx] [PATCH v5 4/9] drm/i915: Allow choosing how to adjust brightness if both supported

Add option to allow choosing how to adjust brightness if panel supports both PWM pin and AUX channel. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/i915_params.c| 6 -- drivers/gpu/drm/i915/i915_params.h| 2 +-

[Intel-gfx] [PATCH v5 7/9] drm/i915: Restore brightness level in aux backlight driver

Some panel will default to zero brightness when turning the panel off and on again. This patch restores last brightness level back when panel is turning back on. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1 + 1 file changed, 1

[Intel-gfx] [PATCH v5 2/9] drm/i915: Correctly enable backlight brightness adjustment via DPCD

intel_dp_aux_enable_backlight() assumed that the register BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has value 01 (DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET) when initialize. This patch fixed that by handling all cases of that register. Signed-off-by: Puthikorn Voravootivat ---

[Intel-gfx] [PATCH v5 6/9] drm/i915: Support dynamic backlight via DPCD register

This patch enables dynamic backlight by default for eDP panel that supports this feature via DPCD register and set minimum / maximum brightness to 0% and 100% of the normal brightness. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c |

[Intel-gfx] [PATCH v5 0/9] Enhancement to intel_dp_aux_backlight driver

This patch set contain 9 patches. - First five patches fix bug in the driver and allow choosing which way to adjust brightness if both PWM pin and AUX are supported - Next patch adds enable DBC by default - Next patch makes the driver restore last brightness level after turning display off and

[Intel-gfx] [PATCH v5 5/9] drm/i915: Set backlight mode before enable backlight

We should set backlight mode register before set register to enable the backlight. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Intel-gfx] [PATCH v5 9/9] drm/i915: Set PWM divider to match desired frequency in vbt

Read desired PWM frequency from panel vbt and calculate the value for divider in DPCD address 0x724 and 0x728 to match that frequency as close as possible. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 71

[Intel-gfx] [PATCH v5 3/9] drm/i915: Drop AUX backlight enable check for backlight control

There are some panel that (1) does not support display backlight enable via AUX (2) support display backlight adjustment via AUX (3) support display backlight enable via eDP BL_ENABLE pin The current driver required that (1) must be support to enable (2). This patch drops that requirement.

[Intel-gfx] [PATCH v5 8/9] drm: Add definition for eDP backlight frequency

This patch adds the following definition - Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap register which only use bit 0:4 - Base frequency (27 MHz) for backlight PWM frequency generator. Signed-off-by: Puthikorn Voravootivat --- include/drm/drm_dp_helper.h | 2 ++ 1

[Intel-gfx] [PATCH v5 1/9] drm/i915: Fix cap check for intel_dp_aux_backlight driver

intel_dp_aux_backlight driver should check for the DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP before enable the driver. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff

Re: [Intel-gfx] [PATCH v7 03/20] drm/i915: Add support for per engine reset recovery

On 27/04/17 16:50, Chris Wilson wrote: On Thu, Apr 27, 2017 at 04:12:43PM -0700, Michel Thierry wrote: From: Arun Siluvery This change implements support for per-engine reset as an initial, less intrusive hang recovery option to be attempted before falling back

Re: [Intel-gfx] [RFC] tests/pm_sseu: Add subtest to verify UMD can configure render powerclock state

On 05/03/2017 04:53 PM, Chris Wilson wrote: On Wed, May 03, 2017 at 09:43:08AM +, Oscar Mateo wrote: On 05/03/2017 08:59 AM, Chris Wilson wrote: On Tue, May 02, 2017 at 03:08:27PM +, Oscar Mateo wrote: Cc: Dmitry Rogozhkin Cc: Chris Wilson

Re: [Intel-gfx] [PATCH] drm/i915: Use engine->context_pin() to report the intel_ring

On 05/03/2017 12:46 PM, Chris Wilson wrote: Since unifying ringbuffer/execlist submission to use engine->pin_context, we ensure that the intel_ring is available before we start constructing the request. We can therefore move the assignment of the request->ring to the central

Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree

Hi all, On Fri, 21 Apr 2017 12:10:14 +1000 Stephen Rothwell wrote: > > After merging the drm-misc tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > drivers/tee/tee_shm.c:87:2: error: unknown field 'kmap_atomic' specified in > initializer >

Re: [Intel-gfx] [PATCH RESEND v4 1/6] drm/i915: Add DPCD preferred mode for backlight control

On Wed, May 3, 2017 at 2:11 AM, Jani Nikula wrote: > On Tue, 18 Apr 2017, Puthikorn Voravootivat wrote: > > Currently the intel_dp_aux_backlight driver requires eDP panel > > to not also support backlight adjustment via PWM pin to use > > this

Re: [Intel-gfx] [PATCH 08/67] drm/i915/cnl: Cannonlake uses CNP PCH.

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Rodrigo Vivi >Sent: Thursday, April 6, 2017 12:15 PM >To: intel-gfx@lists.freedesktop.org >Cc: Vivi, Rodrigo >Subject: [Intel-gfx] [PATCH 08/67] drm/i915/cnl:

[Intel-gfx] [PATCH] drm/i915/cnp: Backlight support for CNP.

From: Rodrigo Vivi Split out BXT and CNP's setup_backlight(),enable_backlight(), disable_backlight() and hz_to_pwm() into two separate functions instead of reusing BXT function. Reuse set_backlight() and get_backlight() since they have no reference to the utility pin.

[Intel-gfx] [PATCH] drm/i915/cnp: Backlight support for CNP.

From: Rodrigo Vivi Split out BXT and CNP's setup_backlight(),enable_backlight(), disable_backlight() and hz_to_pwm() into two separate functions instead of reusing BXT function. Reuse set_backlight() and get_backlight() since they have no reference to the utility pin.

Re: [Intel-gfx] [PATCH RESEND v4 6/6] drm/i915: Set PWM divider to match desired frequency in vbt

On Wed, May 3, 2017 at 7:12 AM, Jani Nikula wrote: > On Tue, 18 Apr 2017, Puthikorn Voravootivat wrote: > > Read desired PWM frequency from panel vbt and calculate the > > value for divider in DPCD address 0x724 and 0x728 to match > > that

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement dma_buf_ops->kmap (rev2)

On Wed, May 03, 2017 at 08:56:59PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Implement dma_buf_ops->kmap (rev2) > URL : https://patchwork.freedesktop.org/series/22704/ > State : success > > == Summary == > > Series 22704v2 drm/i915: Implement dma_buf_ops->kmap >

Re: [Intel-gfx] [PATCH RESEND v4 3/6] drm/i915: Support dynamic backlight via DPCD register

On Tue, May 2, 2017 at 8:00 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > On Tue, 2017-04-18 at 16:48 -0700, Puthikorn Voravootivat wrote: > > This patch enables dynamic backlight by default for eDP > > panel that supports this feature via DPCD register and > > set minimum /

Re: [Intel-gfx] [CI] drm/i915: Implement dma_buf_ops->kmap

On Wed, May 03, 2017 at 09:42:54PM +0100, Chris Wilson wrote: > On Wed, May 03, 2017 at 09:25:17PM +0100, Chris Wilson wrote: > > Since kmap allows us to block we can pin the pages and use our normal > > page lookup routine making the implementation simple, or as some might > > say quick and

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement dma_buf_ops->kmap (rev3)

== Series Details == Series: drm/i915: Implement dma_buf_ops->kmap (rev3) URL : https://patchwork.freedesktop.org/series/22704/ State : failure == Summary == Series 22704v3 drm/i915: Implement dma_buf_ops->kmap https://patchwork.freedesktop.org/api/1.0/series/22704/revisions/3/mbox/ Test

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Implement dma_buf_ops->kmap (rev2)

== Series Details == Series: drm/i915: Implement dma_buf_ops->kmap (rev2) URL : https://patchwork.freedesktop.org/series/22704/ State : success == Summary == Series 22704v2 drm/i915: Implement dma_buf_ops->kmap https://patchwork.freedesktop.org/api/1.0/series/22704/revisions/2/mbox/ Test

[Intel-gfx] [PATCH] drm/i915: Implement dma_buf_ops->kmap

Since kmap allows us to block we can pin the pages and use our normal page lookup routine making the implementation simple, or as some might say quick and dirty. v2: Limit the whole-object-pin to the page lookup, and use the page->mapcount to keep the page itself around for the caller. Testcase:

Re: [Intel-gfx] [CI] drm/i915: Implement dma_buf_ops->kmap

On Wed, May 03, 2017 at 09:25:17PM +0100, Chris Wilson wrote: > Since kmap allows us to block we can pin the pages and use our normal > page lookup routine making the implementation simple, or as some might > say quick and dirty. > > Testcase: igt/drv_selftest/dmabuf > Testcase: igt/prime_rw >

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

Op 03-05-17 om 20:03 schreef Ville Syrjälä: > On Wed, May 03, 2017 at 06:18:46PM +0200, Maarten Lankhorst wrote: >> Op 03-05-17 om 18:07 schreef Ville Syrjälä: >>> On Wed, May 03, 2017 at 05:53:34PM +0200, Maarten Lankhorst wrote: Op 03-05-17 om 16:11 schreef Ville Syrjälä: > On Wed, May

[Intel-gfx] [CI] drm/i915: Implement dma_buf_ops->kmap

Since kmap allows us to block we can pin the pages and use our normal page lookup routine making the implementation simple, or as some might say quick and dirty. Testcase: igt/drv_selftest/dmabuf Testcase: igt/prime_rw Signed-off-by: Chris Wilson Reviewed-by: Joonas

Re: [Intel-gfx] [PATCH] drm/mm: Split up long running selftests with cond_resched()

On Thu, Mar 30, 2017 at 01:16:26PM +0300, Joonas Lahtinen wrote: > On ke, 2017-03-29 at 10:10 +0100, Chris Wilson wrote: > > Scatter a few cond_resched() in between phases of the drm_mm selftests > > to try and prevent us incurring the wrath of the NMI watchdog. > > > > Signed-off-by: Chris

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

Hi Ben, [auto build test WARNING on drm/drm-next] [also build test WARNING on next-20170503] [cannot apply to v4.11] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Ben-Widawsky/drm-Plumb

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove kref from i915_sw_fence

== Series Details == Series: series starting with [1/2] drm/i915: Remove kref from i915_sw_fence URL : https://patchwork.freedesktop.org/series/23902/ State : success == Summary == Series 23902v1 Series without cover letter

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

Hi Ben, [auto build test WARNING on drm/drm-next] [also build test WARNING on next-20170503] [cannot apply to v4.11] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Ben-Widawsky/drm-Plumb

[Intel-gfx] [PATCH 1/2] drm/i915: Remove kref from i915_sw_fence

My original intention was for i915_sw_fence to be the base class and provide the reference count for the container. This was from starting with a design to handle async_work. In practice, for i915 we embed fences into structs which have their own independent reference counting, making the

[Intel-gfx] [PATCH 2/2] drm/i915: Import the kfence selftests for i915_sw_fence

A long time ago, I wrote some selftests for the struct kfence idea. Now that we have infrastructure in i915/igt for running kselftests, include some for i915_sw_fence. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/Kconfig.debug | 12 +

Re: [Intel-gfx] [PATCH v2 9/15] drm/i915: expose _SLICE_MASK GETPARM

On 03/05/17 09:33, Chris Wilson wrote: On Wed, May 03, 2017 at 09:23:56AM -0700, Lionel Landwerlin wrote: From: Robert Bragg Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

On Wed, May 03, 2017 at 06:18:46PM +0200, Maarten Lankhorst wrote: > Op 03-05-17 om 18:07 schreef Ville Syrjälä: > > On Wed, May 03, 2017 at 05:53:34PM +0200, Maarten Lankhorst wrote: > >> Op 03-05-17 om 16:11 schreef Ville Syrjälä: > >>> On Wed, May 03, 2017 at 04:06:37PM +0200, Maarten Lankhorst

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

On Wed, May 03, 2017 at 06:45:05PM +0200, Daniel Vetter wrote: > On Wed, May 03, 2017 at 03:52:23PM +0100, Liviu Dudau wrote: > > On Wed, May 03, 2017 at 03:14:56PM +0100, Daniel Stone wrote: > > > On 3 May 2017 at 15:07, Liviu Dudau wrote: > > > > On Wed, May 03, 2017 at

Re: [Intel-gfx] [RFC] tests/pm_sseu: Add subtest to verify UMD can configure render powerclock state

On Wed, May 03, 2017 at 09:43:08AM +, Oscar Mateo wrote: > > > > On 05/03/2017 08:59 AM, Chris Wilson wrote: > >On Tue, May 02, 2017 at 03:08:27PM +, Oscar Mateo wrote: > >>Cc: Dmitry Rogozhkin > >>Cc: Chris Wilson >

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

On Wed, May 03, 2017 at 03:52:23PM +0100, Liviu Dudau wrote: > On Wed, May 03, 2017 at 03:14:56PM +0100, Daniel Stone wrote: > > On 3 May 2017 at 15:07, Liviu Dudau wrote: > > > On Wed, May 03, 2017 at 02:45:26PM +0100, Daniel Stone wrote: > > >> It does deserve a much better

Re: [Intel-gfx] [RFC] tests/pm_sseu: Add subtest to verify UMD can configure render powerclock state

On 05/03/2017 08:59 AM, Chris Wilson wrote: On Tue, May 02, 2017 at 03:08:27PM +, Oscar Mateo wrote: Cc: Dmitry Rogozhkin Cc: Chris Wilson Signed-off-by: Oscar Mateo --- tests/pm_sseu.c | 105

Re: [Intel-gfx] [PATCH v2 9/15] drm/i915: expose _SLICE_MASK GETPARM

On Wed, May 03, 2017 at 09:23:56AM -0700, Lionel Landwerlin wrote: > From: Robert Bragg > > Enables userspace to determine the number of slices enabled and also > know what specific slices are enabled. This information is required, for > example, to be able to analyse some

Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

On Wed, May 03, 2017 at 09:12:18AM +, Oscar Mateo wrote: >On 05/03/2017 08:52 AM, Mika Kuoppala wrote: > > Oscar Mateo [1] writes: > > > On 05/02/2017 09:17 AM, Mika Kuoppala wrote: > > Chris Wilson [2] writes: > > > On Fri, Apr

Re: [Intel-gfx] [PATCH RESEND v4 5/6] drm: Add definition for eDP backlight frequency

On Wed, May 03, 2017 at 03:49:23PM +0300, Jani Nikula wrote: > On Tue, 02 May 2017, Manasi Navare wrote: > > On Tue, Apr 18, 2017 at 04:48:23PM -0700, Puthikorn Voravootivat wrote: > > > > Since this adds definitions in the DRM layer, you need to copy > > the

[Intel-gfx] [PATCH v2 9/15] drm/i915: expose _SLICE_MASK GETPARM

From: Robert Bragg Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice

[Intel-gfx] [PATCH v2 9/15] drm/i915: expose _SUBSLICE_MASK GETPARM

From: Robert Bragg Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

Op 03-05-17 om 18:07 schreef Ville Syrjälä: > On Wed, May 03, 2017 at 05:53:34PM +0200, Maarten Lankhorst wrote: >> Op 03-05-17 om 16:11 schreef Ville Syrjälä: >>> On Wed, May 03, 2017 at 04:06:37PM +0200, Maarten Lankhorst wrote: Op 03-05-17 om 15:45 schreef Ville Syrjälä: > On Mon, May

Re: [Intel-gfx] [PATCH] drm/i915: Allow null render state batchbuffers bigger than one page

On 05/03/2017 08:52 AM, Mika Kuoppala wrote: Oscar Mateo writes: On 05/02/2017 09:17 AM, Mika Kuoppala wrote: Chris Wilson writes: On Fri, Apr 28, 2017 at 09:11:06AM +, Oscar Mateo wrote: The new batchbuffer for CNL surpasses the

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

On Wed, May 03, 2017 at 05:53:34PM +0200, Maarten Lankhorst wrote: > Op 03-05-17 om 16:11 schreef Ville Syrjälä: > > On Wed, May 03, 2017 at 04:06:37PM +0200, Maarten Lankhorst wrote: > >> Op 03-05-17 om 15:45 schreef Ville Syrjälä: > >>> On Mon, May 01, 2017 at 03:34:34PM +0200, Maarten Lankhorst

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Enable send function only after successful init

On Wed, May 03, 2017 at 05:54:43PM +0200, Michal Wajdeczko wrote: > On Wed, May 03, 2017 at 11:47:12AM +0100, Chris Wilson wrote: > > On Tue, May 02, 2017 at 10:32:42AM +, Michal Wajdeczko wrote: > > > It is safer to setup valid send function after successful GuC > > > hardware initialization.

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Enable send function only after successful init

On Wed, May 03, 2017 at 11:47:12AM +0100, Chris Wilson wrote: > On Tue, May 02, 2017 at 10:32:42AM +, Michal Wajdeczko wrote: > > It is safer to setup valid send function after successful GuC > > hardware initialization. In addition we prepare placeholder > > where we can setup any alternate

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

Op 03-05-17 om 16:11 schreef Ville Syrjälä: > On Wed, May 03, 2017 at 04:06:37PM +0200, Maarten Lankhorst wrote: >> Op 03-05-17 om 15:45 schreef Ville Syrjälä: >>> On Mon, May 01, 2017 at 03:34:34PM +0200, Maarten Lankhorst wrote: The watermarks it should calculate against are the old optimal

[Intel-gfx] [maintainer-tools PATCH v3] dim: Add pull request tag template

Each pull request is accompanied by a summary that is stored in the git tag from which it is generated. These summaries all share the same template with headers classifying changes to UAPI, Cross-subsystem, Core, and Drivers. This patch adds this template to the tag summary automatically in dim

Re: [Intel-gfx] [PATCHv3 2/3] drm/prime: Introduce drm_gem_prime_import_platform

On Wed, May 03, 2017 at 05:07:03PM +0200, Daniel Vetter wrote: > On Wed, May 03, 2017 at 07:40:51AM -0700, Laura Abbott wrote: > > On 05/03/2017 12:39 AM, Daniel Vetter wrote: > > > On Tue, May 02, 2017 at 09:22:13PM +0100, Chris Wilson wrote: > > >> On Tue, May 02, 2017 at 10:02:07AM -0700, Laura

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote: > Updated blob layout (Rob, Daniel, Kristian, xerpi) > > Cc: Rob Clark > Cc: Daniel Stone > Cc: Kristian H. Kristensen > Signed-off-by: Ben Widawsky

Re: [Intel-gfx] [PATCHv3 2/3] drm/prime: Introduce drm_gem_prime_import_platform

On Wed, May 03, 2017 at 07:40:51AM -0700, Laura Abbott wrote: > On 05/03/2017 12:39 AM, Daniel Vetter wrote: > > On Tue, May 02, 2017 at 09:22:13PM +0100, Chris Wilson wrote: > >> On Tue, May 02, 2017 at 10:02:07AM -0700, Laura Abbott wrote: > >>> /** > >>> + * drm_gem_prime_import_platform -

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

On Wed, May 03, 2017 at 03:14:56PM +0100, Daniel Stone wrote: > On 3 May 2017 at 15:07, Liviu Dudau wrote: > > On Wed, May 03, 2017 at 02:45:26PM +0100, Daniel Stone wrote: > >> On 3 May 2017 at 11:34, Liviu Dudau wrote: > >> > You are *really* pushing

Re: [Intel-gfx] [PATCHv3 2/3] drm/prime: Introduce drm_gem_prime_import_platform

On 05/03/2017 12:39 AM, Daniel Vetter wrote: > On Tue, May 02, 2017 at 09:22:13PM +0100, Chris Wilson wrote: >> On Tue, May 02, 2017 at 10:02:07AM -0700, Laura Abbott wrote: >>> /** >>> + * drm_gem_prime_import_platform - alternate implementation of the import >>> callback >>> + * @dev:

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

Hi Daniel, On Wed, May 03, 2017 at 03:07:40PM +0100, Daniel Stone wrote: Hi Brian, On 3 May 2017 at 15:03, Brian Starkey wrote: On Wed, May 03, 2017 at 02:51:18PM +0100, Daniel Stone wrote: formats_offset is the end of the fixed-size element, which is currently

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

On 3 May 2017 at 15:07, Liviu Dudau wrote: > On Wed, May 03, 2017 at 02:45:26PM +0100, Daniel Stone wrote: >> On 3 May 2017 at 11:34, Liviu Dudau wrote: >> > You are *really* pushing your luck by not Cc-ing *any* of the maintainers >> > of >> > the

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

On Wed, May 03, 2017 at 04:06:37PM +0200, Maarten Lankhorst wrote: > Op 03-05-17 om 15:45 schreef Ville Syrjälä: > > On Mon, May 01, 2017 at 03:34:34PM +0200, Maarten Lankhorst wrote: > >> The watermarks it should calculate against are the old optimal watermarks. > >> The currently active crtc

Re: [Intel-gfx] [PATCH RESEND v4 6/6] drm/i915: Set PWM divider to match desired frequency in vbt

On Tue, 18 Apr 2017, Puthikorn Voravootivat wrote: > Read desired PWM frequency from panel vbt and calculate the > value for divider in DPCD address 0x724 and 0x728 to match > that frequency as close as possible. > > Signed-off-by: Puthikorn Voravootivat

Re: [Intel-gfx] [PATCH 5/5] drm/vblank: Lock down vblank->hwmode more

On Wed, May 03, 2017 at 09:26:38AM +0200, Daniel Vetter wrote: > In the previous patch we've implemented hwmode tracking a la i915 for > the vblank timestamp calculations. But that was just the basic > semantics, i915 has some nice sanity checks to make sure we keep > getting this right. Move them

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

Hi Brian, On 3 May 2017 at 15:03, Brian Starkey wrote: > On Wed, May 03, 2017 at 02:51:18PM +0100, Daniel Stone wrote: >> formats_offset is the end of the fixed-size element, which is >> currently aligned to 32 bytes, and practically speaking would always >> have to be

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

On Wed, May 03, 2017 at 02:45:26PM +0100, Daniel Stone wrote: > Hi Liviu, > > On 3 May 2017 at 11:34, Liviu Dudau wrote: > > On Tue, May 02, 2017 at 10:14:26PM -0700, Ben Widawsky wrote: > >> v2: A minor addition from Daniel > > > > You are *really* pushing your luck by not

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

Op 03-05-17 om 15:45 schreef Ville Syrjälä: > On Mon, May 01, 2017 at 03:34:34PM +0200, Maarten Lankhorst wrote: >> The watermarks it should calculate against are the old optimal watermarks. >> The currently active crtc watermarks are pure fiction, and are invalid in >> case of a nonblocking

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

On Wed, May 03, 2017 at 02:51:18PM +0100, Daniel Stone wrote: Hi Brian, On 3 May 2017 at 13:51, Brian Starkey wrote: On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote: + modifiers_size = + sizeof(struct drm_format_modifier) *

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

Hi Brian, On 3 May 2017 at 13:51, Brian Starkey wrote: > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote: >> + modifiers_size = >> + sizeof(struct drm_format_modifier) * >> format_modifier_count; >> + >> + blob_size =

Re: [Intel-gfx] [PATCH v2 00/11] drm/i915: LPE audio runtime PM and multipipe (v2)

On Wed, 03 May 2017 15:39:06 +0200, Ville Syrjälä wrote: > > On Fri, Apr 28, 2017 at 10:41:37AM +0200, Takashi Iwai wrote: > > On Thu, 27 Apr 2017 18:02:19 +0200, > > ville.syrj...@linux.intel.com wrote: > > > > > > From: Ville Syrjälä > > > > > > Okay, here's

Re: [Intel-gfx] [PATCH v2 3/4] drm/i915: Calculate ironlake intermediate watermarks correctly, v2.

On Mon, May 01, 2017 at 03:34:33PM +0200, Maarten Lankhorst wrote: > The watermarks it should calculate against are the old optimal watermarks. > The currently active crtc watermarks are pure fiction, and are invalid in > case of a nonblocking modeset, page flip enabling/disabling planes or any >

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Change get_existing_crtc_state to old state

On Mon, May 01, 2017 at 03:34:32PM +0200, Maarten Lankhorst wrote: > get_existing_crtc_state is currently unused, but the next commit > needs to access the old intel state. Rename this and use this > as convenience wrapper. > > Signed-off-by: Maarten Lankhorst

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915: Calculate vlv/chv intermediate watermarks correctly, v2.

On Mon, May 01, 2017 at 03:34:34PM +0200, Maarten Lankhorst wrote: > The watermarks it should calculate against are the old optimal watermarks. > The currently active crtc watermarks are pure fiction, and are invalid in > case of a nonblocking modeset, page flip enabling/disabling planes or any >

Re: [Intel-gfx] [PATCH 1/3] drm: Plumb modifiers through plane init

Hi Liviu, On 3 May 2017 at 11:34, Liviu Dudau wrote: > On Tue, May 02, 2017 at 10:14:26PM -0700, Ben Widawsky wrote: >> v2: A minor addition from Daniel > > You are *really* pushing your luck by not Cc-ing *any* of the maintainers of > the drivers you touch. You do want

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: Change use get_new_plane_state instead of existing plane state

On Mon, May 01, 2017 at 03:34:31PM +0200, Maarten Lankhorst wrote: > The get_existing macros are deprecated and should be replaced by > get_old/new_state for clarity. > > Signed-off-by: Maarten Lankhorst Reviewed-by: Ville Syrjälä

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v4,1/2] PCI / PM: Add needs_resume flag to avoid suspend complete optimization

On Tue, May 02, 2017 at 07:28:39PM +0300, Imre Deak wrote: > On Tue, May 02, 2017 at 03:10:29PM +, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [v4,1/2] PCI / PM: Add needs_resume flag to > > avoid suspend complete optimization > > URL :

Re: [Intel-gfx] [PATCH v2 00/11] drm/i915: LPE audio runtime PM and multipipe (v2)

On Fri, Apr 28, 2017 at 10:41:37AM +0200, Takashi Iwai wrote: > On Thu, 27 Apr 2017 18:02:19 +0200, > ville.syrj...@linux.intel.com wrote: > > > > From: Ville Syrjälä > > > > Okay, here's the second attempt at getting multiple pipes playing back > > audio on the

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

Hi Ben, On 3 May 2017 at 06:14, Ben Widawsky wrote: > +struct drm_format_modifier_blob { > +#define FORMAT_BLOB_CURRENT 1 > + /* Version of this blob format */ > + u32 version; > + > + /* Flags */ > + u32 flags; > + > + /* Number of fourcc

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote: > Updated blob layout (Rob, Daniel, Kristian, xerpi) > > Cc: Rob Clark > Cc: Daniel Stone > Cc: Kristian H. Kristensen > Signed-off-by: Ben Widawsky

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use engine->context_pin() to report the intel_ring

== Series Details == Series: drm/i915: Use engine->context_pin() to report the intel_ring URL : https://patchwork.freedesktop.org/series/23884/ State : success == Summary == Series 23884v1 drm/i915: Use engine->context_pin() to report the intel_ring

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

Hi, On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote: Updated blob layout (Rob, Daniel, Kristian, xerpi) Cc: Rob Clark Cc: Daniel Stone Cc: Kristian H. Kristensen Signed-off-by: Ben Widawsky ---

[Intel-gfx] [PATCH] drm/i915: Use engine->context_pin() to report the intel_ring

Since unifying ringbuffer/execlist submission to use engine->pin_context, we ensure that the intel_ring is available before we start constructing the request. We can therefore move the assignment of the request->ring to the central i915_gem_request_alloc() and not require it in every

Re: [Intel-gfx] [PATCH RESEND v4 5/6] drm: Add definition for eDP backlight frequency

On Tue, 02 May 2017, Manasi Navare wrote: > On Tue, Apr 18, 2017 at 04:48:23PM -0700, Puthikorn Voravootivat wrote: > > Since this adds definitions in the DRM layer, you need to copy > the dri-de...@lists.freedesktop.org M-L. > >> This patch adds the following

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

Hi Daniel, On Wed, May 03, 2017 at 12:47:18PM +0100, Daniel Stone wrote: Hi Brian, On 3 May 2017 at 12:00, Brian Starkey wrote: Having just caught up on IRC I'm sure I'm far too late for this party, but... Wouldn't this whole thing be a whole lot simpler if

[Intel-gfx] [PATCH i-g-t v3] tests/kms_atomic_allow_modeset: Add DRM_MODE_ATOMIC_ALLOW_MODESET test

When doing a full atomic modeset, kernel should fail if the flag DRM_MODE_ATOMIC_ALLOW_MODESET is not set. Let's add this test as part of Intel-GPU-Tools. The test procedure is the following: - Try to do atomic commit without DRM_MODE_ATOMIC_ALLOW_MODESET flag. Kernel should reject this

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915: Make ptr_unpack_bits() more function-like

== Series Details == Series: series starting with [1/9] drm/i915: Make ptr_unpack_bits() more function-like URL : https://patchwork.freedesktop.org/series/23881/ State : success == Summary == Series 23881v1 Series without cover letter

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Avoid the branch in computing intel_ring_space()

On Wed, May 03, 2017 at 01:02:40PM +0100, Chris Wilson wrote: > On Wed, May 03, 2017 at 02:53:43PM +0300, Mika Kuoppala wrote: > > > void intel_ring_update_space(struct intel_ring *ring) > > > @@ -1669,12 +1673,9 @@ static int wait_for_space(struct > > > drm_i915_gem_request *req, int bytes) > >

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_atomic_abi: Test event ABI corner cases

Op 27-04-17 om 14:42 schreef Mika Kahola: > Atomic has a few special cases around async commits and event generation > that we need to test. This patch addresses these two tests > > - kernel rejects events on a disabled pipe > - events on a pipe that is getting enabled/disabled > > For: VIZ-6954 >

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Avoid the branch in computing intel_ring_space()

On Wed, May 03, 2017 at 02:53:43PM +0300, Mika Kuoppala wrote: > Chris Wilson writes: > > > Exploit the power-of-two ring size to compute the space across the > > wraparound using a mask rather than a if. Convert to unsigned integers > > so the operation is well

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Avoid the branch in computing intel_ring_space()

Chris Wilson writes: > Exploit the power-of-two ring size to compute the space across the > wraparound using a mask rather than a if. Convert to unsigned integers > so the operation is well defined. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=99671 >

Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob

Hi Brian, On 3 May 2017 at 12:00, Brian Starkey wrote: > Having just caught up on IRC I'm sure I'm far too late for this party, > but... > > Wouldn't this whole thing be a whole lot simpler if "IN_FORMATS" > stored "pointers" to separate blobs for the format and modifier

[Intel-gfx] [PATCH 7/9] drm/i915/execlists: Reduce lock context between schedule/submit_request

If we do not require to perform priority bumping, and we haven't yet submitted the request, we can update its priority in situ and skip acquiring the engine locks -- thus avoiding any contention between us and submit/execute. Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH 1/9] drm/i915: Make ptr_unpack_bits() more function-like

ptr_unpack_bits() is a function-like macro, as such it is meant to be replaceable by a function. In this case, we should be passing in the out-param as a pointer. Bizarrely this does affect code generation: function old new delta i915_gem_object_pin_map

[Intel-gfx] [PATCH 5/9] drm/i915: Use a define for the default priority [0]

Explicitly assign the default priority, and give it a name (macro). Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/i915_gem_request.h | 1 + 2 files changed, 2 insertions(+) diff --git

[Intel-gfx] [PATCH 4/9] drm/i915: Don't mark an execlists context-switch when idle

If we *know* that the engine is idle, i.e. we have not more contexts in flight, we can skip any spurious CSB idle interrupts. These spurious interrupts seem to arrive long after we assert that the engines are completely idle, triggering later assertions: [ 178.896646] intel_engine_is_idle(bcs):

[Intel-gfx] [PATCH 9/9] drm/i915: Don't force serialisation on marking up execlists irq posted

Since we coordinate with the execlists tasklet using a locked schedule operation that ensures that after we set the engine->irq_posted we always have an invocation of the tasklet, we do not need to use a locked operation to set the engine->irq_posted itself. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 8/9] drm/i915: Stop inlining the execlists IRQ handler

As the handler is now quite complex, involving a few atomics, the cost of the function preamble is negligible in comparison and so we should leave the function out-of-line for better I$. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_irq.c | 2 +- 1 file

[Intel-gfx] [PATCH 3/9] drm/i915/execlists: Pack the count into the low bits of the port.request

add/remove: 1/1 grow/shrink: 5/4 up/down: 391/-578 (-187) function old new delta execlists_submit_ports 262 471+209 port_assign.isra - 136+136 capture

[Intel-gfx] [PATCH 6/9] drm/i915: Split execlist priority queue into rbtree + linked list

All the requests at the same priority are executed in FIFO order. They do not need to be stored in the rbtree themselves, as they are a simple list within a level. If we move the requests at one priority into a list, we can then reduce the rbtree to the set of priorities. This should keep the

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