[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: stolen_reserved_base is also dma_addr_t

== Series Details == Series: series starting with [1/2] drm/i915: stolen_reserved_base is also dma_addr_t URL : https://patchwork.freedesktop.org/series/30923/ State : failure == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252

[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce DVFS.

== Series Details == Series: Introduce DVFS. URL : https://patchwork.freedesktop.org/series/30922/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test kms_flip: Subgroup flip-vs-expired-vblank:

[Intel-gfx] ✗ Fi.CI.IGT: warning for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev2)

== Series Details == Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev2) URL : https://patchwork.freedesktop.org/series/30860/ State : warning == Summary == Test gem_eio: Subgroup throttle: pass -> DMESG-WARN (shard-hsw)

Re: [Intel-gfx] [PATCH 0/6] Adding NV12 support

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Tuesday, September 26, 2017 5:17 PM > To: Kristian Høgsberg > Cc: Daniel Vetter ; Srinivas, Vidya > ;

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [RFC,1/2] drm/i915/uc: Move uC related types into dedicated header

== Series Details == Series: series starting with [RFC,1/2] drm/i915/uc: Move uC related types into dedicated header URL : https://patchwork.freedesktop.org/series/30918/ State : failure == Summary == Test kms_flip: Subgroup flip-vs-expired-vblank: fail -> PASS

Re: [Intel-gfx] [PATCH] drm/i915/cnl: allow HDMI 2.0 clock rates

Please ignore this patch. Freq is wrong... shoudl be 594000 as GLK but also other parts are missing. Causes blank screen on CNL with HDMI 2.0 panel. On Tue, Sep 26, 2017 at 3:13 PM, Rodrigo Vivi wrote: > From: Shashank Sharma > > From GLK

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/selftests: Replace wmb() with i915_gem_chipset_flush()

== Series Details == Series: drm/i915/selftests: Replace wmb() with i915_gem_chipset_flush() URL : https://patchwork.freedesktop.org/series/30916/ State : warning == Summary == Test kms_frontbuffer_tracking: Subgroup fbc-1p-offscren-pri-indfb-draw-render: pass ->

[Intel-gfx] [maintainer-tools PATCH] qf: Handle unused patches on sub-directories.

Most of internal patches are nowadays organized in quilt subdirectories, but qf was never updated to check for unused patches there. Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi --- qf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests (rev3)

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests (rev3) URL : https://patchwork.freedesktop.org/series/30895/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL

[Intel-gfx] ✗ Fi.CI.BAT: warning for igt/gem_workarounds: Read the workaround registers from the active context

== Series Details == Series: igt/gem_workarounds: Read the workaround registers from the active context URL : https://patchwork.freedesktop.org/series/30930/ State : warning == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: allow HDMI 2.0 clock rates

== Series Details == Series: drm/i915/cnl: allow HDMI 2.0 clock rates URL : https://patchwork.freedesktop.org/series/30929/ State : success == Summary == Series 30929v1 drm/i915/cnl: allow HDMI 2.0 clock rates https://patchwork.freedesktop.org/api/1.0/series/30929/revisions/1/mbox/ Test

[Intel-gfx] ✓ Fi.CI.IGT: success for GEM/GuC Suspend/Resume/Reset fixes and restructuring (rev2)

== Series Details == Series: GEM/GuC Suspend/Resume/Reset fixes and restructuring (rev2) URL : https://patchwork.freedesktop.org/series/30802/ State : success == Summary == shard-hswtotal:2429 pass:1328 dwarn:5 dfail:0 fail:13 skip:1083 time:9867s == Logs == For more details

[Intel-gfx] [PATCH igt] igt/gem_workarounds: Read the workaround registers from the active context

The workarounds are only valid whilst the GPU is active. To be sure we are reading the registers in the right state, issue the reads from the GPU. Signed-off-by: Chris Wilson --- tests/gem_workarounds.c | 138 +++- 1 file

[Intel-gfx] [PATCH] drm/i915/cnl: allow HDMI 2.0 clock rates

From: Shashank Sharma From GLK onwards, Intel platforms contain native HDMI 2.0 controller, which is capable of driving clocks upto 600Mhz. This patch updates the max tmds clock limit for the same. V2: check for gen 10 and above (Ville) align the gen10 condition

Re: [Intel-gfx] [PATCH] drm/i915: Avoid using dev_priv->info.gen directly.

On Tue, Sep 26, 2017 at 09:21:43PM +, Paulo Zanoni wrote: > Em Ter, 2017-09-26 às 14:13 -0700, Rodrigo Vivi escreveu: > > Let's stop this usage before it spreads so much. > > > > 1. This check is not part of usual searches happening when adding > > new platform. > > 2. There is already a

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid using dev_priv->info.gen directly.

== Series Details == Series: drm/i915: Avoid using dev_priv->info.gen directly. URL : https://patchwork.freedesktop.org/series/30926/ State : success == Summary == Series 30926v1 drm/i915: Avoid using dev_priv->info.gen directly.

Re: [Intel-gfx] [PATCH 02/22] drm/i915: introduce simple gemfs

On Tue, Sep 26, 2017 at 04:21:47PM +0300, Joonas Lahtinen wrote: > On Tue, 2017-09-26 at 09:52 +0200, Greg Kroah-Hartman wrote: > > On Mon, Sep 25, 2017 at 07:47:17PM +0100, Matthew Auld wrote: > > > Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so > > > moves us away from

Re: [Intel-gfx] [PATCH] drm/i915: Avoid using dev_priv->info.gen directly.

On Tue, Sep 26, 2017 at 02:13:46PM -0700, Rodrigo Vivi wrote: > Let's stop this usage before it spreads so much. > > 1. This check is not part of usual searches happening when adding > new platform. > 2. There is already a duplication here with INTEL_INFO(dev_priv)->gen > and INTEL_GEN(dev_priv).

Re: [Intel-gfx] [PATCH] drm/i915: Avoid using dev_priv->info.gen directly.

Em Ter, 2017-09-26 às 14:13 -0700, Rodrigo Vivi escreveu: > Let's stop this usage before it spreads so much. > > 1. This check is not part of usual searches happening when adding > new platform. > 2. There is already a duplication here with INTEL_INFO(dev_priv)->gen > and INTEL_GEN(dev_priv). >

[Intel-gfx] [PATCH] drm/i915: Avoid using dev_priv->info.gen directly.

Let's stop this usage before it spreads so much. 1. This check is not part of usual searches happening when adding new platform. 2. There is already a duplication here with INTEL_INFO(dev_priv)->gen and INTEL_GEN(dev_priv). So let's please avoid yet another way. Fixes: b22ca995ba1c ("drm/i915:

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

On Tue, Sep 26, 2017 at 1:37 PM, Puthikorn Voravootivat wrote: > > > On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat > wrote: >> >> >> >> On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter wrote: >>> >>> On Thu, Sep 21, 2017 at

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v8,1/8] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

== Series Details == Series: series starting with [v8,1/8] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors URL : https://patchwork.freedesktop.org/series/30905/ State : success == Summary == Test kms_frontbuffer_tracking: Subgroup

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

On Tue, Sep 26, 2017 at 10:37 AM, Puthikorn Voravootivat < put...@chromium.org> wrote: > > > On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter wrote: > >> On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote: >> > On Wed, Sep 20, 2017 at 02:32:34PM +, vathsala nagaraju

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

== Series Details == Series: drm/i915/cnl: Allow 2 pixel per clock on Cannonlake. URL : https://patchwork.freedesktop.org/series/30924/ State : success == Summary == Series 30924v1 drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

Re: [Intel-gfx] [PATCH 2/2] drm/i915: use size_t instead of u32 for stolen memory size variables

Quoting Paulo Zanoni (2017-09-26 20:29:08) > Stolen memory pointers are dma_addr_t, which means they can be 64 bit > things. By using u32 we leave room for bugs in case we ever get huge > amounts of stolen memory. By using size_t we don't risk running into > those problems. > > Cc: Chris Wilson

Re: [Intel-gfx] [PATCH 2/2] drm/i915: use size_t instead of u32 for stolen memory size variables

Quoting Paulo Zanoni (2017-09-26 20:29:08) > Stolen memory pointers are dma_addr_t, which means they can be 64 bit > things. By using u32 we leave room for bugs in case we ever get huge > amounts of stolen memory. By using size_t we don't risk running into > those problems. What platform? -Chris

Re: [Intel-gfx] [PATCH 1/2] drm/i915: stolen_reserved_base is also dma_addr_t

Quoting Paulo Zanoni (2017-09-26 20:29:07) > The chunk added by this patch was missed by these commits: > * 920bcd1820a6 ("drm/i915: make i915_stolen_to_physical() return phys_addr_t") > * c88473878d47 ("drm/i915: Treat stolen memory as DMA addresses") > > The stolen_reserved_base variable

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for lib: Ask the kernel to quiescent the GPU

Quoting Patchwork (2017-09-26 19:13:26) > == Series Details == > > Series: lib: Ask the kernel to quiescent the GPU > URL : https://patchwork.freedesktop.org/series/30890/ > State : failure > > == Summary == > > IGT patchset tested on top of latest successful build >

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Fix SSEU Device Status.

On Fri, Sep 22, 2017 at 06:32:04PM +, Rodrigo Vivi wrote: > On Fri, Sep 22, 2017 at 04:44:38PM +, Oscar Mateo wrote: > > > > > > On 09/22/2017 06:15 AM, Rodrigo Vivi wrote: > > > CNL adds an extra register for slice/subslice information. > > > Although no SKU is planed with an extra

Re: [Intel-gfx] [PATCH 7/8] drm/i915/pmu: Wire up engine busy stats to PMU

Quoting Tvrtko Ursulin (2017-09-26 13:32:25) > > On 25/09/2017 18:48, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2017-09-25 16:15:42) > >> From: Tvrtko Ursulin > >> > >> We can use engine busy stats instead of the MMIO sampling timer > >> for better efficiency. >

Re: [Intel-gfx] [PATCH 7/8] drm/i915/pmu: Wire up engine busy stats to PMU

Quoting Rogozhkin, Dmitry V (2017-09-26 19:46:48) > On Tue, 2017-09-26 at 13:32 +0100, Tvrtko Ursulin wrote: > > On 25/09/2017 18:48, Chris Wilson wrote: > > > Quoting Tvrtko Ursulin (2017-09-25 16:15:42) > > >> From: Tvrtko Ursulin > > >> > > >> We can use engine busy

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: stolen_reserved_base is also dma_addr_t

== Series Details == Series: series starting with [1/2] drm/i915: stolen_reserved_base is also dma_addr_t URL : https://patchwork.freedesktop.org/series/30923/ State : success == Summary == Series 30923v1 series starting with [1/2] drm/i915: stolen_reserved_base is also dma_addr_t

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

On Tue, Sep 26, 2017 at 12:43 PM, Rodrigo Vivi wrote: > This is heavily based on a initial patch provided by Ville > plus all changes provided later by Ander. > > As Geminilake, Cannonlake also supports 2 pixels per clock. > > Different from Geminilake we are not

[Intel-gfx] [PATCH] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

This is heavily based on a initial patch provided by Ville plus all changes provided later by Ander. As Geminilake, Cannonlake also supports 2 pixels per clock. Different from Geminilake we are not implementing the 99% Wa. But we can revisit that decision later if we find out any limitation on

[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce DVFS.

== Series Details == Series: Introduce DVFS. URL : https://patchwork.freedesktop.org/series/30922/ State : success == Summary == Series 30922v1 Introduce DVFS. https://patchwork.freedesktop.org/api/1.0/series/30922/revisions/1/mbox/ Test drv_module_reload: Subgroup

[Intel-gfx] [PATCH 2/2] drm/i915: use size_t instead of u32 for stolen memory size variables

Stolen memory pointers are dma_addr_t, which means they can be 64 bit things. By using u32 we leave room for bugs in case we ever get huge amounts of stolen memory. By using size_t we don't risk running into those problems. Cc: Chris Wilson Signed-off-by: Paulo Zanoni

[Intel-gfx] [PATCH 1/2] drm/i915: stolen_reserved_base is also dma_addr_t

The chunk added by this patch was missed by these commits: * 920bcd1820a6 ("drm/i915: make i915_stolen_to_physical() return phys_addr_t") * c88473878d47 ("drm/i915: Treat stolen memory as DMA addresses") The stolen_reserved_base variable contains a memory address for stolen memory and our code

[Intel-gfx] [PATCH 0/5] Introduce DVFS.

This Display Voltage and Frequency Switching Sequence exist for a while, but now on CNL it got a separated doc in spec and more attention since it is required to be called for more places. So this series from Paulo and mostly from Mika addresses the changes required specially for CNL. Last patch

[Intel-gfx] [PATCH 5/5] drm/i915: Extend DVFS function back to Skylake.

Although SKL Spec doesn't explicit call this sequence as DVFS, that is exactly what it is. So let's remove a bit of code duplication and re-use CNL functions. No functional change. Cc: Ville Syrjälä Cc: Paulo Zanoni Signed-off-by:

[Intel-gfx] [PATCH 1/5] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change

From: Paulo Zanoni These functions even have their own page in our spec, so extract them from cnl_set_cdclk(). Cc: Ville Syrjälä Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH 2/5] drm/i915/cnl: Expose DVFS change functions

From: "Kahola, Mika" DVFS computation needs cnl_dvfs_{pre,post}_change() functions to be exposed. These functions will be used when computing DVFS levels in intel_dpll_mgr.c Cc: Ville Syrjälä Signed-off-by: Kahola, Mika

[Intel-gfx] [PATCH 3/5] drm/i915/cnl: DVFS for PLL enabling

From: "Kahola, Mika" Display Voltage and Frequency Switching (DVFS) is used to adjust the display voltage to match the display clock frequencies. If voltage is set too low, it will break functionality. If voltage is set too high, it will waste power. Voltage level is

[Intel-gfx] [PATCH 4/5] drm/i915/cnl: DVFS for PLL disabling

From: "Kahola, Mika" Display Voltage and Frequency Switching (DVFS) is used to adjust the display voltage to match the display clock frequencies. To save power the voltage is set to minimum when disabling PLL. The sequence before frequency change is the following and it

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests URL : https://patchwork.freedesktop.org/series/30895/ State : success == Summary == Test perf: Subgroup blocking: fail -> PASS (shard-hsw)

[Intel-gfx] ✗ Fi.CI.BAT: failure for lib/igt_kms: Convert properties to be more atomic-like.

== Series Details == Series: lib/igt_kms: Convert properties to be more atomic-like. URL : https://patchwork.freedesktop.org/series/30903/ State : failure == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3 igt/gem_exec_schedule: Ignore

Re: [Intel-gfx] [PATCH 7/8] drm/i915/pmu: Wire up engine busy stats to PMU

On Tue, 2017-09-26 at 13:32 +0100, Tvrtko Ursulin wrote: > On 25/09/2017 18:48, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2017-09-25 16:15:42) > >> From: Tvrtko Ursulin > >> > >> We can use engine busy stats instead of the MMIO sampling timer > >> for better

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev2)

== Series Details == Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev2) URL : https://patchwork.freedesktop.org/series/30860/ State : success == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3

Re: [Intel-gfx] [PATCH i-g-t v5 03/11] tests/perf: update max buffer size for reading reports

On 31 August 2017 at 11:35, Lionel Landwerlin wrote: > Signed-off-by: Lionel Landwerlin Maybe add the why to the commit message? Reviewed-by: Matthew Auld ___

[Intel-gfx] ✗ Fi.CI.BAT: failure for lib: Ask the kernel to quiescent the GPU

== Series Details == Series: lib: Ask the kernel to quiescent the GPU URL : https://patchwork.freedesktop.org/series/30890/ State : failure == Summary == IGT patchset tested on top of latest successful build 2885b10f99b4beeb046e75af8b8488c229f629d3 igt/gem_exec_schedule: Ignore set-priority

Re: [Intel-gfx] [PATCH i-g-t v5 11/11] tests/perf: add support for Coffeelake

On 31 August 2017 at 11:35, Lionel Landwerlin wrote: > Using the same timestamp frequency as Skylake/Kabylake. > > Signed-off-by: Lionel Landwerlin > --- > tests/perf.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/dp: Add defines for latency in sink

== Series Details == Series: series starting with [1/2] drm/dp: Add defines for latency in sink URL : https://patchwork.freedesktop.org/series/30893/ State : warning == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test

Re: [Intel-gfx] [PATCH i-g-t v5 09/11] tests/perf: estimate number of blocking/polling based on time spent

On 31 August 2017 at 11:35, Lionel Landwerlin wrote: > Blocking & polling tests define an amount of time to spend in the test > and then estimate the number of syscalls that should successfully > return. The problem is that while running the test we might spend >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] drm/i915/uc: Move uC related types into dedicated header

== Series Details == Series: series starting with [RFC,1/2] drm/i915/uc: Move uC related types into dedicated header URL : https://patchwork.freedesktop.org/series/30918/ State : success == Summary == Series 30918v1 series starting with [RFC,1/2] drm/i915/uc: Move uC related types into

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

On Mon, Sep 25, 2017 at 10:11 PM, Daniel Vetter wrote: > On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote: > > On Wed, Sep 20, 2017 at 02:32:34PM +, vathsala nagaraju wrote: > > > Add defines for dpcd register 2009 (synchronization latency > > > in sink). > > > >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use memset64() to prefill the GTT page

== Series Details == Series: drm/i915: Use memset64() to prefill the GTT page URL : https://patchwork.freedesktop.org/series/30892/ State : success == Summary == Test perf: Subgroup polling: pass -> FAIL (shard-hsw) fdo#102252 Test kms_setmode:

Re: [Intel-gfx] [PATCH] dim: Accept author x signed-off based on email.

On Tue, Sep 26, 2017 at 01:24:35PM +, Jani Nikula wrote: > On Tue, 26 Sep 2017, Daniel Vetter wrote: > > On Thu, Sep 21, 2017 at 06:27:28AM -0700, Rodrigo Vivi wrote: > >> On Thu, Sep 21, 2017 at 11:12:52AM +, Jani Nikula wrote: > >> > On Wed, 20 Sep 2017, Rodrigo Vivi

[Intel-gfx] [RFC 1/2] drm/i915/uc: Move uC related types into dedicated header

In old header structure we were mixing type definitions and declarations that prevent us from exposing some functions as inline. Lets try to fix that. Suggested-by: Chris Wilson Signed-off-by: Michal Wajdeczko Cc: Chris Wilson

[Intel-gfx] [RFC 2/2] drm/i915: Make intel_guc_wopcm_size() inline

It's small and we are using this function sporadically. Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/intel_guc_loader.c | 11 --- drivers/gpu/drm/i915/intel_uc.c | 4 ++-- drivers/gpu/drm/i915/intel_uc.h | 13 - 3

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Replace wmb() with i915_gem_chipset_flush()

== Series Details == Series: drm/i915/selftests: Replace wmb() with i915_gem_chipset_flush() URL : https://patchwork.freedesktop.org/series/30916/ State : success == Summary == Series 30916v1 drm/i915/selftests: Replace wmb() with i915_gem_chipset_flush()

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests (rev3)

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests (rev3) URL : https://patchwork.freedesktop.org/series/30895/ State : success == Summary == Series 30895v3 series starting with [1/2] drm/i915/execlists: Notify context-out for

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Don't mix inline functions with declarations

== Series Details == Series: drm/i915: Don't mix inline functions with declarations URL : https://patchwork.freedesktop.org/series/30908/ State : warning == Summary == Series 30908v1 drm/i915: Don't mix inline functions with declarations

[Intel-gfx] [PATCH] drm/i915/selftests: Replace wmb() with i915_gem_chipset_flush()

Currently, we are being fairly lazy and only using a wmb() following an update to an active batch. Previously, we have found that to be insufficient to ensure that a write from the CPU reaches memory in a timely fashion, and in some caches we may need to flush a chipset cache. To that end, we have

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp: Avoid needless delay while link training

== Series Details == Series: drm/dp: Avoid needless delay while link training URL : https://patchwork.freedesktop.org/series/30891/ State : success == Summary == shard-hswtotal:2429 pass:1325 dwarn:4 dfail:0 fail:17 skip:1083 time:9960s == Logs == For more details see:

Re: [Intel-gfx] [PATCH v8 2/8] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

On 9/26/2017 8:18 PM, Chris Wilson wrote: Subject includes the word "fences". That was quite surprising as it doesn't involve either dma, sw or guc fences; or the fence registers. -Chris This was related to fence registers whose state is updated in i915_gem_restore_fences. With this patch I

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Set our shrinker->batch to 4096 (~16MiB)

Quoting Joonas Lahtinen (2017-09-20 14:28:40) > On Wed, 2017-08-16 at 14:55 +0100, Chris Wilson wrote: > > Quoting Joonas Lahtinen (2017-08-16 14:39:00) > > > On Sat, 2017-08-12 at 12:51 +0100, Chris Wilson wrote: > > > > Prefer to defer activating our GEM shrinker until we have a few > > > >

[Intel-gfx] [PATCH v2] drm/i915/execlists: Distinguish the incomplete context notifies

Let the listener know that the context we just scheduled out was not complete, and will be scheduled back in at a later point. v2: Handle CONTEXT_STATUS_PREEMPTED in gvt by aliasing it to CONTEXT_STATUS_OUT for the moment, gvt can expand upon the difference later. Signed-off-by: Chris Wilson

[Intel-gfx] ✓ Fi.CI.BAT: success for GEM/GuC Suspend/Resume/Reset fixes and restructuring (rev2)

== Series Details == Series: GEM/GuC Suspend/Resume/Reset fixes and restructuring (rev2) URL : https://patchwork.freedesktop.org/series/30802/ State : success == Summary == Series 30802v2 GEM/GuC Suspend/Resume/Reset fixes and restructuring

Re: [Intel-gfx] [PATCH v8 2/8] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

Subject includes the word "fences". That was quite surprising as it doesn't involve either dma, sw or guc fences; or the fence registers. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org

Re: [Intel-gfx] [PATCH] drm/i915: Don't mix inline functions with declarations

Quoting Michal Wajdeczko (2017-09-26 15:37:23) > We group function forward declarations by file. There is no > reason to mix these declarations with our unline functions. Can of worms, can of worms. Our headers are a mess because we mix types and inlines, and so we end up with code being placed

Re: [Intel-gfx] [PATCH v8 2/8] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

Quoting Sagar Arun Kamble (2017-09-26 15:24:15) > > > On 9/26/2017 7:12 PM, Chris Wilson wrote: > > Quoting Sagar Arun Kamble (2017-09-26 14:24:39) > >> diff --git a/drivers/gpu/drm/i915/i915_gem.c > >> b/drivers/gpu/drm/i915/i915_gem.c > >> index dbe181b..5dcd8c0 100644 > >> ---

[Intel-gfx] [PATCH] drm/i915: Don't mix inline functions with declarations

We group function forward declarations by file. There is no reason to mix these declarations with our unline functions. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_uc.h | 36

Re: [Intel-gfx] [PATCH v8 2/8] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

On 9/26/2017 7:12 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2017-09-26 14:24:39) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index dbe181b..5dcd8c0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2022,11

Re: [Intel-gfx] [PATCH v8 3/8] drm/i915: Create uC runtime and system suspend/resume helpers

On 9/26/2017 7:13 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2017-09-26 14:24:40) @@ -2077,7 +2079,7 @@ int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) reg->dirty = true; } - return 0; + return ret; OI! These are written as

Re: [Intel-gfx] [PATCH v8 4/8] drm/i915/guc: Introduce intel_guc_sanitize

On 9/26/2017 7:16 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2017-09-26 14:24:41) Currently GPU is reset at the end of suspend via i915_gem_sanitize. On resume, GuC will not be loaded until intel_uc_init_hw happens during GEM resume flow but action to exit sleep wll be send to GuC

Re: [Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Ignore set-priority failures on old kernels

Quoting Michał Winiarski (2017-09-26 15:11:15) > On Mon, Sep 25, 2017 at 09:21:15PM +0100, Chris Wilson wrote: > > When plugging the device, we need to submit batches at highest priority > > so that they cannot be gazumped by the queued requests. On older kernels > > that do not support the user

Re: [Intel-gfx] [PATCH v8 7/8] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset

On 9/26/2017 7:22 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2017-09-26 14:24:44) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index d710f0d..aec3f6b 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -562,6 +562,14

Re: [Intel-gfx] [PATCH v8 6/8] drm/i915/guc: Update GuC suspend functionality in intel_uc_suspend

On 9/26/2017 7:27 PM, Michał Winiarski wrote: On Tue, Sep 26, 2017 at 02:49:48PM +0100, Chris Wilson wrote: Quoting Sagar Arun Kamble (2017-09-26 14:24:43) With this patch we disable GuC submission in i915_drm_suspend path. This will destroy the client which will be setup back again. We also

Re: [Intel-gfx] [PATCH igt] igt/gem_exec_schedule: Ignore set-priority failures on old kernels

On Mon, Sep 25, 2017 at 09:21:15PM +0100, Chris Wilson wrote: > When plugging the device, we need to submit batches at highest priority > so that they cannot be gazumped by the queued requests. On older kernels > that do not support the user changing context priority, all contexts > therefore have

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v8,1/8] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

== Series Details == Series: series starting with [v8,1/8] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors URL : https://patchwork.freedesktop.org/series/30905/ State : success == Summary == Series 30905v1 series starting with [v8,1/8] drm/i915: Create GEM

Re: [Intel-gfx] [PATCH v8 6/8] drm/i915/guc: Update GuC suspend functionality in intel_uc_suspend

On Tue, Sep 26, 2017 at 02:49:48PM +0100, Chris Wilson wrote: > Quoting Sagar Arun Kamble (2017-09-26 14:24:43) > > With this patch we disable GuC submission in i915_drm_suspend path. > > This will destroy the client which will be setup back again. We also > > reuse the complete sanitization done

Re: [Intel-gfx] [PATCH v8 7/8] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset

Quoting Sagar Arun Kamble (2017-09-26 14:24:44) > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index d710f0d..aec3f6b 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -562,6 +562,14 @@ int intel_uc_resume(struct

Re: [Intel-gfx] [PATCH v8 6/8] drm/i915/guc: Update GuC suspend functionality in intel_uc_suspend

Quoting Sagar Arun Kamble (2017-09-26 14:24:43) > With this patch we disable GuC submission in i915_drm_suspend path. > This will destroy the client which will be setup back again. We also > reuse the complete sanitization done via intel_uc_runtime_suspend in > this path. Post i915_drm_resume,

Re: [Intel-gfx] [PATCH v8 4/8] drm/i915/guc: Introduce intel_guc_sanitize

Quoting Sagar Arun Kamble (2017-09-26 14:24:41) > Currently GPU is reset at the end of suspend via i915_gem_sanitize. > On resume, GuC will not be loaded until intel_uc_init_hw happens > during GEM resume flow but action to exit sleep wll be send to GuC > considering the FW load status. To make

Re: [Intel-gfx] [PATCH v8 3/8] drm/i915: Create uC runtime and system suspend/resume helpers

Quoting Sagar Arun Kamble (2017-09-26 14:24:40) > @@ -2077,7 +2079,7 @@ int i915_gem_runtime_suspend(struct drm_i915_private > *dev_priv) > reg->dirty = true; > } > > - return 0; > + return ret; OI! These are written as return 0 because you are very much not

Re: [Intel-gfx] [PATCH v8 2/8] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

Quoting Sagar Arun Kamble (2017-09-26 14:24:39) > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index dbe181b..5dcd8c0 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -2022,11 +2022,22 @@ int i915_gem_fault(struct

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Try to recover from a wedged GPU during reset tests

Chris Wilson writes: > Quoting Mika Kuoppala (2017-09-26 13:48:17) >> Chris Wilson writes: >> >> > If we see the seqno stop progressing, we abandon the test for fear that >> > the GPU died following the reset. However, during test teardown we

Re: [Intel-gfx] [PATCH v8 1/8] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

Quoting Sagar Arun Kamble (2017-09-26 14:24:38) > drivers/gpu/drm/i915/i915_drv.c | 34 -- > drivers/gpu/drm/i915/i915_drv.h | 5 +++-- > drivers/gpu/drm/i915/i915_gem.c | 20 ++-- > 3 files changed, 41 insertions(+), 18 deletions(-) > > diff

[Intel-gfx] [PATCH v9 2/8] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

This patch moves GuC suspend/resume handlers to corresponding GEM handlers and orders them properly in the runtime and system suspend/resume flows. It also adds documentation for GEM suspend/resume handlers. i915_gem_restore_fences is GEM resumption task hence it is moved to i915_gem_resume from

[Intel-gfx] [PATCH v9 6/8] drm/i915/guc: Update GuC suspend functionality in intel_uc_suspend

With this patch we disable GuC submission in i915_drm_suspend path. This will destroy the client which will be setup back again. We also reuse the complete sanitization done via intel_uc_runtime_suspend in this path. Post i915_drm_resume, this state is recreated by intel_uc_init_hw hence we need

[Intel-gfx] [PATCH v9 7/8] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset

Before i915 reset, we need to disable GuC submission and suspend GuC operations as it is recreated during intel_uc_init_hw. We can't reuse the intel_uc_suspend functionality as reset path already holds struct_mutex. v2: Rebase w.r.t removal of GuC code restructuring. Updated reset_prepare

[Intel-gfx] [PATCH v9 4/8] drm/i915/guc: Introduce intel_guc_sanitize

Currently GPU is reset at the end of suspend via i915_gem_sanitize. On resume, GuC will not be loaded until intel_uc_init_hw happens during GEM resume flow but action to exit sleep wll be send to GuC considering the FW load status. To make sure we don't invoke that action update GuC FW load status

[Intel-gfx] [PATCH v9 5/8] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume

Apart from configuring interrupts, we need to update the ggtt invalidate interface and GuC communication on suspend/resume. This functionality can be reused for other suspend and reset paths. v2: Rebase w.r.t removal of GuC code restructuring. v3: Removed GuC specific helpers as tasks other than

[Intel-gfx] [PATCH v9 8/8] drm/i915/guc: Fix GuC cleanup in unload path

We ensure that GuC is completely suspended and client is destroyed in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw should just take care of cleanup, hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly we also updated as

[Intel-gfx] [PATCH v9 3/8] drm/i915: Create uC runtime and system suspend/resume helpers

Prepared generic helpers intel_uc_suspend, intel_uc_resume, intel_uc_runtime_suspend, intel_uc_runtime_resume. These are called from respective GEM functions. v2: Rebase w.r.t removal of GuC code restructuring. v3: Calling intel_uc_resume from i915_gem_resume post resuming i915 gem setup. This

[Intel-gfx] [PATCH v9 1/8] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

Prepared helper i915_gem_runtime_resume to recreate gem setup. Returning status from i915_gem_runtime_suspend and i915_gem_resume. This will be placeholder for handling any errors from uC suspend/resume in upcoming patches. Restructured the suspend/resume routines w.r.t setup creation and rollback

[Intel-gfx] [PATCH v9 0/8] GEM/GuC Suspend/Resume/Reset fixes and restructuring

Fixed patch 1 based on review inputs from Michal Winiarski. Rebased all patches. Updated ordering of cc, s-o-b, r-b tags for all patches. Sagar Arun Kamble (8): drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors drm/i915: Update GEM suspend/resume flows

Re: [Intel-gfx] [PATCH v8 1/8] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

And I have forgot to amend the ordering of tags cc, s-o-b etc. Sorry for the same. On 9/26/2017 6:54 PM, Sagar Arun Kamble wrote: Prepared helper i915_gem_runtime_resume to recreate gem setup. Returning status from i915_gem_runtime_suspend and i915_gem_resume. This will be placeholder for

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests

== Series Details == Series: series starting with [1/2] drm/i915/execlists: Notify context-out for lost requests URL : https://patchwork.freedesktop.org/series/30895/ State : success == Summary == Series 30895v1 series starting with [1/2] drm/i915/execlists: Notify context-out for lost

Re: [Intel-gfx] [PATCH] dim: Accept author x signed-off based on email.

On Tue, 26 Sep 2017, Daniel Vetter wrote: > On Thu, Sep 21, 2017 at 06:27:28AM -0700, Rodrigo Vivi wrote: >> On Thu, Sep 21, 2017 at 11:12:52AM +, Jani Nikula wrote: >> > On Wed, 20 Sep 2017, Rodrigo Vivi wrote: >> > > It seems Patchwork or SMTP

Re: [Intel-gfx] [PATCH 02/22] drm/i915: introduce simple gemfs

On Tue, 2017-09-26 at 09:52 +0200, Greg Kroah-Hartman wrote: > On Mon, Sep 25, 2017 at 07:47:17PM +0100, Matthew Auld wrote: > > Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so > > moves us away from the shmemfs shm_mnt, and gives us the much needed > > flexibility to do

  1   2   >