[Intel-gfx] [drm-intel:for-linux-next 18/27] drivers/gpu/drm/i915/i915_gem_gtt.c:1087: warning: 'iter' is used uninitialized in this function

tree: git://anongit.freedesktop.org/drm-intel for-linux-next head: a883241c3922000b21b58b5740c55badfe09940f commit: 0a03852e049af91da9ae70326c44bb5d9b0d377a [18/27] drm/i915: support 2M pages for the 48b PPGTT config: x86_64-randconfig-a0-10072329 (attached as .config) compiler: gcc-4.4

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Split uncore init into vfunc setup and mmio setup

Quoting Michal Wajdeczko (2017-10-07 12:14:30) > On Sat, 07 Oct 2017 10:56:58 +0200, Chris Wilson > > +void intel_uncore_init_mmio(struct drm_i915_private *dev_priv) > > +{ > > + i915_check_vgpu(dev_priv); > > + > > + intel_uncore_edram_detect(dev_priv); > > +

Re: [Intel-gfx] [PATCH v3 00/12] drm/i915: Separate RC6, RPS, LLC ring Frequency management

On 10/7/2017 2:03 PM, Chris Wilson wrote: Quoting Sagar Arun Kamble (2017-10-07 08:07:23) With GuC based SLPC, frequency control will be moved to GuC and Host will continue to control RC6 and LLC ring frequency setup. This needs separate handling of RPS, RC6 and LLC ring frequencies in i915

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Split uncore init into vfunc setup and mmio setup

On Sat, 07 Oct 2017 10:56:58 +0200, Chris Wilson wrote: Some early initialisation functions (like intel_uc_init_early) would like to access the table of mmio registers sorted by their powerwell, which is currently setup later in intel_uncore_init(). Since this is a

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Split uncore init into vfunc setup and mmio setup

== Series Details == Series: series starting with [1/2] drm/i915: Split uncore init into vfunc setup and mmio setup URL : https://patchwork.freedesktop.org/series/31531/ State : failure == Summary == Test kms_cursor_legacy: Subgroup cursorA-vs-flipA-atomic-transitions:

Re: [Intel-gfx] [drm/i915] 202c1ca611: WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#intel_uncore_forcewake_for_reg[i915]

On Sat, 07 Oct 2017 06:25:09 +0200, kernel test robot wrote: FYI, we noticed the following commit (built with gcc-6): commit: 202c1ca611488c621eed76cd63132a2c2838ee5f ("drm/i915: Move core GuC functions into dedicated file") url:

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,01/21] mm/shmem: introduce shmem_file_setup_with_mnt

Quoting Patchwork (2017-10-07 06:19:37) > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5938/shards.html No surprises this time, so pushed. Need to sit down and think about the context issue. It's a bad interaction between context-pinning and evict_for_something, I

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Split uncore init into vfunc setup and mmio setup

== Series Details == Series: series starting with [1/2] drm/i915: Split uncore init into vfunc setup and mmio setup URL : https://patchwork.freedesktop.org/series/31531/ State : success == Summary == Series 31531v1 series starting with [1/2] drm/i915: Split uncore init into vfunc setup and

[Intel-gfx] [PATCH 1/2] drm/i915: Split uncore init into vfunc setup and mmio setup

Some early initialisation functions (like intel_uc_init_early) would like to access the table of mmio registers sorted by their powerwell, which is currently setup later in intel_uncore_init(). Since this is a static table that now doesn't touch hw, once upon a time we needed to probe ivb to

[Intel-gfx] [PATCH 2/2] drm/i915: Remove early invocations of i915_engines_cleanup()

Engines are now only allocated during init_mmio, so we can forgo iterating over the empty list and calling kfree(NULL) prior to intel_engines_init_mmio(). Fixes: 63ffbcdadcf2 ("drm/i915: Sanitize engine context sizes") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen

Re: [Intel-gfx] [drm/i915] 202c1ca611: WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#intel_uncore_forcewake_for_reg[i915]

Quoting Chris Wilson (2017-10-07 09:36:07) > Quoting kernel test robot (2017-10-07 05:25:09) > > kern :warn : [ 72.33] WARNING: CPU: 0 PID: 179 at > > drivers/gpu/drm/i915/intel_uncore.c:1839 > > intel_uncore_forcewake_for_reg+0x1bb/0x250 [i915] > > kern :warn : [ 72.37] Modules

Re: [Intel-gfx] [drm/i915] 202c1ca611: WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#intel_uncore_forcewake_for_reg[i915]

Quoting kernel test robot (2017-10-07 05:25:09) > FYI, we noticed the following commit (built with gcc-6): > > commit: 202c1ca611488c621eed76cd63132a2c2838ee5f ("drm/i915: Move core GuC > functions into dedicated file") > url: >

Re: [Intel-gfx] [PATCH v3 00/12] drm/i915: Separate RC6, RPS, LLC ring Frequency management

Quoting Sagar Arun Kamble (2017-10-07 08:07:23) > With GuC based SLPC, frequency control will be moved to GuC and Host will > continue to control RC6 and LLC ring frequency setup. This needs separate > handling of RPS, RC6 and LLC ring frequencies in i915 flows. We still > continue use the

Re: [Intel-gfx] [PATCH v3 12/12] drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup

Quoting Sagar Arun Kamble (2017-10-07 08:07:35) > Defined new struct intel_rc6 to hold RC6 specific state and > intel_ring_pstate to hold ring specific state. > > v2: s/intel_ring_pstate/intel_llc_pstate. Removed checks from > autoenable_* functions. (Chris) > > Signed-off-by: Sagar Arun Kamble

Re: [Intel-gfx] [PATCH v3 11/12] drm/i915: Create generic functions to control RC6, RPS

Quoting Sagar Arun Kamble (2017-10-07 08:07:34) > Prepared generic functions intel_enable_rc6, intel_disable_rc6, > intel_enable_rps and intel_disable_rps functions to setup RC6/RPS > based on platforms. > > v2: Make intel_enable/disable_rc6/rps static. (Chris) > > v3: Added

Re: [Intel-gfx] [PATCH v3 10/12] drm/i915: Create generic function to setup LLC ring frequency table

Quoting Sagar Arun Kamble (2017-10-07 08:07:33) > Prepared intel_update_ring_freq function to setup ring frequency > for applicable platforms determined by macro HAS_LLC. > > v2: Replaced NEEDS_RING_FREQ_UPDATE with HAS_LLC macro. (Chris) > Added check while calling from

Re: [Intel-gfx] [PATCH v3 09/12] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled

Quoting Sagar Arun Kamble (2017-10-07 08:07:32) > This function gives the status of RC6, whether disabled or if > enabled then which state. intel_enable_rc6 will be used for > enabling RC6 in the next patch. > > v2: Rebase. > > v3: Rebase. > > Signed-off-by: Sagar Arun Kamble

Re: [Intel-gfx] [PATCH v3 07/12] drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock

Quoting Sagar Arun Kamble (2017-10-07 08:07:30) > In order to separate GT PM related functionality into new structure > we are updating rps structure. hw_lock in it is used for display > related PCU communication too hence move it to dev_priv. > > Signed-off-by: Sagar Arun Kamble

Re: [Intel-gfx] [PATCH v3 08/12] drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "gt_pm"

Quoting Sagar Arun Kamble (2017-10-07 08:07:31) > Prepared substructure rps for RPS related state. autoenable_work is > used for RC6 too hence it is defined outside rps structure. As we do > this lot many functions are refactored to use intel_rps *rps to access > rps related members. Hence renamed

Re: [Intel-gfx] [PATCH v3 06/12] drm/i915: Name i915_runtime_pm structure in dev_priv as "runtime_pm"

Quoting Sagar Arun Kamble (2017-10-07 08:07:29) > We were using dev_priv->pm for runtime power management related state. > This patch renames it to "runtime_pm" which looks more apt. > > v2: s/rpm/runtime_pm (Chris) > > Signed-off-by: Sagar Arun Kamble > Cc: Imre Deak

Re: [Intel-gfx] [PATCH v3 01/12] drm/i915: Separate RPS and RC6 handling for gen6+

Quoting Sagar Arun Kamble (2017-10-07 08:07:24) > This patch separates enable/disable of RC6 and RPS for gen6+ > platforms prior to VLV. > > v2: Fixed checkpatch issue. (Sagar) > > Signed-off-by: Sagar Arun Kamble > Cc: Imre Deak > Cc: Chris

Re: [Intel-gfx] [PATCH v14 5/7] vfio: ABI for mdev display dma-buf operation

> -Original Message- > From: Gerd Hoffmann [mailto:kra...@redhat.com] > Sent: Friday, October 6, 2017 8:13 PM > To: Zhang, Tina ; zhen...@linux.intel.com; Wang, Zhi > A ; Tian, Kevin ; Alex > Williamson

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Separate RC6, RPS, LLC ring Frequency management (rev2)

== Series Details == Series: drm/i915: Separate RC6, RPS, LLC ring Frequency management (rev2) URL : https://patchwork.freedesktop.org/series/31487/ State : warning == Summary == Series 31487v2 drm/i915: Separate RC6, RPS, LLC ring Frequency management

[Intel-gfx] [PATCH v3 09/12] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled

This function gives the status of RC6, whether disabled or if enabled then which state. intel_enable_rc6 will be used for enabling RC6 in the next patch. v2: Rebase. v3: Rebase. Signed-off-by: Sagar Arun Kamble Cc: Chris Wilson Cc: Imre Deak

[Intel-gfx] [PATCH v3 03/12] drm/i915: Separate RPS and RC6 handling for BDW

This patch separates RC6 and RPS enabling for BDW. RC6/RPS Disabling are handled through gen6 functions. PM Programming guide recommends a sequence within forcewakes to configure RC6, RPS and ring frequencies in sequence. With this patch the order is still maintained. v2: Update sequence numbers

[Intel-gfx] [PATCH v3 08/12] drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "gt_pm"

Prepared substructure rps for RPS related state. autoenable_work is used for RC6 too hence it is defined outside rps structure. As we do this lot many functions are refactored to use intel_rps *rps to access rps related members. Hence renamed intel_rps_client pointer variables to rps_client in

[Intel-gfx] [PATCH v3 06/12] drm/i915: Name i915_runtime_pm structure in dev_priv as "runtime_pm"

We were using dev_priv->pm for runtime power management related state. This patch renames it to "runtime_pm" which looks more apt. v2: s/rpm/runtime_pm (Chris) Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson

[Intel-gfx] [PATCH v3 05/12] drm/i915: Separate RPS and RC6 handling for CHV

This patch separates enable/disable of RC6 and RPS for CHV. v2: Fixed comment. Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson Cc: Joonas Lahtinen Reviewed-by: Radoslaw

[Intel-gfx] [PATCH v3 11/12] drm/i915: Create generic functions to control RC6, RPS

Prepared generic functions intel_enable_rc6, intel_disable_rc6, intel_enable_rps and intel_disable_rps functions to setup RC6/RPS based on platforms. v2: Make intel_enable/disable_rc6/rps static. (Chris) v3: Added lockdep_assert_held(dev_priv->pcu_lock) in new generic functions. (Chris) Removed

[Intel-gfx] [PATCH v3 10/12] drm/i915: Create generic function to setup LLC ring frequency table

Prepared intel_update_ring_freq function to setup ring frequency for applicable platforms determined by macro HAS_LLC. v2: Replaced NEEDS_RING_FREQ_UPDATE with HAS_LLC macro. (Chris) Added check while calling from intel_enable_gt_powersave. v3:

[Intel-gfx] [PATCH v3 02/12] drm/i915: Remove superfluous IS_BDW checks and non-BDW changes from gen8_enable_rps

This patch removes all IS_BROADWELL checks and non-BDW changes from gen8_enable_rps as it is called only for BROADWELL. Suggested-by: Chris Wilson Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson

[Intel-gfx] [PATCH v3 04/12] drm/i915: Separate RPS and RC6 handling for VLV

This patch separates enable/disable of RC6 and RPS for VLV. v2: Removed unnecessary comments about forcewakes while enabling RC6/RPS. Added changes to output turbo control status for VLV in i915_frequency_info. Signed-off-by: Sagar Arun Kamble Cc: Imre Deak

[Intel-gfx] [PATCH v3 07/12] drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock

In order to separate GT PM related functionality into new structure we are updating rps structure. hw_lock in it is used for display related PCU communication too hence move it to dev_priv. Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris

[Intel-gfx] [PATCH v3 12/12] drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup

Defined new struct intel_rc6 to hold RC6 specific state and intel_ring_pstate to hold ring specific state. v2: s/intel_ring_pstate/intel_llc_pstate. Removed checks from autoenable_* functions. (Chris) Signed-off-by: Sagar Arun Kamble Cc: Imre Deak

[Intel-gfx] [PATCH v3 01/12] drm/i915: Separate RPS and RC6 handling for gen6+

This patch separates enable/disable of RC6 and RPS for gen6+ platforms prior to VLV. v2: Fixed checkpatch issue. (Sagar) Signed-off-by: Sagar Arun Kamble Cc: Imre Deak Cc: Chris Wilson Cc: Joonas Lahtinen

[Intel-gfx] [PATCH v3 00/12] drm/i915: Separate RC6, RPS, LLC ring Frequency management

With GuC based SLPC, frequency control will be moved to GuC and Host will continue to control RC6 and LLC ring frequency setup. This needs separate handling of RPS, RC6 and LLC ring frequencies in i915 flows. We still continue use the *gt_powersave routines with separate status variables for RPS,