Re: [Intel-gfx] [PATCH 2/5] drm/vblank: Fix data type width for drm_crtc_arm_vblank_event()

Dhinakaran Pandiyan writes: > Now that drm_vblank_count() returns all bits of the vblank count, update > drm_crtc_arm_vblank_event() so that it queues the correct sequence. > Otherwise, this leads to prolonged waits for a vblank sequence when the > current count is

Re: [Intel-gfx] [PATCH 1/5] drm/vblank: Fix return type for drm_vblank_count()

Dhinakaran Pandiyan writes: > drm_vblank_count() has a u32 type returning what is a 64-bit vblank > count. It looks like a general review of the 64-bit widening patch is needed. * drm_crtc_accurate_vblank_count has a 32-bit return, and uses a 32-bit temporary

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/guc: Fix return from guc_log_relay_file_create

== Series Details == Series: series starting with [1/3] drm/i915/guc: Fix return from guc_log_relay_file_create URL : https://patchwork.freedesktop.org/series/37382/ State : success == Summary == Series 37382v1 series starting with [1/3] drm/i915/guc: Fix return from

[Intel-gfx] [PATCH 2/3] drm/i915/guc: Handle interrupt based logging with lack of SSE4.1, relay and other setup

On some systems like skl-gvtdvm, SSE4.1 movntdqa might not be available. movntdqa is needed for efficient capture of the logs from uncached GuC log buffer. GuC init was tied with this support and other setup needed for interrupt based GuC log capture like relay channel/file support and uncached

[Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix return from guc_log_relay_file_create

guc_log_relay_file_create will return -EEXIST if we invoke relay_late_setup_files multiple times as part of i915_guc_log_control. However this is to be not cosidered as fail and need to return 0. This was mistakenly introduced in the below commit. Fix it. Fixes: 70deeaddc6e6 "drm/i915/guc: Fix

[Intel-gfx] [PATCH 3/3] [HAX] drm/i915/guc: Enable GuC and logging for CI

Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_params.h | 4 ++-- drivers/gpu/drm/i915/intel_guc_log.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h

[Intel-gfx] ✓ Fi.CI.IGT: success for tests/kms_frontbuffer_tracking: Including DRRS test coverage

== Series Details == Series: tests/kms_frontbuffer_tracking: Including DRRS test coverage URL : https://patchwork.freedesktop.org/series/37334/ State : success == Summary == Test kms_sysfs_edid_timing: pass -> WARN (shard-apl) fdo#100047 Test kms_cursor_legacy:

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Flush ggtt writes through the old fenced vma before changing fences

== Series Details == Series: drm/i915: Flush ggtt writes through the old fenced vma before changing fences URL : https://patchwork.freedesktop.org/series/37355/ State : warning == Summary == Test kms_cursor_legacy: Subgroup 2x-long-flip-vs-cursor-legacy: fail ->

Re: [Intel-gfx] [PATCH] Revert "drm/i915: mark all device info struct with __initconst"

On Tue, Jan 30, 2018 at 08:44:46AM +, Jani Nikula wrote: > On Mon, 29 Jan 2018, Jani Nikula wrote: > > On Mon, 29 Jan 2018, Lionel Landwerlin > > wrote: > >> On 29/01/18 09:02, Chris Wilson wrote: > >>> Quoting Lionel Landwerlin

Re: [Intel-gfx] [PATCH] drm/i915: Remove Firmware URL.

On Tue, Jan 30, 2018 at 09:06:14AM +, Chris Wilson wrote: > Quoting Rodrigo Vivi (2018-01-29 21:40:27) > > On Mon, Jan 29, 2018 at 08:45:24PM +, Chris Wilson wrote: > > > Quoting Srivatsa, Anusha (2018-01-29 20:17:25) > > > > > > > > > > > > >-Original Message- > > > > >From:

Re: [Intel-gfx] [PATCH 10/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.

On Tue, Jan 30, 2018 at 08:46:49PM +, Ville Syrjälä wrote: > On Tue, Jan 30, 2018 at 12:42:12PM -0800, Rodrigo Vivi wrote: > > On Tue, Jan 30, 2018 at 07:45:03AM +, Jani Nikula wrote: > > > On Mon, 29 Jan 2018, Rodrigo Vivi wrote: > > > > On CNL SKUs that uses port

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Optimize drop-caches

== Series Details == Series: drm/i915: Optimize drop-caches URL : https://patchwork.freedesktop.org/series/37351/ State : failure == Summary == Test drv_suspend: Subgroup fence-restore-untiled: pass -> DMESG-WARN (shard-snb) fdo#102365 Test prime_self_import:

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Convert intel_hpd_irq_event() into an encoder hotplug hook

Almost forgot to respond to this one! Reviewed-by: Lyude Paul On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Allow encoders to customize their hotplug processing by moving the > intel_hpd_irq_event() code into

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Track whether the DP link is trained or not

Reviewed-by: Lyude Paul On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > LSPCON likes to throw short HPDs during the enable seqeunce prior to the > link being trained. These obviously result in the channel CR/EQ

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Move SST DP link retraining into the ->post_hotplug() hook

On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Doing link retraining from the short pulse handler is problematic since > that might introduce deadlocks with MST sideband processing. Currently > we don't retrain MST links from this

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Nuke intel_dp->channel_eq_status

Reviewed-by: Lyude Paul On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > intel_dp->channel_eq_status is used in exactly one function, and we > don't need it to persist between calls. So just go back to using a >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix Limited Range Color Handling (rev4)

== Series Details == Series: drm/i915: Fix Limited Range Color Handling (rev4) URL : https://patchwork.freedesktop.org/series/35725/ State : failure == Summary == Test pm_rc6_residency: Subgroup rc6-accuracy: skip -> PASS (shard-snb) Test kms_vblank:

Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD

On Wed, 2018-01-17 at 21:21 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > The LG 4k TV I have doesn't deassert HPD when I turn the TV off, but > when I turn it back on it will pulse the HPD line. By that time it has > forgotten everything we told it about

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing

== Series Details == Series: series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing URL : https://patchwork.freedesktop.org/series/37344/ State : failure == Summary == Test kms_rotation_crc: Subgroup sprite-rotation-180:

[Intel-gfx] ✗ Fi.CI.IGT: failure for ICL mergeable patches

== Series Details == Series: ICL mergeable patches URL : https://patchwork.freedesktop.org/series/37341/ State : failure == Summary == Test kms_plane: Subgroup plane-panning-bottom-right-suspend-pipe-b-planes: dmesg-warn -> PASS (shard-snb) Test perf_pmu:

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+

== Series Details == Series: series starting with [1/7] drm/i915: Don't set cursor pipe select bits on g4x+ URL : https://patchwork.freedesktop.org/series/37362/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK

Re: [Intel-gfx] [PATCH 10/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.

On Tue, Jan 30, 2018 at 12:42:12PM -0800, Rodrigo Vivi wrote: > On Tue, Jan 30, 2018 at 07:45:03AM +, Jani Nikula wrote: > > On Mon, 29 Jan 2018, Rodrigo Vivi wrote: > > > On CNL SKUs that uses port F, max DP rate is 8.1G for all > > > ports when we have the elevated

Re: [Intel-gfx] [PATCH 10/10] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.

On Tue, Jan 30, 2018 at 07:45:03AM +, Jani Nikula wrote: > On Mon, 29 Jan 2018, Rodrigo Vivi wrote: > > On CNL SKUs that uses port F, max DP rate is 8.1G for all > > ports when we have the elevated voltage (higher than 0.85V). > > > > v2: Make commit message more

[Intel-gfx] ✓ Fi.CI.BAT: success for tests/kms_frontbuffer_tracking: Including DRRS test coverage

== Series Details == Series: tests/kms_frontbuffer_tracking: Including DRRS test coverage URL : https://patchwork.freedesktop.org/series/37334/ State : success == Summary == IGT patchset tested on top of latest successful build 3f820260ce660cdff7fb803237c57554a29498c0

[Intel-gfx] [PATCH 4/7] drm/i915: Clean up cursor defines

From: Ville Syrjälä Use MCURSOR_ instead of CURSOR_ as the prefix for the non-845/865 cursor defines consistently, and move the pipe CSC enable bit next to the other non-845/865 cursor defines. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 5/7] drm/i915: Disable trickle feed for SNB/IVB cursors

From: Ville Syrjälä We disable trickle feed whenever possible, except for the cursors on SNB/IVB. Let's try disabling it there too if for no other reason than consistency. Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 6/7] drm/i915: Drop WaDoubleCursorLP3Latency:ivb

From: Ville Syrjälä WaDoubleCursorLP3Latency was meant for pre-production hardware. Drop it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 deletions(-) diff --git

[Intel-gfx] [PATCH 7/7] drm/i915: s/plane/i9xx_plane/

From: Ville Syrjälä Call the enum i9xx_plane_id variable i9xx_plane like we do elsewhere. Cc: Hans de Goede Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dsi.c | 8 1 file changed, 4

[Intel-gfx] [PATCH 3/7] drm/i915: Have plane->get_hw_state() return the current pipe

From: Ville Syrjälä Like we do for encoder let's make the plane->get_hw_state() return the pipe to which the plane is currently attached. We don't currently allow planes to move between the pipes, but perhaps one day we will. In either case this makes the code

[Intel-gfx] [PATCH 1/7] drm/i915: Don't set cursor pipe select bits on g4x+

From: Ville Syrjälä G4x cursor control registers still allow us to write to the pipe select bits even though cursors are supposed to be fixed to a specific pipe. Bspec tells us that we should only ever write 0 to these bits. Let's follow that recommendation. On

[Intel-gfx] [PATCH 2/7] drm/i915: Set the primary plane pipe select bits on gen4

From: Ville Syrjälä i965 and g4x still have the pipe select bits in the plane control registers, they're just hardcoded to select a specific pipe. However plane C on i965 can still move between the pipes, thus we should program the pipe select bits on i965 if we

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.

On Tue, Jan 30, 2018 at 08:05:41PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for > another SKU. > URL : https://patchwork.freedesktop.org/series/37309/ > State : failure > > == Summary == > > Applying:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add a new modparam for customized ring multiplier (rev2)

== Series Details == Series: drm/i915: Add a new modparam for customized ring multiplier (rev2) URL : https://patchwork.freedesktop.org/series/35535/ State : failure == Summary == Series 35535v2 drm/i915: Add a new modparam for customized ring multiplier

Re: [Intel-gfx] [PATCH] drm/i915: Fix Limited Range Color Handling

On Tue, Jan 30, 2018 at 03:23:32PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >Sent: Friday, December 22, 2017 9:43 PM > >To: Shankar, Uma > >Cc: intel-gfx@lists.freedesktop.org; Lin,

Re: [Intel-gfx] [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

On Tue, Jan 30, 2018 at 07:52:14PM +, Pandiyan, Dhinakaran wrote: > > On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote: > > From: "Kumar, Mahesh" > > > > Platforms before Gen11 were sharing lanes between port-A & port-E. > > This limitation is no more there. >

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.

== Series Details == Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. URL : https://patchwork.freedesktop.org/series/37309/ State : failure == Summary == Applying: drm/i915/cnl: Add Cannonlake PCI IDs for another SKU. Using index info to reconstruct

[Intel-gfx] ✓ Fi.CI.BAT: success for ICL mergeable patches

== Series Details == Series: ICL mergeable patches URL : https://patchwork.freedesktop.org/series/37341/ State : success == Summary == Series 37341v1 ICL mergeable patches https://patchwork.freedesktop.org/api/1.0/series/37341/revisions/1/mbox/ fi-bdw-5557u total:288 pass:267 dwarn:0

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing

== Series Details == Series: series starting with [1/3] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing URL : https://patchwork.freedesktop.org/series/37338/ State : success == Summary == Warning: bzip CI_DRM_3701/shard-glkb6/results1.json.bz2 wasn't in correct JSON

Re: [Intel-gfx] [PATCH] drm/i915/icl: remove port A/E lane sharing limitation.

On Tue, 2018-01-30 at 14:51 +0530, Mahesh Kumar wrote: > From: "Kumar, Mahesh" > > Platforms before Gen11 were sharing lanes between port-A & port-E. > This limitation is no more there. > > Changes since V1: > - optimize the code (Shashank/Jani) > - create helper

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Flush ggtt writes through the old fenced vma before changing fences

== Series Details == Series: drm/i915: Flush ggtt writes through the old fenced vma before changing fences URL : https://patchwork.freedesktop.org/series/37355/ State : success == Summary == Series 37355v1 drm/i915: Flush ggtt writes through the old fenced vma before changing fences

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Optimize drop-caches

== Series Details == Series: drm/i915: Optimize drop-caches URL : https://patchwork.freedesktop.org/series/37351/ State : success == Summary == Series 37351v1 drm/i915: Optimize drop-caches https://patchwork.freedesktop.org/api/1.0/series/37351/revisions/1/mbox/ Test debugfs_test:

Re: [Intel-gfx] [PATCH] drm/i915: Only allocate preempt context when required

Quoting Lis, Tomasz (2018-01-30 18:47:55) > > > On 2018-01-27 21:28, Chris Wilson wrote: > > If we remove some hardcoded assumptions about the preempt context having > > a fixed id, reserved from use by normal user contexts, we may only > > allocate the i915_gem_context when required. Then the

Re: [Intel-gfx] [PATCH] drm/i915: Only allocate preempt context when required

On 2018-01-27 21:28, Chris Wilson wrote: If we remove some hardcoded assumptions about the preempt context having a fixed id, reserved from use by normal user contexts, we may only allocate the i915_gem_context when required. Then the subsequent decisions on using preemption reduce to having

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix Limited Range Color Handling (rev4)

== Series Details == Series: drm/i915: Fix Limited Range Color Handling (rev4) URL : https://patchwork.freedesktop.org/series/35725/ State : success == Summary == Series 35725v4 drm/i915: Fix Limited Range Color Handling https://patchwork.freedesktop.org/api/1.0/series/35725/revisions/4/mbox/

[Intel-gfx] [RFC] drm/i915: cpufreq based dynamic ring freqency table on Gen9

A known issue that ring frequency transition would lead to a full system stall had impacted the media performance when the GT frequency is lower than IA freqency and there's heavy GT workload while having low IA workload. In this case, the ring frequency will be toggled between GT and IA

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use the correct maximum in skl_compute_plane_wm (rev2)

== Series Details == Series: drm/i915: Use the correct maximum in skl_compute_plane_wm (rev2) URL : https://patchwork.freedesktop.org/series/37342/ State : failure == Summary == Applying: drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm error: sha1 information is lacking or

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS

== Series Details == Series: drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS URL : https://patchwork.freedesktop.org/series/37345/ State : failure == Summary == Applying: drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS Using index info to reconstruct a base tree... M

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Restore HDCP DRM_INFO when with no downstream (rev2)

== Series Details == Series: drm/i915: Restore HDCP DRM_INFO when with no downstream (rev2) URL : https://patchwork.freedesktop.org/series/36921/ State : failure == Summary == Applying: drm/i915: Restore HDCP DRM_INFO when with no downstream error: Failed to merge in the changes. Using index

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing

== Series Details == Series: series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing URL : https://patchwork.freedesktop.org/series/37344/ State : success == Summary == Series 37344v1 series starting with [v2,1/2] drm/i915/bxt, glk: Increase PCODE

[Intel-gfx] ✓ Fi.CI.BAT: success for ICL mergeable patches

== Series Details == Series: ICL mergeable patches URL : https://patchwork.freedesktop.org/series/37341/ State : success == Summary == Series 37341v1 ICL mergeable patches https://patchwork.freedesktop.org/api/1.0/series/37341/revisions/1/mbox/ Test debugfs_test: Subgroup

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/icl: remove port A/E lane sharing limitation.

== Series Details == Series: drm/i915/icl: remove port A/E lane sharing limitation. URL : https://patchwork.freedesktop.org/series/37325/ State : warning == Summary == Test perf: Subgroup enable-disable: fail -> PASS (shard-apl) fdo#103715 Subgroup

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing

== Series Details == Series: series starting with [1/3] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing URL : https://patchwork.freedesktop.org/series/37338/ State : success == Summary == Series 37338v1 series starting with [1/3] drm/i915/bxt, glk: Increase PCODE

Re: [Intel-gfx] [PATCH v4 1/7] drm/i915: Add CRTC output format YCBCR 4:2:0

Regards Shashank On 1/30/2018 3:53 PM, Jani Nikula wrote: On Tue, 30 Jan 2018, Shashank Sharma wrote: From: "Sharma, Shashank" Currently, we are using a bool in CRTC state (state->ycbcr420), to indicate modeset, that the output format

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable debugobjects for request validation (rev3)

== Series Details == Series: drm/i915: Enable debugobjects for request validation (rev3) URL : https://patchwork.freedesktop.org/series/37240/ State : success == Summary == Series 37240v3 drm/i915: Enable debugobjects for request validation

[Intel-gfx] [PATCH] drm/i915: Flush ggtt writes through the old fenced vma before changing fences

This is a precautionary measure as I have no evidence to suggest we've hit a bug here (I was hoping this might explain gdg's odd behaviour, but alas), but given that we have a function to flush the ggtt writes it seems prudent to use it prior to changing the fence register. Due to the intrinsic

[Intel-gfx] ✓ Fi.CI.IGT: success for dma-buf: Refanctor reservation_object_add_shared_fence()

== Series Details == Series: dma-buf: Refanctor reservation_object_add_shared_fence() URL : https://patchwork.freedesktop.org/series/37327/ State : success == Summary == Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON format Test kms_flip: Subgroup

Re: [Intel-gfx] [PATCH v2] drm/i915: Restore HDCP DRM_INFO when with no downstream

On Tue, Jan 30, 2018 at 09:29:34AM -0500, Sean Paul wrote: > The commit below returned earlier than before, but failed to move the > info message when authenticating without downstream devices. This patch > restores the message on authentication success. > > Changes in v2: > - s/no downstream

Re: [Intel-gfx] [PATCH] drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS

On Tue, Jan 30, 2018 at 04:12:14PM +0100, Daniel Vetter wrote: > On Tue, Jan 30, 2018 at 09:47:01AM -0500, Sean Paul wrote: > > HDCP was a bit too chatty to get along with the rest of the i915 driver. > > > > Suggested-by: Daniel Vetter > > Signed-off-by: Sean Paul

Re: [Intel-gfx] [PATCH] drm/i915: Always run hangcheck while the GPU is busy

Quoting Mika Kuoppala (2018-01-30 13:00:50) > Chris Wilson writes: > > > Quoting Mika Kuoppala (2018-01-30 12:18:17) > >> Chris Wilson writes: > >> > >> > Previously, we relied on only running the hangcheck while somebody was > >> > waiting

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation.

== Series Details == Series: drm/i915/icl: remove port A/E lane sharing limitation. URL : https://patchwork.freedesktop.org/series/37325/ State : success == Summary == Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.

Re: [Intel-gfx] [PATCH v11 5/6] drm/i915: add query uAPI

On 30/01/18 15:01, Lahtinen, Joonas wrote: On Mon, 2018-01-29 at 16:24 +, Lionel Landwerlin wrote: Thanks all, I don't really read much opposition to the current patch series. If anything we could actually want to do more it seems. It would be good to have the green light and land that.

[Intel-gfx] [PATCH] drm/i915: Optimize drop-caches

Although this is a debugfs routine, so it may seem a little pointless to optimize, it is heavily used by igt to idle the driver and HW between every test. As such, speeding it from 40ms to 40us on a plain Broadwell system is beneficial overall. Signed-off-by: Chris Wilson

Re: [Intel-gfx] [v3] drm/i915: Fix Limited Range Color Handling

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Tuesday, January 30, 2018 8:53 PM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ; >Syrjala, Ville ;

[Intel-gfx] [v4] drm/i915: Fix Limited Range Color Handling

From: Johnson Lin Some panels support limited range output (16-235) compared to full range RGB values (0-255). Also userspace can control the RGB range using "Broadcast RGB" property. Currently the code to handle full range to limited range is broken. This patch fixes the

[Intel-gfx] ✓ Fi.CI.IGT: success for dma-buf: Refanctor reservation_object_add_shared_fence()

== Series Details == Series: dma-buf: Refanctor reservation_object_add_shared_fence() URL : https://patchwork.freedesktop.org/series/37327/ State : success == Summary == Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON format Test kms_flip: Subgroup

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/bxt, glk: Avoid long atomic poll during CDCLK change

Quoting Imre Deak (2018-01-30 14:29:39) > There is no requirement for doing the PCODE request polling atomically, > so do that only for a short time switching to sleeping poll afterwards. > The specification requires a 150usec timeout for the change notification, > so let's use that for the atomic

Re: [Intel-gfx] [PATCH] drm/i915: Fix Limited Range Color Handling

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Friday, December 22, 2017 9:43 PM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ; >Syrjala, Ville ;

Re: [Intel-gfx] [v3] drm/i915: Fix Limited Range Color Handling

On Tue, Jan 30, 2018 at 08:49:22PM +0530, Uma Shankar wrote: > From: Johnson Lin > > Some panels support limited range output (16-235) compared > to full range RGB values (0-255). Also userspace can control > the RGB range using "Broadcast RGB" property. Currently the >

Re: [Intel-gfx] [PATCH] drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm

On Tue, Jan 30, 2018 at 04:05:20PM +0100, Maarten Lankhorst wrote: > According to bspec, result_lines > 31 is only a maximum for latency > level 1 through 7. > > For level 0 the number of lines is ignored, so always write 0 there > to prevent overflowing the 5 bits value. > > This is required to

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: remove port A/E lane sharing limitation.

== Series Details == Series: drm/i915/icl: remove port A/E lane sharing limitation. URL : https://patchwork.freedesktop.org/series/37325/ State : success == Summary == Warning: bzip CI_DRM_3697/shard-glkb6/results1.json.bz2 wasn't in correct JSON format Test kms_sysfs_edid_timing:

Re: [Intel-gfx] [PATCH] drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS

On Tue, Jan 30, 2018 at 09:47:01AM -0500, Sean Paul wrote: > HDCP was a bit too chatty to get along with the rest of the i915 driver. > > Suggested-by: Daniel Vetter > Signed-off-by: Sean Paul Reviewed-by: Daniel Vetter >

[Intel-gfx] [v3] drm/i915: Fix Limited Range Color Handling

From: Johnson Lin Some panels support limited range output (16-235) compared to full range RGB values (0-255). Also userspace can control the RGB range using "Broadcast RGB" property. Currently the code to handle full range to limited range is broken. This patch fixes the

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915: Add display WA #1175 for planes ending close to right screen edge

On Tue, Jan 16, 2018 at 02:05:30PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [v2,1/2] drm/i915: Add display WA #1175 for > planes ending close to right screen edge > URL : https://patchwork.freedesktop.org/series/36526/ > State : failure The failures look

[Intel-gfx] [PATCH] drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm

According to bspec, result_lines > 31 is only a maximum for latency level 1 through 7. For level 0 the number of lines is ignored, so always write 0 there to prevent overflowing the 5 bits value. This is required to make NV12 work. Signed-off-by: Maarten Lankhorst

Re: [Intel-gfx] [PATCH v11 5/6] drm/i915: add query uAPI

On Mon, 2018-01-29 at 16:24 +, Lionel Landwerlin wrote: > > Thanks all, > > I don't really read much opposition to the current patch series. If > anything we could actually want to do more it seems. > It would be good to have the green light and land that. > I've played quickly with a Chris'

[Intel-gfx] [PATCH] drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS

HDCP was a bit too chatty to get along with the rest of the i915 driver. Suggested-by: Daniel Vetter Signed-off-by: Sean Paul --- drivers/gpu/drm/i915/intel_hdcp.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH v2 2/2] drm/i915/bxt, glk: Avoid long atomic poll during CDCLK change

There is no requirement for doing the PCODE request polling atomically, so do that only for a short time switching to sleeping poll afterwards. The specification requires a 150usec timeout for the change notification, so let's use that for the atomic poll. Do the extra 2ms poll - needed as a

[Intel-gfx] [PATCH v2] drm/i915: Restore HDCP DRM_INFO when with no downstream

The commit below returned earlier than before, but failed to move the info message when authenticating without downstream devices. This patch restores the message on authentication success. Changes in v2: - s/no downstream devices/no repeater present/ (Ram) Fixes: 87eb3ec818fa ("drm/i915: II

[Intel-gfx] [PATCH v2 1/2] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing

Currently we see sporadic timeouts during CDCLK changing both on BXT and GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by changing the frequency in a tight loop after blanking the display. The upper bound for the completion time is 800us based on my tests, so increase it

[Intel-gfx] ✗ Fi.CI.BAT: failure for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2)

== Series Details == Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2) URL : https://patchwork.freedesktop.org/series/36068/ State : failure == Summary == Series 36068v2 YCBCR 4:2:0/4:4:4 output support for LSPCON

Re: [Intel-gfx] [PATCH] drm/i915: Restore HDCP DRM_INFO when with no downstream

On Tue, Jan 30, 2018 at 09:35:34AM +0100, Daniel Vetter wrote: > On Mon, Jan 22, 2018 at 12:55:00PM -0500, Sean Paul wrote: > > The commit below returned earlier than before, but failed to move the > > info message when authenticating without downstream devices. This patch > > restores the message

Re: [Intel-gfx] [PATCH 1/3] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing

On Tue, Jan 30, 2018 at 03:42:45PM +0200, Ville Syrjälä wrote: > On Tue, Jan 30, 2018 at 01:47:10PM +0200, Imre Deak wrote: > > Currently we see sporadic timeouts during CDCLK changing both on BXT and > > GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by > > changing the

Re: [Intel-gfx] [PATCH] drm/i915: Use the correct maximum in skl_compute_plane_wm

On Tue, Jan 30, 2018 at 02:54:11PM +0100, Maarten Lankhorst wrote: > According to bspec, result_lines > 31 is only a maximum for latency > level 1 through 7, so correctly apply the check there. The register still has only 5 bits for the line watermark. However the spec says "Hardware ignores the

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Enable debugobjects for request validation (rev3)

== Series Details == Series: drm/i915: Enable debugobjects for request validation (rev3) URL : https://patchwork.freedesktop.org/series/37240/ State : failure == Summary == Test perf: Subgroup oa-exponents: pass -> FAIL (shard-apl) fdo#102254

[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf: Refanctor reservation_object_add_shared_fence()

== Series Details == Series: dma-buf: Refanctor reservation_object_add_shared_fence() URL : https://patchwork.freedesktop.org/series/37327/ State : success == Summary == Series 37327v1 dma-buf: Refanctor reservation_object_add_shared_fence()

[Intel-gfx] [PATCH] drm/i915: Use the correct maximum in skl_compute_plane_wm

According to bspec, result_lines > 31 is only a maximum for latency level 1 through 7, so correctly apply the check there. This is required to make NV12 work. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH 9/9] drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register

This enables the Mesa driver to advertise support for ARB_timer_query, and thus an OpenGL version higher than 3.2. Based on the CNL patch by Nanley Chery. v2: Rebase. Cc: Anuj Phogat Cc: Nanley Chery Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 7/9] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field

From: James Ausmus ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23], however, all existing PLANE_CTL_FORMAT_* definitions still map to the correct values. Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use that for masking for the conversion to

[Intel-gfx] [PATCH 3/9] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed

From: Mahesh Kumar ICL require DDB allocation of plane to be more than "minimum display buffer needed" for each level in order to enable WM level. This patch implements and consider the same while allocating DDB and enabling WM. Changes Since V1: - rebase Changes

[Intel-gfx] [PATCH 4/9] drm/i915/icl: NV12 y-plane ddb is not in same plane

From: Mahesh Kumar We don't have planar pixel format support implemented for ICL yet. ICL require 2 display planes to be allocated for Planar formats unlike previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in NV12_BUF_CFG register and

[Intel-gfx] [PATCH 6/9] drm/i915/gen11: fix the SAGV block time for gen11

It's 10us for gen 11. Reviewed-by: Mahesh Kumar Reviewed-by: James Ausmus Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 5/9] drm/i915/icl: Introduce MBus related registers

From: Mahesh Kumar This patch introduce MBus control registers and their bit-fields MBUS_ABOX_CTL MBUS_BBOX_CTL MBUS_DBOX_CTL MBUS_UBOX_CTL Changes Since V1: - Use function like macros (Paulo) - fix copy-paste error (Paulo) Reviewed-by: Paulo Zanoni

[Intel-gfx] [PATCH 8/9] drm/i915/icl: Set graphics mode register for gen11

From: Kelvin Gardiner This patch clears a single bit. The bit is 0 by default but expected not to be set. Explicitly clearing the bit in this patch is intended to indicate some thinking has occurred, and that we want this bit cleared and we are not just excepting the

[Intel-gfx] [PATCH 2/9] drm/i915/icl: Do not fix dbuf block size to 512

From: Mahesh Kumar GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a fixed number anymore in GEN11, it varies according to bits per pixel and tiling. If 8bpp & Yf-tile surface, block size = 256 else block size = 512 This patch addresses the same. v2

[Intel-gfx] [PATCH 1/9] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL

From: Mahesh Kumar GEN9 onwards bypass path allocation of 4 blocks was needed, as per hardware design. ICL doesn't require bypass path allocation of 4 DDB blocks, handling the same in this patch. v2 (from Paulo): - No need for a comment that says what the code already

[Intel-gfx] [PATCH 0/9] ICL mergeable patches

These patches were part of the other ICL series that arrived on the list a few days ago, they already received public reviews. They should be good to go, but let's see what the CI system has to say about them first. James Ausmus (1): drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field Kelvin

Re: [Intel-gfx] [PATCH 1/3] drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing

On Tue, Jan 30, 2018 at 01:47:10PM +0200, Imre Deak wrote: > Currently we see sporadic timeouts during CDCLK changing both on BXT and > GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by > changing the frequency in a tight loop after blanking the display. The > upper bound for

[Intel-gfx] ✓ Fi.CI.BAT: success for dma-buf: Refanctor reservation_object_add_shared_fence()

== Series Details == Series: dma-buf: Refanctor reservation_object_add_shared_fence() URL : https://patchwork.freedesktop.org/series/37327/ State : success == Summary == Series 37327v1 dma-buf: Refanctor reservation_object_add_shared_fence()

[Intel-gfx] ✗ Fi.CI.BAT: warning for YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2)

== Series Details == Series: YCBCR 4:2:0/4:4:4 output support for LSPCON (rev2) URL : https://patchwork.freedesktop.org/series/36068/ State : warning == Summary == Series 36068v2 YCBCR 4:2:0/4:4:4 output support for LSPCON

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation.

== Series Details == Series: drm/i915/icl: remove port A/E lane sharing limitation. URL : https://patchwork.freedesktop.org/series/37325/ State : success == Summary == Series 37325v1 drm/i915/icl: remove port A/E lane sharing limitation.

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