Hello,
*TL;DR*: how can I set a 8960x2880 screen (not display) size on a T580? A
patch for i915 that I found on the internets does not seem to work.
Full story:
I'm a rather happy user of ThinkPad T580 which comes with a
high-density 3840x2160 LCD, and the following graphics hardware.
00:02.0
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Use a full emulation of
a user ppgtt context
URL : https://patchwork.freedesktop.org/series/46890/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4516_full -> Patchwork_9722_full =
== Summary -
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Use a full emulation of
a user ppgtt context
URL : https://patchwork.freedesktop.org/series/46890/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4515_full -> Patchwork_9721_full =
== Summary -
== Series Details ==
Series: drm/i915: Fix psr sink status report. (rev3)
URL : https://patchwork.freedesktop.org/series/46831/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4518 -> Patchwork_9726 =
== Summary - FAILURE ==
Serious unknown changes coming with
Anusha,
This is not the correct latest patch. This still doesnt have _MMIO for DSCA_
and DSCC registers.
On Tue, Jul 17, 2018 at 02:10:59PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha"
>
> Display Stream Compression(DSC) has a set of Picture
> Parameter Set(PPS) components that the
On Thu, 2018-07-19 at 17:31 -0700, Rodrigo Vivi wrote:
> First of all don't try to read dpcd if PSR is not even supported.
>
> But also, if read failed return -EIO instead of reporting via a
> backchannel.
>
> v2: fix dev_priv: At this level m->private is the connector. (CI/DK)
> don't
On Thu, Jul 19, 2018 at 05:16:03PM -0700, Nathan Ciobanu wrote:
> On Thu, Jul 19, 2018 at 04:42:17PM -0700, Rodrigo Vivi wrote:
> > Just a small clean-up with no functional change, only
> > removing a variable that is never actually used.
> >
> > Cc: Dhinakaran Pandiyan
> > Signed-off-by:
First of all don't try to read dpcd if PSR is not even supported.
But also, if read failed return -EIO instead of reporting via a
backchannel.
v2: fix dev_priv: At this level m->private is the connector. (CI/DK)
don't convert dpcd read errors to EIO. (DK)
Fixes: 5b7b30864d1d ("drm/i915/psr:
== Series Details ==
Series: series starting with [v5,2/2] drm/i915/dp: Refactor mav_vswing_tries
variable (rev2)
URL : https://patchwork.freedesktop.org/series/46897/
State : failure
== Summary ==
Applying: drm/i915/dp: Refactor mav_vswing_tries variable
error: sha1 information is lacking
On Thu, Jul 19, 2018 at 04:42:17PM -0700, Rodrigo Vivi wrote:
> Just a small clean-up with no functional change, only
> removing a variable that is never actually used.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Rodrigo Vivi
Nice one :)
Reviewed-by:
> ---
>
Changes the type and renames the max_vswing_tries variable
which was declared as an integer but used as a boolean
making it easy to be confused with a counter.
Changes in v2:
- updated the title and commit message
- left the loop exit point in place
v3: fix typo in title
Cc: Dhinakaran
== Series Details ==
Series: drm/i915: Remove unused "ret" variable.
URL : https://patchwork.freedesktop.org/series/46904/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4517 -> Patchwork_9724 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4515_full -> Patchwork_9720_full =
== Summary - FAILURE ==
Serious unknown changes coming with
Just a small clean-up with no functional change, only
removing a variable that is never actually used.
Cc: Dhinakaran Pandiyan
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp_mst.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
On Thu, Jul 19, 2018 at 11:51:40AM -0700, Dhinakaran Pandiyan wrote:
> On Wed, 2018-07-18 at 22:43 -0700, Rodrigo Vivi wrote:
> > On Wed, Jul 18, 2018 at 10:19:43AM -0700, Dhinakaran Pandiyan wrote:
> > >
> > > We are too late in the enabling sequence to back out cleanly, not
> > > updating
> > >
On 7/19/18 1:56 PM, Takashi Iwai wrote:
On Thu, 19 Jul 2018 15:05:45 +0200,
Pierre-Louis Bossart wrote:
On 7/19/18 12:50 AM, Takashi Iwai wrote:
On Wed, 18 Jul 2018 22:54:35 +0200,
Pierre-Louis Bossart wrote:
On 07/17/2018 04:26 AM, Takashi Iwai wrote:
Hi,
this is a preliminiary patch
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/icl: move has_resource_streamer
to GEN11_FEATURES
URL : https://patchwork.freedesktop.org/series/46884/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4514_full -> Patchwork_9719_full =
== Summary -
On Thu, Jul 19, 2018 at 02:47:59PM -0700, Atwood, Matthew S wrote:
> On Thu, 2018-07-19 at 14:07 -0700, Rodrigo Vivi wrote:
> > On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atw...@intel.com
> > wrote:
> > > From: Matt Atwood
> > >
> > > According to DP spec (2.9.3.1 of DP 1.4) if
> > >
Changes the type and renames the max_vswing_tries variable
which was declared as an integer but used as a boolean
making it easy to be confused with a counter.
Changes in v2:
- updated the title and commit message
- left the loop exit point in place
Cc: Dhinakaran Pandiyan
Cc: Rodrigo
Limit the link training clock recovery loop to 10 attempts at
LANEx_CR_DONE per DP 1.4 spec section 3.5.1.2.2 and 80 attempts for
pre-DP 1.4 (4 voltage levels x 4 preemphasis levels x
x 5 identical voltages tries). Some faulty USB-C MST hubs can
cause us to get stuck in this loop indefinitely
On Thu, 2018-07-19 at 14:07 -0700, Rodrigo Vivi wrote:
> On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atw...@intel.com
> wrote:
> > From: Matt Atwood
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> >
== Series Details ==
Series: series starting with [1/2] drm/dp: add extended receiver capability
field present bit (rev3)
URL : https://patchwork.freedesktop.org/series/46743/
State : failure
== Summary ==
Applying: drm/dp: add extended receiver capability field present bit
Applying: drm/dp:
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Use a full emulation of
a user ppgtt context
URL : https://patchwork.freedesktop.org/series/46890/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4516 -> Patchwork_9722 =
== Summary - SUCCESS ==
== Series Details ==
Series: drm/i915: Cache the error string (rev4)
URL : https://patchwork.freedesktop.org/series/46777/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4513_full -> Patchwork_9718_full =
== Summary - WARNING ==
Minor unknown changes coming with
On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
>
On Thu, Jul 19, 2018 at 01:35:48PM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> This bit was added to DP Training Aux RD interval sometime between DP
> 1.2 and DP 1.3.
I understand that some 1.2 version that I had here that caused
all the trouble around XXX 1.2, but since
From: Matt Atwood
This bit was added to DP Training Aux RD interval sometime between DP
1.2 and DP 1.3. Via description of the spec this field indicates the
panels true capabilities are described in DPCD address space 02200h
through 022FFh.
v2: version comment update
Signed-off-by: Matt Atwood
From: Matt Atwood
According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 0h through Fh, except for DPCD_REV,
MAX_LINK_RATE,
Quoting Ville Syrjälä (2018-07-19 21:16:20)
> > > > > +} __packed;
> > > > > +
> > > > > +static inline void assert_intel_remapped_info_is_packed(void)
> > > > > +{
> > > > > + BUILD_BUG_ON(sizeof(struct intel_remapped_info) !=
> > > > > 10*sizeof(unsigned int));
>
> Hmm. These assert
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Use a full emulation of
a user ppgtt context
URL : https://patchwork.freedesktop.org/series/46890/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4515 -> Patchwork_9721 =
== Summary - FAILURE ==
On Thu, Jul 19, 2018 at 08:03:42PM +, Shaikh, Azhar wrote:
>
>
> >-Original Message-
> >From: Shaikh, Azhar
> >Sent: Friday, July 6, 2018 11:38 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: ville.syrj...@linux.intel.com; Navare, Manasi D
> >; Shaikh, Azhar
> >Subject: [PATCH v8]
On Thu, Jul 19, 2018 at 08:46:54PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-07-19 20:33:57)
> > On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-07-19 19:22:11)
> > > > +static struct scatterlist *
> > > > +remap_pages(const dma_addr_t
>-Original Message-
>From: Shaikh, Azhar
>Sent: Friday, July 6, 2018 11:38 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: ville.syrj...@linux.intel.com; Navare, Manasi D
>; Shaikh, Azhar
>Subject: [PATCH v8] drm/i915: Fix assert_plane() warning on bootup with
>external display
>
>On KBL,
On Thu, Jul 19, 2018 at 08:46:54PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-07-19 20:33:57)
> > On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-07-19 19:22:11)
> > > > +static struct scatterlist *
> > > > +remap_pages(const dma_addr_t
On Thu, Jul 19, 2018 at 12:12:08PM -0700, Lucas De Marchi wrote:
> On Thu, Jul 19, 2018 at 10:18 AM Rodrigo Vivi wrote:
> >
> > On Thu, Jul 19, 2018 at 10:05:57AM -0700, Lucas De Marchi wrote:
> > > After disabling resource streamer on ICL (due to it actually not
> > > existing there), I got
On older HW, gen2/3, fence registers are used for detiling GPU commands
and as such changing those registers requires serialisation with the
requests on the GPU. Anything running on the GPU is subject to a hang,
and so we must be able to recover cleanly in the middle of a stuck wait
on a fence
To test eviction from a ppgtt, we just want a ppgtt i.e. something other
than the Global GTT which is shared and used by the kernel for HW
features like fencing and scanout. However, we also need it to pass
!i915_is_ggtt() and the simplest way is to emulate a full user context
rather than the
Quoting Ville Syrjälä (2018-07-19 20:33:57)
> On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-07-19 19:22:11)
> > > +static struct scatterlist *
> > > +remap_pages(const dma_addr_t *in, unsigned int offset,
> > > + unsigned int width,
On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-07-19 19:22:11)
> > +static struct scatterlist *
> > +remap_pages(const dma_addr_t *in, unsigned int offset,
> > + unsigned int width, unsigned int height,
> > + unsigned int stride,
> >
On Thu, Jul 19, 2018 at 08:01:12PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-07-19 19:22:12)
> > From: Ville Syrjälä
> >
> > The display engine stride limits are getting in our way. On SKL+
> > we are limited to 8k pixels, which is easily exceeded with three
> > 4k displays. To
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4515 -> Patchwork_9720 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Thu, Jul 19, 2018 at 10:18 AM Rodrigo Vivi wrote:
>
> On Thu, Jul 19, 2018 at 10:05:57AM -0700, Lucas De Marchi wrote:
> > After disabling resource streamer on ICL (due to it actually not
> > existing there), I got feedback that there have been some experimental
> > patches for mesa to use RS
Quoting Ville Syrjala (2018-07-19 19:22:12)
> From: Ville Syrjälä
>
> The display engine stride limits are getting in our way. On SKL+
> we are limited to 8k pixels, which is easily exceeded with three
> 4k displays. To overcome this limitation we can remap the pages
> in the GTT to provide the
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Fix glk/cnl display w/a #1175
Okay!
Commit: drm/i915: s/tile_offset/aligned_offset/
Okay!
Quoting Ville Syrjala (2018-07-19 19:22:11)
> +static struct scatterlist *
> +remap_pages(const dma_addr_t *in, unsigned int offset,
> + unsigned int width, unsigned int height,
> + unsigned int stride,
> + struct sg_table *st, struct scatterlist *sg)
> +{
> +
On Thu, 19 Jul 2018 15:05:45 +0200,
Pierre-Louis Bossart wrote:
>
> On 7/19/18 12:50 AM, Takashi Iwai wrote:
> > On Wed, 18 Jul 2018 22:54:35 +0200,
> > Pierre-Louis Bossart wrote:
> >>
> >>
> >>
> >> On 07/17/2018 04:26 AM, Takashi Iwai wrote:
> >>> Hi,
> >>>
> >>> this is a preliminiary patch
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0655c1625b0a drm/i915: Fix glk/cnl display w/a #1175
c95e166cfd63 drm/i915: s/tile_offset/aligned_offset/
On Thu, Jul 19, 2018 at 10:01:41AM -0700, Rodrigo Vivi wrote:
> On Tue, Jul 17, 2018 at 06:05:51PM -0700, Nathan Ciobanu wrote:
> > On Tue, Jul 17, 2018 at 03:21:17PM -0700, Dhinakaran Pandiyan wrote:
> > > On Mon, 2018-07-16 at 16:51 -0700, Marc Herbert wrote:
> > > > >
> > > > > >
> > > > > >
max_vswing_tries variable was declared as an int but
used as a bool and not even needed because we can
just check the return of intel_dp_link_max_vswing_reached.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Cc: Marc Herbert
Signed-off-by: Nathan Ciobanu
---
Limit the link training clock recovery loop to 10 attempts at
LANEx_CR_DONE per DP 1.4 spec section 3.5.1.2.2 and 80 attempts for
pre-DP 1.4 (4 voltage levels x 4 preemphasis levels x
x 5 identical voltages tries). Some faulty USB-C MST hubs can
cause us to get stuck in this loop indefinitely
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, July 19, 2018 9:42 PM
> To: Chauhan, Madhav
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Zanoni, Paulo R ; Vivi, Rodrigo
>
> Subject: Re: [Intel-gfx] [PATCH v5 01/13]
On Wed, 2018-07-18 at 22:43 -0700, Rodrigo Vivi wrote:
> On Wed, Jul 18, 2018 at 10:19:43AM -0700, Dhinakaran Pandiyan wrote:
> >
> > We are too late in the enabling sequence to back out cleanly, not
> > updating
> > state tracking variables, like intel_dp->active_mst_links in this
> > instance,
From: Ville Syrjälä
Move the display w/a #1175 to a better place. That place
being the new skl+ specific plane->check() hook. This leaves
the skl_check_plane_surface() stuff to deal with the gtt offset
and src coordinate stuff as originally envisioned.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
We can easily calculate the plane can_scale/min_downscale on demand.
And later on we'll probably want to start calculating these dynamically
based on the cdclk just as skl already does.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 8 +---
From: Ville Syrjälä
Rename some of the tile_offset() functions to aligned_offset() since
they operate on both linear and tiled functions. And we'll include
_plane_ in the name of all the variants that take a plane state.
Should make it more clear which function to use where.
Signed-off-by:
From: Ville Syrjälä
Move the chv rotation vs. reflections checks to the plane->check() hook,
away from the (now) platform agnostic
intel_plane_atomic_check_with_state().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 9 -
From: Ville Syrjälä
With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.
No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/icl: move has_resource_streamer
to GEN11_FEATURES
URL : https://patchwork.freedesktop.org/series/46884/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4514 -> Patchwork_9719 =
== Summary - SUCCESS ==
No
From: Ville Syrjälä
With gtt remapping in place we can use arbitraily large framebuffers.
Let's bump the limits as high as we can (32k-1). Going beyond that
would require switching out s16.16 src coordinate representation to
something with more spare bits.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
To overcome display engine stride limits we'll want to remap the
pages in the GTT. To that end we need a new gtt_view type which
is just like the "rotated" type except not rotated.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +
From: Ville Syrjälä
The display engine stride limits are getting in our way. On SKL+
we are limited to 8k pixels, which is easily exceeded with three
4k displays. To overcome this limitation we can remap the pages
in the GTT to provide the display engine with a view of memory
with a smaller
From: Ville Syrjälä
Extract intel_cursor_check_surface() to better match the code layout
of the other plane types.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 47 ++--
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git
From: Ville Syrjälä
The display engine has unfortunately low stride limits when compared to
modern display resolutions. 2x4k is about as big as we can go currently.
This series aims to overcome that by shuffling the pages in the GTT to
provide the display engine with a view of memory with a
From: Ville Syrjälä
Move the skl+ specific framebuffer related checks from
intel_plane_atomic_check_with_state() into a new function
(skl_plane_check_fb()) which we'll simply call from the skl
plane->check() hook.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 42
From: Ville Syrjälä
The workaround was supposed to look at the plane destination
coordinates. Currently it's looking at some mixture of src
and dst coordinates that doesn't make sense. Fix it up.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 7 ---
1 file
From: Ville Syrjälä
Stash the gtt_view structure into the plane state. This will become
useful when we do GTT remapping as the gtt_view will not come directly
from the fb anymore.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 16 +---
From: Ville Syrjälä
To reduce the confusion between a drm plane and the planes of
framebuffers let's desiginate the latter as "color plane".
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 106 ++-
drivers/gpu/drm/i915/intel_drv.h |
From: Ville Syrjälä
Split up intel_check_primary_plane() and intel_check_sprite_plane()
into per-platform variants. This way we can get a unified behaviour
between the SKL universal planes, and we stop checking for non-SKL
specific scaling limits for the "sprite" planes. And we now get
a natural
From: Ville Syrjälä
Let's assume that the primary plane for pipe A has the highest max
stride of all planes, and we'll use that as the global limit when
creating a new framebuffer.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 33 ++---
1
From: Ville Syrjälä
Make the main/aux surface stuff a bit more generic by using an array
of structures. This will allow us to deal with both the main and aux
surfaces with common code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 56
From: Ville Syrjälä
Let's store the final plane stride in the plane state. This avoids
having to pick betwen the normal vs. rotated stride during hardware
programming. And once we get GTT remapping the plane stride will
no longer match the fb stride so we'll need a place to store it
anyway.
From: Ville Syrjälä
Each plane may have different stride limitations. Let's add a new
plane function to retutn the maximum stride for each plane. There's
going to be some use for this outside the .atomic_check() stuff hence
the separate hook.
Signed-off-by: Ville Syrjälä
---
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/icl: move has_resource_streamer
to GEN11_FEATURES
URL : https://patchwork.freedesktop.org/series/46884/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: move has_resource_streamer to
== Series Details ==
Series: drm/i915: Cache the error string (rev4)
URL : https://patchwork.freedesktop.org/series/46777/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4513 -> Patchwork_9718 =
== Summary - SUCCESS ==
No regressions found.
External URL:
CC'ing gvt maintainers (and fixing Jani's address in CC).
See below
On Wed, 2018-07-18 at 13:01 +0300, Ville Syrjälä wrote:
> On Tue, Jul 17, 2018 at 03:16:53PM -0700, Lucas De Marchi wrote:
> > On Fri, Jul 13, 2018 at 9:10 AM Ville Syrjälä
> > wrote:
> > >
> > > On Fri, Jul 13, 2018 at
On Thu, Jul 19, 2018 at 10:05:57AM -0700, Lucas De Marchi wrote:
> After disabling resource streamer on ICL (due to it actually not
> existing there), I got feedback that there have been some experimental
> patches for mesa to use RS years ago, but nothing ever landed or shipped
> because there
-19
for you to fetch changes up to ef821e3f14e868779505bf08f96afb4eade53652:
drm/i915: Update DRIVER_DATE to 20180719 (2018-07-19 08:47:59 -0700)
On GEM side:
- GuC related fixes (Chris, Michal)
- GTT read-only pages support (
== Series Details ==
Series: drm/i915: Cache the error string (rev4)
URL : https://patchwork.freedesktop.org/series/46777/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Cache the error string
+drivers/gpu/drm/i915/i915_gpu_error.c:846:25: warning: Using plain
After disabling resource streamer on ICL (due to it actually not
existing there), I got feedback that there have been some experimental
patches for mesa to use RS years ago, but nothing ever landed or shipped
because there was no performance improvement.
This removes it from kernel keeping the
Resource streamer has been removed on GEN11 so move it to the FEATURES
macro.
Signed-off-by: Lucas De Marchi
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c| 2 +-
2 files changed, 2 insertions(+), 2
On Tue, Jul 17, 2018 at 06:05:51PM -0700, Nathan Ciobanu wrote:
> On Tue, Jul 17, 2018 at 03:21:17PM -0700, Dhinakaran Pandiyan wrote:
> > On Mon, 2018-07-16 at 16:51 -0700, Marc Herbert wrote:
> > > >
> > > > >
> > > > > I think the bug is with this infinite loop which is at the mercy
> > > > >
Currently, we convert the error state into a string every time we read
from sysfs (and sysfs reads in page size (4KiB) chunks). We do try to
window the string and only capture the portion that is being read, but
that means that we must always convert up to the window to find the
start. For a very
Quoting Tvrtko Ursulin (2018-07-19 17:37:56)
> From: Tvrtko Ursulin
>
> Restore runtime PM state (via a newly added library function) when the
> test which sets it up exit. This was we avoid running all subsequent sub-
> tests in the aggressive runtime PM mode.
>
> Signed-off-by: Tvrtko Ursulin
From: Tvrtko Ursulin
Restore runtime PM state (via a newly added library function) when the
test which sets it up exit. This was we avoid running all subsequent sub-
tests in the aggressive runtime PM mode.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_pm.c | 13 -
lib/igt_pm.h
On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
> DSI transcoder registers.
>
> Credits-to: Jani N
>
> Cc: Jani Nikula
> Signed-off-by: Madhav Chauhan
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> 1 file
On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
> This patch programs D-PHY timing parameters for the
> bus turn around flow(in escape clocks) only if dsi link
> frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
> identical register DSI_TA_TIMING_PARAM (inside DSI
> Controller
On Tue, Jul 10, 2018 at 03:10:08PM +0530, Madhav Chauhan wrote:
> This patch programs D-PHY timing parameters for the
> clock and data lane (in escape clocks) of DSI
> controller (DSI port 0 and 1).
> These programmed timings would be used by DSI Controller
> to calculate link transition latencies
On Tue, Jul 10, 2018 at 03:10:02PM +0530, Madhav Chauhan wrote:
> This patch set the loadgen select and latency optimization for
> aux and transmit lanes of combo phy transmitters. It will be
> used for MIPI DSI HS operations.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan
> ---
>
Quoting Kenneth Graunke (2018-07-17 21:02:33)
> On Tuesday, July 17, 2018 2:57:50 AM PDT Chris Wilson wrote:
> > We should we have all the kinks worked out and full-ppgtt now works
> > reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can
> > let userspace have full control over
On 2018-07-19 09:12, Joonas Lahtinen wrote:
Quoting Lis, Tomasz (2018-07-18 18:28:32)
On 2018-07-18 16:42, Tvrtko Ursulin wrote:
On 18/07/2018 14:24, Joonas Lahtinen wrote:
Quoting Tomasz Lis (2018-07-16 16:07:16)
+++ b/include/uapi/drm/i915_drm.h
@@ -1456,6 +1456,13 @@ struct
== Series Details ==
Series: drm/i915/execlists: Move the assertion we have the rpm wakeref down
URL : https://patchwork.freedesktop.org/series/46837/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4509_full -> Patchwork_9716_full =
== Summary - WARNING ==
Minor unknown
On 7/19/18 12:50 AM, Takashi Iwai wrote:
On Wed, 18 Jul 2018 22:54:35 +0200,
Pierre-Louis Bossart wrote:
On 07/17/2018 04:26 AM, Takashi Iwai wrote:
Hi,
this is a preliminiary patch set to convert the existing i915 /
HD-audio component binding to be applicable to other drivers like
radeon
== Series Details ==
Series: drm/i915/kvmgt: fix an error code in gvt_dma_map_page()
URL : https://patchwork.freedesktop.org/series/46842/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4508_full -> Patchwork_9715_full =
== Summary - WARNING ==
Minor unknown changes
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/guc: Fix GuC pin bias and WOPCM
initialization order
URL : https://patchwork.freedesktop.org/series/46843/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4510 -> Patchwork_9717 =
== Summary - FAILURE ==
Quoting Tvrtko Ursulin (2018-07-19 13:14:38)
>
> On 19/07/2018 12:59, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-07-19 12:49:13)
> >>
> >> On 19/07/2018 08:50, Chris Wilson wrote:
> >>> There's a race between idling the engine and finishing off the last
> >>> tasklet (as we may kick the
On 19/07/2018 12:59, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-07-19 12:49:13)
On 19/07/2018 08:50, Chris Wilson wrote:
There's a race between idling the engine and finishing off the last
tasklet (as we may kick the tasklets after declaring an individual
engine idle). However, since
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/guc: Fix GuC pin bias and WOPCM
initialization order
URL : https://patchwork.freedesktop.org/series/46843/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/guc: Fix GuC pin bias and WOPCM
Quoting Tvrtko Ursulin (2018-07-19 12:49:13)
>
> On 19/07/2018 08:50, Chris Wilson wrote:
> > There's a race between idling the engine and finishing off the last
> > tasklet (as we may kick the tasklets after declaring an individual
> > engine idle). However, since we do not need to access the
On 19/07/2018 08:50, Chris Wilson wrote:
There's a race between idling the engine and finishing off the last
tasklet (as we may kick the tasklets after declaring an individual
engine idle). However, since we do not need to access the device until
we try to submit to the ELSP register
Quoting Tvrtko Ursulin (2018-07-19 12:42:06)
>
> On 19/07/2018 09:33, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/execlists: Move the assertion we have the rpm wakeref down
> > URL : https://patchwork.freedesktop.org/series/46837/
> > State : failure
> >
> > == Summary
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