Re: [Intel-gfx] [PATCH] drm/i915: Add ppgtt to GVT GEM context

Quoting Zhenyu Wang (2018-10-19 04:05:20) > On 2018.10.18 13:40:31 +0800, Xiong Zhang wrote: > > Currently the guest couldn't boot up under GVT-g environment as the > > following call trace exists: > > [ 272.504762] BUG: unable to handle kernel NULL pointer dereference at > > 0100 > >

Re: [Intel-gfx] [RFC 2/8] drm/i915: Use the ddi_ports info to kill ugly CNL_WITH_PORT_F.

On Thu, 18 Oct 2018, Rodrigo Vivi wrote: > Now that we have the number of ddi ports information available > let's use it instead of that ugly platform macro. > > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_drv.c | 10 ++ > drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH v2 3/5] drm/i915: context submission pvmmio optimization

It is performance optimization to reduce mmio trap numbers from 4 to 1 durning ELSP porting writing (context submission). When context subission, to cache elsp_data[4] values in the shared page, the last elsp_data[0] port writing will be trapped to gvt for real context submission. Use PVMMIO_ELSP

[Intel-gfx] [PATCH v2 0/5] i915 pvmmio to improve GVTg performance

To improve GVTg performance, it could reduce the mmio access trap numbers within guest driver in some certain scenarios since mmio access trap will introuduce vm exit/vm enter cost. the solution in this patch set is to setup a shared memory region which accessed both by guest and GVTg without trap

[Intel-gfx] [PATCH v2 4/5] drm/i915: master irq pvmmio optimization

Master irq register is accessed twice every irq handling, then trapped to SOS very frequently. Optimize it by moving master irq register to share page, writing don't need be trapped. When need enable irq to let SOS inject irq timely, use another pvmmio register to achieve this purpose. So avoid on

[Intel-gfx] [PATCH v2 2/5] drm/i915: get ready of memory for pvmmio

To enable pvmmio feature, we need to prepare one 4K shared page which will be accessed by both guest and backend i915 driver. guest i915 allocate one page memory and then the guest physical address is passed to backend i915 driver through PVINFO register so that backend i915 driver can access this

[Intel-gfx] [PATCH v2 1/5] drm/i915: introduced pv capability for vgpu

This u32 pv_caps field is used to control the different level pvmmio feature for MMIO emulation in GVT. This field is default zero, no pvmmio feature enabled. it also add VGT_CAPS_PVMMIO capability BIT for guest to check GVTg can support PV feature or not. v0: RFC, introudced enable_pvmmio modul

[Intel-gfx] [PATCH v2 5/5] drm/i915: ppgtt update pvmmio optimization

This patch extends g2v notification to notify host GVT-g of ppgtt update from guest, including alloc_4lvl, clear_4lv4 and insert_4lvl. It uses shared page to pass the additional params. This patch also add one new pvmmio level to control ppgtt update. Use PVMMIO_PPGTT_UPDATE to control this level

Re: [Intel-gfx] [PULL] drm-intel-next-fixes

On Fri, Oct 19, 2018 at 8:59 AM Joonas Lahtinen wrote: > > Quoting Daniel Vetter (2018-10-18 22:32:00) > > On Thu, Oct 18, 2018 at 6:57 PM Joonas Lahtinen > > wrote: > > > > > > Hi Dave, > > > > > > Here comes the final set of fixes under -next-fixes umbrella. > > > Next one will be then from -fi

[Intel-gfx] [GVT-g] [ANNOUNCE] 2018-Q3 release of XenGT (Intel GVT-g for Xen)

Hi all, We are pleased to announce an update of Intel GVT-g for Xen. Intel GVT-g is a full GPU virtualization solution with mediated pass-through, starting from 4th generation Intel Core(TM) processors with Intel processor graphics. A virtual GPU instance is maintained for each VM, with par

[Intel-gfx] [GVT-g] [ANNOUNCE] 2018-Q3 release of KVMGT (Intel GVT-g for KVM)

Hi all, We are pleased to announce an update of Intel GVT-g for KVM. Intel GVT-g for KVM (a.k.a. KVMGT) is a full GPU virtualization solution with mediated pass-through, starting from 5th generation Intel Core(TM) processors with Intel processor graphics. A virtual GPU instance is maintain

<    1   2