Would like to ask ping for review patch set v2. thanks very much.
BRs, Xiaolin
On 10/19/2018 03:27 PM, Zhang, Xiaolin wrote:
> To improve GVTg performance, it could reduce the mmio access trap
> numbers within guest driver in some certain scenarios since mmio
> access trap will introuduce vm
Reviewed-by: Chunming Zhou
> -Original Message-
> From: Julia Lawall
> Sent: Thursday, October 25, 2018 2:57 AM
> To: Zhou, David(ChunMing)
> Cc: kbuild-...@01.org; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; Christian König
> ; Gustavo Padovan
> ; Maarten
== Series Details ==
Series: drm: fix call_kern.cocci warnings (fwd)
URL : https://patchwork.freedesktop.org/series/51481/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5030_full -> Patchwork_10567_full =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off
(rev5)
URL : https://patchwork.freedesktop.org/series/49447/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5033 -> Patchwork_10570 =
== Summary - WARNING ==
Minor unknown
On Wed, Oct 24, 2018 at 01:22:57PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> > Whenever possible we should stick with IS_GEN checks.
> >
> > Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> > Allow optimized platform checks") for
On Wed, 2018-10-24 at 16:22 -0700, Dhinakaran Pandiyan wrote:
> On Wed, 2018-10-24 at 15:08 -0700, Dhinakaran Pandiyan wrote:
> > On Sat, 2018-10-20 at 00:12 +, Souza, Jose wrote:
> > > On Fri, 2018-10-19 at 16:14 -0700, Dhinakaran Pandiyan wrote:
> > > > On Wed, 2018-10-10 at 17:41 -0700,
On Wed, 2018-10-24 at 15:08 -0700, Dhinakaran Pandiyan wrote:
> On Sat, 2018-10-20 at 00:12 +, Souza, Jose wrote:
> > On Fri, 2018-10-19 at 16:14 -0700, Dhinakaran Pandiyan wrote:
> > > On Wed, 2018-10-10 at 17:41 -0700, José Roberto de Souza wrote:
> > > > While PSR is active hardware will do
On Wed, Oct 24, 2018 at 04:01:09PM -0700, Anusha Srivatsa wrote:
> From: Animesh Manna
>
> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> DC5/6 when appropriate.
>
> v2: (James Ausmus)
> - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>
On Wed, Oct 24, 2018 at 09:48:13PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
Just to confirm, we're
From: Animesh Manna
ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.
v2: (James Ausmus)
- Also handle ICL as GEN9_LP in i915_drm_suspend_late and
i915_drm_suspend_early
- Add DC9 to gen9_dc_mask for ICL
- Re-order GEN checks for newest
Gah, the more I think about this the more I realize this was never the correct
approach to begin with. I wrote this patch a long time ago when I wasn't
nearly as experienced, so that's not terribly surprising.
So: the thing is this isn't actually a problem that's specific to MST. Pretty
much all
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP (rev6)
URL : https://patchwork.freedesktop.org/series/47514/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5033 -> Patchwork_10569 =
== Summary - FAILURE ==
Serious unknown changes coming with
== Series Details ==
Series: Enable Plane Input CSC for ICL
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5029_full -> Patchwork_10566_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP (rev6)
URL : https://patchwork.freedesktop.org/series/47514/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
Okay!
On Fri, Oct 12, 2018 at 11:42:32AM -0700, Radhakrishna Sripada wrote:
> At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> level shifters etc. To workaround them we may need to drive the output
> at a lower bpc. Currently the user space does not have a way to limit
> the bpc. The
On Wed, 2018-10-24 at 18:09 -0400, Lyude Paul wrote:
> Since there's going to be quite a number of changes I need to make to
> this I'm
> just going to make the changes myself! I'll make sure to Cc you with
> the
> respin
Sounds good, thanks for picking it up!
Juston
== Series Details ==
Series: Display Stream Compression enabling on eDP/DP (rev6)
URL : https://patchwork.freedesktop.org/series/47514/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
505058122024 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
65c4be454ee2 drm/dp:
== Series Details ==
Series: drm/i915: Use intel_panel_actually_set_backlight() to disable PWM
backlight
URL : https://patchwork.freedesktop.org/series/51462/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5029_full -> Patchwork_10565_full =
== Summary - SUCCESS ==
No
On Wed, 2018-10-24 at 15:28 -0700, Manasi Navare wrote:
> DSC can be supported per DP connector. This patch adds a per connector
> debugfs node to expose DSC support capability by the kernel.
> The same node can be used from userspace to force DSC enable.
>
> v2:
> * Use kstrtobool_from_user to
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v3:
* Use cpu_transcoder instead of encoder->type
Currently the driver will only enable DSC if a certain mode
does not fit the available link BW. However IGT/userspace
can force DSC enable through dsc support debugfs node to
test the DSC functionality if supported by the panel.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v2:
* Rebase ond drm-tip
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by:
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
From: Gaurav K Singh
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
v2:
* Use kstrtobool_from_user to avoid explicit error checking (Lyude)
* Rebase on drm-tip (Manasi)
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v3 (From Manasi):
- Change the hex values to lower case (Madhav)
- Use BIT macro (Manasi)
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing
VESA has developed an industry standard Display Stream Compression(DSC)
for interoperable, visually lossless compression over display links to
address the needs for higher resolution displays.
This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels.
This implementation is based on
== Series Details ==
Series: drm/i915/hdmi: Detect HDMI 2.0 monitors using multiple EDID
capabilities (rev2)
URL : https://patchwork.freedesktop.org/series/51150/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5033 -> Patchwork_10568 =
== Summary - WARNING ==
Minor
Thought this was going to be an easy review until I realized that there's
multiple problems in nouveau this would cause issues with, even if we didn't
pay attention to the -EINVAL that gets returned. The suspend/resume order in
nouveau needs some fixing up to prevent this patch from causing
== Series Details ==
Series: series starting with [1/2] ALSA: x86: Fix runtime PM for hdmi-lpe-audio
URL : https://patchwork.freedesktop.org/series/51461/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5029_full -> Patchwork_10564_full =
== Summary - SUCCESS ==
No
On Sat, 2018-10-20 at 00:12 +, Souza, Jose wrote:
> On Fri, 2018-10-19 at 16:14 -0700, Dhinakaran Pandiyan wrote:
> > On Wed, 2018-10-10 at 17:41 -0700, José Roberto de Souza wrote:
> > > While PSR is active hardware will do aux transactions by it self
> > > to
> > > wakeup sink to receive a
From: Clint Taylor
HDMI 2.0 monitors may not support SCDC and still be able to accept VICs
above 63. Use multiple EDID capbilities to determine if the SINK is
actually an HDMI 2.0 device. The QD980B HDMI 2.0 Analyzer generates unique
EDIDs during CTS tests that don't contain a HDMI Forum VSDB if
On Wed, Oct 24, 2018 at 09:48:12PM +0530, Uma Shankar wrote:
> Defined the plane input csc coefficient registers and macros.
> 6 registers are used to program a total of 9 coefficients,
> added macros to define each of them for all the planes
> supporting the feature on pipes. On ICL, bottom 3
== Series Details ==
Series: drm: fix call_kern.cocci warnings (fwd)
URL : https://patchwork.freedesktop.org/series/51481/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5030 -> Patchwork_10567 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: drm: fix call_kern.cocci warnings (fwd)
URL : https://patchwork.freedesktop.org/series/51481/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fd425f4226a8 drm: fix call_kern.cocci warnings (fwd)
-:30: WARNING:BAD_SIGN_OFF: Duplicate signature
#30:
The containing function is called with a spin_lock held, so GFP_KERNEL
can't be used.
julia
-- Forwarded message --
Date: Tue, 23 Oct 2018 17:14:25 +0800
From: kbuild test robot
To: kbu...@01.org
Cc: Julia Lawall
Subject: [PATCH] drm: fix call_kern.cocci warnings
CC:
== Series Details ==
Series: series starting with [1/2] locking/lockdep: restore cross-release checks
URL : https://patchwork.freedesktop.org/series/51445/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5027_full -> Patchwork_10562_full =
== Summary - WARNING ==
Minor
== Series Details ==
Series: Enable Plane Input CSC for ICL
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5029 -> Patchwork_10566 =
== Summary - SUCCESS ==
No regressions found.
External URL:
From: Navare, Manasi D
Sent: Friday, October 05, 2018 4:23 PM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Navare, Manasi D; Jani Nikula; Ville Syrjala; Srivatsa, Anusha
Subject: [PATCH v5 28/28] drm/i915/dsc: Force DSC enable
== Series Details ==
Series: Enable Plane Input CSC for ICL
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers
Okay!
Commit: drm/i915/icl:
== Series Details ==
Series: Enable Plane Input CSC for ICL
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
41d6b4c477ae drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:48: CHECK:MACRO_ARG_REUSE: Macro argument
== Series Details ==
Series: drm/i915: Use intel_panel_actually_set_backlight() to disable PWM
backlight
URL : https://patchwork.freedesktop.org/series/51462/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5029 -> Patchwork_10565 =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: series starting with [1/2] locking/lockdep: restore cross-release checks
URL : https://patchwork.freedesktop.org/series/51445/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5026_full -> Patchwork_10561_full =
== Summary - WARNING ==
Minor
On Wed, Oct 24, 2018 at 01:13:51PM +0300, Jani Nikula wrote:
> On Tue, 23 Oct 2018, Rodrigo Vivi wrote:
> > But I thought while doing this I could consolidade it along with all
> > the other has_feature cases.
> >
> > I believe we should either have everything as info.has_feature or everything
>
== Series Details ==
Series: series starting with [1/2] ALSA: x86: Fix runtime PM for hdmi-lpe-audio
URL : https://patchwork.freedesktop.org/series/51461/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5029 -> Patchwork_10564 =
== Summary - SUCCESS ==
No regressions
On Tue, Oct 23, 2018 at 01:39:10PM +0200, Maarten Lankhorst wrote:
>
>
> Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: Fixed
== Series Details ==
Series: series starting with [1/2] ALSA: x86: Fix runtime PM for hdmi-lpe-audio
URL : https://patchwork.freedesktop.org/series/51461/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fc8795c8431a ALSA: x86: Fix runtime PM for hdmi-lpe-audio
-:9:
On Wed, Oct 24, 2018 at 05:35:51PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-10-24 17:33:17)
> > On Wed, Oct 24, 2018 at 05:02:18PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-10-24 16:52:08)
> > > > From: Ville Syrjälä
> > > >
> > > > Use
On Wed, 2018-10-24 at 10:57 +0200, Daniel Vetter wrote:
> On Tue, Oct 23, 2018 at 07:19:23PM -0700, Juston Li wrote:
> >
> > Signed-off-by: Juston Li
>
> For formality, does this also imply a reviewed-by tag?
I'm quite new to drm so I'll withhold a reviewed-by tag and ask that
someone else
Quoting Ville Syrjälä (2018-10-24 17:33:17)
> On Wed, Oct 24, 2018 at 05:02:18PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-10-24 16:52:08)
> > > From: Ville Syrjälä
> > >
> > > Use intel_panel_actually_set_backlight() instead of a direct
> > > call to pwm_config() in
On Wed, Oct 24, 2018 at 05:02:18PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-10-24 16:52:08)
> > From: Ville Syrjälä
> >
> > Use intel_panel_actually_set_backlight() instead of a direct
> > call to pwm_config() in pwm_disable_backlight().
> >
> > The main benefit is consistent
Quoting Ville Syrjälä (2018-10-24 17:28:45)
> On Wed, Oct 24, 2018 at 04:52:22PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-10-24 16:48:24)
> > > From: Ville Syrjälä
> > >
> > > Commit 46e831abe864 ("drm/i915/lpe: Mark LPE audio runtime pm as
> > > "no callbacks"") broke runtime
On Wed, Oct 24, 2018 at 04:52:22PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-10-24 16:48:24)
> > From: Ville Syrjälä
> >
> > Commit 46e831abe864 ("drm/i915/lpe: Mark LPE audio runtime pm as
> > "no callbacks"") broke runtime PM with lpe audio. We can no longer
> > runtime suspend
Quoting Ville Syrjala (2018-10-24 16:48:24)
> From: Ville Syrjälä
>
> Commit 46e831abe864 ("drm/i915/lpe: Mark LPE audio runtime pm as
> "no callbacks"") broke runtime PM with lpe audio. We can no longer
> runtime suspend the GPU since the sysfs power/control for the
> lpe-audio device no
== Series Details ==
Series: drm/i915: Mark skl_update_plane and skl_disable_plane as static
URL : https://patchwork.freedesktop.org/series/51442/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5026_full -> Patchwork_10560_full =
== Summary - WARNING ==
Minor unknown
Quoting Ville Syrjala (2018-10-24 16:52:08)
> From: Ville Syrjälä
>
> Use intel_panel_actually_set_backlight() instead of a direct
> call to pwm_config() in pwm_disable_backlight().
>
> The main benefit is consistent debug logging when we turn off the
> backlight. Currently we see nothing in
This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.
v2: Separated the patch into 2 parts as per Maarten's comments.
Addressed Ville and Maarten's
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats.
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, October 24, 2018 8:10 PM
>To: Maarten Lankhorst
>Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915:
Quoting Ville Syrjala (2018-10-24 16:48:24)
> From: Ville Syrjälä
>
> Commit 46e831abe864 ("drm/i915/lpe: Mark LPE audio runtime pm as
> "no callbacks"") broke runtime PM with lpe audio. We can no longer
> runtime suspend the GPU since the sysfs power/control for the
> lpe-audio device no
From: Ville Syrjälä
Use intel_panel_actually_set_backlight() instead of a direct
call to pwm_config() in pwm_disable_backlight().
The main benefit is consistent debug logging when we turn off the
backlight. Currently we see nothing in dmesg which made me wonder
whether the backlight was even
From: Ville Syrjälä
Ever since commit 46e831abe864 ("drm/i915/lpe: Mark LPE audio runtime
pm as "no callbacks"") the runtime suspend/resume hooks are no longer
used. Inline them into the system suspend hooks.
Cc: Chris Wilson
Cc: Takashi Iwai
Cc: Pierre-Louis Bossart
Signed-off-by: Ville
From: Ville Syrjälä
Commit 46e831abe864 ("drm/i915/lpe: Mark LPE audio runtime pm as
"no callbacks"") broke runtime PM with lpe audio. We can no longer
runtime suspend the GPU since the sysfs power/control for the
lpe-audio device no longer exists and the device is considered
always active. We
== Series Details ==
Series: Add support for Gen 11 pipe color features (rev2)
URL : https://patchwork.freedesktop.org/series/51408/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5028 -> Patchwork_10563 =
== Summary - FAILURE ==
Serious unknown changes coming with
On Wed, Oct 24, 2018 at 03:54:56PM +0100, Julia Lawall wrote:
> > I wish it would look something more like this:
> >
> > @@
> > identifier old =~ "^INTEL_GEN$";
> > expression exp;
> > constant gen;
> > fresh identifier new = "IS_GEN" ## gen;
> > @@
> > - old(exp) == gen
> > + new(exp)
> >
>
== Series Details ==
Series: Add support for Gen 11 pipe color features (rev2)
URL : https://patchwork.freedesktop.org/series/51408/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
019fa0c46108 drm/i915/icl: Add icl pipe degamma and gamma support
-:72: CHECK:SPACING: No space is
> I wish it would look something more like this:
>
> @@
> identifier old=~ "^INTEL_GEN$";
> expression exp;
> constant gen;
> fresh identifier new = "IS_GEN" ## gen;
> @@
> - old(exp) == gen
> + new(exp)
>
> But coccinelle doesn't seem to accept the constant in the fresh
> identifier
Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.
v2: Addressed Maarten's review comments.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 14 --
2 files changed, 13
Add support for icl pipe degamma and gamma.
v2: Removed a POSTING_READ and corrected the Bit
Definition as per Maarten's comments.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 3 ++
drivers/gpu/drm/i915/intel_color.c | 74 ++
2 files
This patch series adds support for Gen11 pipe degamma, CSC
and gamma hardware blocks.
CRC checks are not working for 10bit gamma but works for 8bit
pallete modes which seems to be due to some rounding errors in pipe.
ToDo: Support for Multi Segmented Gamma will be added later.
v2: Addressed
Add the degamma and gamma lut sizes to gen11 capability
structure.
v2: Reorder the patch as per Maarten's suggestion.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c
On Wed, Oct 24, 2018 at 03:42:34PM +0200, Maarten Lankhorst wrote:
> Op 24-10-18 om 15:12 schreef Shankar, Uma:
> >
> >> -Original Message-
> >> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> >> Sent: Wednesday, October 24, 2018 5:37 PM
> >> To: Shankar, Uma ;
== Series Details ==
Series: series starting with [1/2] locking/lockdep: restore cross-release checks
URL : https://patchwork.freedesktop.org/series/51445/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5027 -> Patchwork_10562 =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: drm/i915/perf: Fix warning in documentation
URL : https://patchwork.freedesktop.org/series/51441/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5024_full -> Patchwork_10559_full =
== Summary - WARNING ==
Minor unknown changes coming with
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Wednesday, October 24, 2018 7:08 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/icl: Enable ICL
== Series Details ==
Series: series starting with [1/2] locking/lockdep: restore cross-release checks
URL : https://patchwork.freedesktop.org/series/51445/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5026 -> Patchwork_10561 =
== Summary - FAILURE ==
Serious unknown
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Wednesday, October 24, 2018 6:49 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/icl: Add
>-Original Message-
>From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
>Sent: Wednesday, October 24, 2018 7:04 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add icl
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