== Series Details ==
Series: drm/i915/fia: FIA registers offset implementation.
URL : https://patchwork.freedesktop.org/series/51566/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10596 =
== Summary - SUCCESS ==
No regressions found.
External URL:
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++
1 file
== Series Details ==
Series: Forward Error Correction (rev3)
URL : https://patchwork.freedesktop.org/series/47848/
State : failure
== Summary ==
Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_dp.c).
error:
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state,
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
Cc: Gaurav K Singh
Cc: Jani Nikula
With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
Suggested-by: Ville Syrjala
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by:
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Check if the sink supports FEC using the helper.
v2: Mention External DP where ever FEC is mentioned
in the code.Check return status of dpcd reads. (Gaurav)
- Do regular mode check
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
Suggested-by: Jani Nikula
Cc: Jani Nikula
Cc: Ville
== Series Details ==
Series: drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG
URL : https://patchwork.freedesktop.org/series/51538/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10594 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Make igt for cross-driver, I think you should rename it first, not an intel
specific. NO company wants their employee working on other company stuff.
You can rename it to DGT(drm graphics test), and published following libdrm,
or directly merge to libdrm, then everyone can use it and develop
On 2018.10.25 11:28:28 -0700, Rodrigo Vivi wrote:
> On Thu, Oct 25, 2018 at 04:07:14PM +0300, Joonas Lahtinen wrote:
> > Quoting Zhenyu Wang (2018-10-23 06:46:59)
> > >
> > > Hi,
> > >
> > > Here's gvt-next-fixes for 4.20 with three changes. Mostly
> > > to fix possible arbitrary update on guest
== Series Details ==
Series: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
URL : https://patchwork.freedesktop.org/series/51542/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10585_full =
== Summary - FAILURE ==
Serious unknown changes
> -Original Message-
> From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
> Behalf Of Chris Wilson
> Sent: Thursday, October 25, 2018 8:51 PM
> To: Yuan, Hang
> Cc: intel-gfx@lists.freedesktop.org; joonas.lahti...@linux.intel.com;
> matthew.william.a...@gmail.com;
== Series Details ==
Series: series starting with [1/2] drm/plane: Export
drm_plane_check_pixel_format()
URL : https://patchwork.freedesktop.org/series/51563/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10593 =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2)
URL : https://patchwork.freedesktop.org/series/50649/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10584_full =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: series starting with [1/2] drm/plane: Export
drm_plane_check_pixel_format()
URL : https://patchwork.freedesktop.org/series/51563/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
442fd2d0bbaf drm/plane: Export drm_plane_check_pixel_format()
== Series Details ==
Series: series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in
intel_psr_disable_source()
URL : https://patchwork.freedesktop.org/series/51562/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10592 =
== Summary - FAILURE
Currently there is some duplication of pixel format and modifier
validation code between the fb creation and plane check paths. We can
unify them by checking if any plane supports a pixel format and modifier
combination during framebuffer creation.
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
i915 will make use of this to fail early during framebuffer creation.
Suggested-by: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/drm_plane.c | 1 +
include/drm/drm_plane.h | 11 +++
2 files changed, 12
== Series Details ==
Series: series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in
intel_psr_disable_source()
URL : https://patchwork.freedesktop.org/series/51562/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Use
== Series Details ==
Series: series starting with [v3,01/10] drm/i915/psr: Use intel_psr_exit() in
intel_psr_disable_source()
URL : https://patchwork.freedesktop.org/series/51562/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ed40d086a0b drm/i915/psr: Use intel_psr_exit() in
== Series Details ==
Series: drm/i915/glk: Remove 99% limitation.
URL : https://patchwork.freedesktop.org/series/51561/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10591 =
== Summary - SUCCESS ==
No regressions found.
External URL:
When we detect a error and disable PSR, it is kept disable until the
next modeset but as the sink already show signs that it do not
properly work with PSR lets disabled it for good to avoid any
additional flickering.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
The IIR register is a result of a AND operation between the mask
register and the actual interruption state so checking IIR before
unmask interruptions will never get any errors even if they exits.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c
In the past we had hooks to configure HW for VLV/CHV too, in the drop
of VLV/CHV support the intel_psr_disable_source() code was not moved
to the caller, so doing it here.
Suggested-by: Dhinakaran Pandiyan
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de
If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
will still keep the error set even after the reset done in the
irq_preinstall and irq_uninstall hooks.
And enabling in this situation cause the screen to freeze in the
first time that PSR HW tries to activate so lets keep PSR
While PSR is active hardware will do aux transactions by it self to
wakeup sink to receive a new frame when necessary. If that
transaction is not acked by sink, hardware will trigger this
interruption.
So let's disable PSR as it is a hint that there is problem with this
sink.
The removed FIXME
When a PSR error happens sink sets the PSR errors register and also
set the link to a error status.
So in the short pulse handling it was returning earlier and doing a
full detection and attempting to retrain but it fails as PSR HW is
in change of the main-link.
Just call intel_psr_short_pulse()
All other interruptions gen11 interruptions are reset in
gen11_irq_reset() also it is done for other gens that supports PSR.
Cc: Dhinakaran Pandiyan
Cc: Paulo Zanoni
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
It should always wait for idle state when disabling PSR because PSR
could be inactive due a call to intel_psr_exit() and while PSR is
still being disabled asynchronously userspace could change the
modeset causing a call to psr_disable() that will not wait for PSR
idle and then PSR will be enabled
Some eDP panels do not set a valid sink count value and even for the
ones that sets is should always be one for eDP, that is why it is not
cached in intel_edp_init_dpcd().
But intel_dp_short_pulse() compares the old count with the read one
if there is a mistmatch a full port detection will be
Both functions have the same code to disable PSR, so let's reuse that
code instead of duplicate.
Suggested-by: Dhinakaran Pandiyan
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 50
While checking the opportunity to add a display_gen
check to allow glk and cnl to be on same bucket I noticed
these FIXME cases here.
So I got the confirmation from HW architect that we actually
never needed this workaround.
"GLK supports 2 pixel per clock, so pixel clock can be up to 2 *
On Tue, Oct 23, 2018 at 10:30:18AM +0300, Jani Nikula wrote:
> On Mon, 22 Oct 2018, Rodrigo Vivi wrote:
> > On Mon, Oct 22, 2018 at 05:12:18PM -0700, Paulo Zanoni wrote:
> >> Em Seg, 2018-10-22 às 16:55 -0700, Rodrigo Vivi escreveu:
> >> > On Mon, Oct 22, 2018 at 04:32:00PM -0700, Paulo Zanoni
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Add function to check for
linear surfaces (rev2)
URL : https://patchwork.freedesktop.org/series/51550/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10590 =
== Summary - SUCCESS ==
== Series Details ==
Series: drm/syncobj: Avoid kmalloc(GFP_KERNEL) under spinlock
URL : https://patchwork.freedesktop.org/series/51525/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10581_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51558/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10589 =
== Summary - FAILURE ==
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51558/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dsc: Add
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51558/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48f9de182d37 drm/i915/dsc: Add slice_row_per_frame in
== Series Details ==
Series: drm/i915: HPD IRQ storm detection fixes
URL : https://patchwork.freedesktop.org/series/51556/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10588 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: drm/syncobj: Avoid kmalloc(GFP_KERNEL) under spinlock
URL : https://patchwork.freedesktop.org/series/51525/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10580_full =
== Summary - SUCCESS ==
No regressions found.
A framebuffer can comprise surfaces with distinct tiling formats,
making checks against modifier alone insufficient. Make use of a
function to identify a linear surface based on both modifier and color
plane.
v2: Typo fix
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
== Series Details ==
Series: drm/i915: HPD IRQ storm detection fixes
URL : https://patchwork.freedesktop.org/series/51556/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST
Okay!
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev3)
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10587 =
== Summary - SUCCESS ==
No regressions found.
External URL:
== Series Details ==
Series: attempts at catching mmu_notifer deadlocks
URL : https://patchwork.freedesktop.org/series/51522/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5037_full -> Patchwork_10579_full =
== Summary - FAILURE ==
Serious unknown changes coming with
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev3)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers
Okay!
Commit:
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev3)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
99febf0a6212 drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:54: CHECK:MACRO_ARG_REUSE: Macro
== Series Details ==
Series: series starting with [1/2] drm/i915: Add function to check for linear
surfaces
URL : https://patchwork.freedesktop.org/series/51550/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10586 =
== Summary - FAILURE ==
Serious
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Unfortunately, it seems that the HPD IRQ storm problem from the early
days of Intel GPUs was never entirely solved, only mostly. Within the
last couple of days, I got a bug report from one of our customers who
had been having issues with their machine suddenly booting up very
slowly after having
IMPORTANT -
As a note: I have not had the customer who this second patch is for test
this yet, I'm sending this ahead of time to make sure this is something
that isn't too crazy for upstream to accept. I'm not planning on pushing
this after review until I've verified this actually fixes
Turns out that if you trigger an HPD storm on a system that has an MST
topology connected to it, you'll end up causing the kernel to eventually
hit a NULL deref:
[ 332.339041] BUG: unable to handle kernel NULL pointer dereference at
00ec
[ 332.340906] PGD 0 P4D 0
[ 332.342750]
On Thu, Oct 25, 2018 at 12:36 PM Nathan Chancellor
wrote:
>
> This warning is disabled by default in scripts/Makefile.extrawarn when
> W= is not provided but this Makefile adds -Wall after this warning is
> disabled so it shows up in the build when it shouldn't:
>
> In file included from
On Fri, Oct 26, 2018 at 03:33:37AM +0530, Uma Shankar wrote:
> Defined the plane input csc coefficient registers and macros.
> 6 registers are used to program a total of 9 coefficients,
> added macros to define each of them for all the planes
> supporting the feature on pipes. On ICL, bottom 3
On Fri, Oct 26, 2018 at 03:33:38AM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the
This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.
This series enables color conversion for Full Range YUV data,
limited range handling will be
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats.
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro
A framebuffer can comprise surfaces with distinct tiling formats,
making checks against modifier alone insufficient. Make use of a
function to identify a linear surface based on both modifier and color
plane.
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
---
The PLANE_AUX_OFFSET mmio does not exist on ICL, do not program it. We'll
still calculate the aux offset as it is required for adjusing x-y offsets.
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_sprite.c | 8 +---
1 file
Chris Wilson writes:
> Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> notifiers") we have been able to report failure from
> mmu_invalidate_range_start which allows us to use a trylock on the
> struct_mutex to avoid potential recursion and report -EBUSY instead.
>
On Mon, Oct 22, 2018 at 03:54:45PM -0700, Jeff McGee wrote:
> See https://lists.freedesktop.org/archives/intel-gfx/2018-October/178452.html
> for RFC v1 and the helpful feedback incorporated into this v2.
thanks!
I liked the new one.
Acked-by: Rodrigo Vivi
>
> The GuC firmware team is
On Wed, Oct 24, 2018 at 06:28:02PM -0400, Lyude Paul wrote:
> On Wed, 2018-10-24 at 15:28 -0700, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same node can be used from
On Thu, Oct 25, 2018 at 05:03:06PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:30PM -0700, Manasi Navare wrote:
> > From: Gaurav K Singh
> >
> > This patch enables decompression support in sink device
> > before link training and disables the same during the
> > DDI disabling.
>
== Series Details ==
Series: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
URL : https://patchwork.freedesktop.org/series/51542/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10585 =
== Summary - SUCCESS ==
No regressions found.
External
On Thu, Oct 25, 2018 at 05:09:42PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:34PM -0700, Manasi Navare wrote:
> > DSC PPS secondary data packet infoframes are filled with
> > DSC picure parameter set metadata according to the DSC standard.
> > These infoframes are sent to the
On Thu, Oct 25, 2018 at 05:15:34PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:36PM -0700, Manasi Navare wrote:
> > Display Stream Splitter registers need to be programmed to enable
> > the joiner if two DSC engines are used and also to enable
> > the left and the right DSC
On Thu, Oct 25, 2018 at 05:16:58PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:37PM -0700, Manasi Navare wrote:
> > 1. Disable Left/right VDSC branch in DSS Ctrl reg
> > depending on the number of VDSC engines being used
> > 2. Disable joiner in DSS Ctrl reg
> >
> > v3 (From
== Series Details ==
Series: drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2)
URL : https://patchwork.freedesktop.org/series/50649/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10584 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
URL : https://patchwork.freedesktop.org/series/51542/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Disable -Wuninitialized for intel_breadcrumbs.o
-
== Series Details ==
Series: drm/i915: Fix ilk+ watermarks when disabling pipes
URL : https://patchwork.freedesktop.org/series/51518/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5035_full -> Patchwork_10578_full =
== Summary - FAILURE ==
Serious unknown changes coming
Quoting Daniel Vetter (2018-10-25 20:16:50)
> On Thu, Oct 25, 2018 at 01:45:42PM +0100, Chris Wilson wrote:
> > Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> > notifiers") we have been able to report failure from
> > mmu_invalidate_range_start which allows us to use a
On Thu, Oct 25, 2018 at 05:22:18PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:38PM -0700, Manasi Navare wrote:
> > A separate power well 2 (PG2) is required for VDSC on eDP transcoder
> > whereas all other transcoders use the power wells associated with the
> > transcoders for
This warning is disabled by default in scripts/Makefile.extrawarn when
W= is not provided but this Makefile adds -Wall after this warning is
disabled so it shows up in the build when it shouldn't:
In file included from drivers/gpu/drm/i915/intel_breadcrumbs.c:895:
== Series Details ==
Series: drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values (rev2)
URL : https://patchwork.freedesktop.org/series/50649/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e2ad180a5f8f drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values
-:6:
On Thu, Oct 25, 2018 at 01:45:42PM +0100, Chris Wilson wrote:
> Since commit 93065ac753e4 ("mm, oom: distinguish blockable mode for mmu
> notifiers") we have been able to report failure from
> mmu_invalidate_range_start which allows us to use a trylock on the
> struct_mutex to avoid potential
== Series Details ==
Series: drm/i915: convert HDCP DRM_ERROR into DRM_DEBUG
URL : https://patchwork.freedesktop.org/series/51538/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10583 =
== Summary - FAILURE ==
Serious unknown changes coming with
== Series Details ==
Series: drm/i915/userptr: Avoid struct_mutex recursion for
mmu_invalidate_range_start (rev2)
URL : https://patchwork.freedesktop.org/series/51362/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5035_full -> Patchwork_10577_full =
== Summary - FAILURE
On 10/15/2018 04:31 AM, Jani Nikula wrote:
On Mon, 15 Oct 2018, Jani Nikula wrote:
On Fri, 05 Oct 2018, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N
value mode instead of HDMI specification values.
From: Clint Taylor
reorder structure of 297, 594 N values to group Audio Sample Frequencies
together to make updating from HDMI specification easier.
V2: Match patch 1/2 version
Cc: Jani Nikula
Cc: sta...@vger.kernel.org
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c |
From: Clint Taylor
Added HDMI 2.0 N and CTS values for 594 Pixel clock modes. Reorganized
structure to group by Audio Sample Frequency
Clint Taylor (2):
drm/i915/hdmi: Add HDMI 2.0 audio clock recovery N values
drm/i915/hdmi: Reorder structure to match specification
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value
mode instead of HDMI specification values.
V2: Fix 88.2 Hz N value
Cc: Jani Nikula
Cc: sta...@vger.kernel.org
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_audio.c | 17
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev2)
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5037 -> Patchwork_10582 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Thu, Oct 25, 2018 at 04:07:14PM +0300, Joonas Lahtinen wrote:
> Quoting Zhenyu Wang (2018-10-23 06:46:59)
> >
> > Hi,
> >
> > Here's gvt-next-fixes for 4.20 with three changes. Mostly
> > to fix possible arbitrary update on guest GGTT entry and
> > with proper invalidate of old entry. Another
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev2)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers
Okay!
Commit:
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev2)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
300ba10fc48e drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:51: CHECK:MACRO_ARG_REUSE: Macro
Conceptually user should be knowing the feature status through uAPI.
So HDCP authentication failure information need not DRM_ERRORS.
They are needed only for ENG debugging.
And also in HDCP we tolerate the retries for HDCP authentication.
Hence if we print the failure info initial attempts as
This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.
This series enables color conversion for Full Range YUV data,
limited range handling will be
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats.
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro
Op 25-10-18 om 14:01 schreef Chunming Zhou:
>
> 在 2018/10/25 18:36, Maarten Lankhorst 写道:
>> Op 25-10-18 om 12:21 schreef Chunming Zhou:
>>> drivers/gpu/drm/drm_syncobj.c:202:4-14: ERROR: function
>>> drm_syncobj_find_signal_pt_for_point called on line 390 inside lock on line
>>> 389 but uses
1 - 100 of 178 matches
Mail list logo
