== Series Details ==
Series: drm/i915/selftest: test aligned offsets for 64K
URL : https://patchwork.freedesktop.org/series/51707/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10636_full =
== Summary - SUCCESS ==
No regressions found.
==
== Series Details ==
Series: drm/i915/selftest: fix 64K alignment in igt_write_huge
URL : https://patchwork.freedesktop.org/series/51705/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5051_full -> Patchwork_10635_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915/execlists: Poison the CSB after use
URL : https://patchwork.freedesktop.org/series/51703/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5051_full -> Patchwork_10634_full =
== Summary - SUCCESS ==
No regressions found.
== Known
On Thu, Oct 25, 2018 at 09:49:40PM -0700, Anusha Srivatsa wrote:
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving forward we can use the state
> to have error correction on other scenarios too
> if needed.
>
> Suggested-by: Ville
On Thu, Oct 25, 2018 at 09:49:38PM -0700, Anusha Srivatsa wrote:
> DP 1.4 has Forward Error Correction Support(FEC).
> Add helper function to check if the sink device
> supports FEC.
>
> v2: Separate the helper and the code that uses the helper into
> two separate patches. (Manasi)
>
> v3:
> -
On Thu, Oct 25, 2018 at 09:49:37PM -0700, Anusha Srivatsa wrote:
> Similar to DSC DPCD registers, let us cache
> FEC_CAPABLE register to avoid using stale
> values. With this we can avoid aux reads
> everytime and instead read the cached values.
>
> v2: Avoid using memset and array for a single
>
On Fri, 19 Oct 2018 at 18:51, Daniel Vetter wrote:
>
> Hi all,
>
> This is just to collect feedback on this idea, and see whether the
> overall dri-devel community stands on all this. I think the past few
> cross-vendor uapi extensions all came with igts attached, and
> personally I think there's
== Series Details ==
Series: series starting with [v4,1/2] drm: Add drm_any_plane_has_format()
URL : https://patchwork.freedesktop.org/series/51700/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5050_full -> Patchwork_10633_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: series starting with [RFC,1/4] drm/i915: Add Display Gen info.
URL : https://patchwork.freedesktop.org/series/51717/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10643 =
== Summary - FAILURE ==
Serious unknown changes
== Series Details ==
Series: series starting with [RFC,1/4] drm/i915: Add Display Gen info.
URL : https://patchwork.freedesktop.org/series/51717/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add Display Gen info.
== Series Details ==
Series: series starting with [RFC,1/4] drm/i915: Add Display Gen info.
URL : https://patchwork.freedesktop.org/series/51717/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
082cfae8228c drm/i915: Add Display Gen info.
-:83: CHECK:MACRO_ARG_REUSE: Macro
== Series Details ==
Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3)
URL : https://patchwork.freedesktop.org/series/51713/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10642 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Record the scratch pte
URL : https://patchwork.freedesktop.org/series/51698/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5050_full -> Patchwork_10632_full =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3)
URL : https://patchwork.freedesktop.org/series/51713/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Remove CNL from WA 827
Okay!
Commit:
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51711/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10641 =
== Summary - SUCCESS ==
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51558/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5050_full -> Patchwork_10631_full =
== Summary -
== Series Details ==
Series: drm/i915/fia: FIA registers offset implementation. (rev2)
URL : https://patchwork.freedesktop.org/series/51566/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10640 =
== Summary - FAILURE ==
Serious unknown changes coming
Let's prefer DISPLAY_GEN over GEN check on Display related files.
On this first step let's just convert using coccinelle and later
we adjust the gray areas and work to minimize the existent mix
of GEN and platform checks.
spatch -sp_file display_gen.cocci intel_atomic*.c intel_audio.c \
Now that GLK is properly defined as gen10 display
we can use gen9 display to identify this case here
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_color.c | 3 +--
drivers/gpu/drm/i915/intel_pm.c| 5 +
2 files changed, 2 insertions(+), 6 deletions(-)
diff
Now that we have INTEL_DISPLAY_GEN checks in place we
can recognize Geminilake as Gen 10 display instead of
individual platform checks mixed with gen ones.
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
Introduce Display Gen. The goal is to use this to minimize
the amount of platform codename checks we have nowdays on
display code.
The introduction of a new platform should be just
gen >= current.
Just a gen++ without exposing any new feature or ip.
so this would minimize the amount of patches
== Series Details ==
Series: series starting with [1/5] drm/i915: Remove CNL from WA 827
URL : https://patchwork.freedesktop.org/series/51713/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10639 =
== Summary - SUCCESS ==
No regressions found.
According to BSpec this is not needed anymore:
"This workaround is no longer needed since NV12
support is dropped for the affected projects.
"
v2: Rebase
Cc: Clinton Taylor
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 10
== Series Details ==
Series: series starting with [1/5] drm/i915: Remove CNL from WA 827
URL : https://patchwork.freedesktop.org/series/51713/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Remove CNL from WA 827
Okay!
Commit: drm/i915/cnl:
These were always useless since CNL A stepping needed many
more workarounds that were never introduced and also
we started Linux work on CNL B stepping anyways.
v2: Clinton noticed this isolated patch outside of series
wasn't compiling due to missing brackets.
Cc: Clinton Taylor
Cc: Paulo
== Series Details ==
Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off
(rev6)
URL : https://patchwork.freedesktop.org/series/49447/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10638 =
== Summary - SUCCESS ==
No regressions
On 10/29/2018 04:00 PM, Rodrigo Vivi wrote:
CNL A stepping was the only affected there.
But also it is time to clean old pre-production
CNL Workarounds, so let's just remove and clean
this W/A.
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
On Mon, Oct 29, 2018 at 04:23:15PM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
>
> v2:
> - Follow spec for numbering -
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51711/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10637 =
== Summary - FAILURE ==
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)
Cc: Lucas De Marchi
Signed-off-by:
On Fri, Oct 26, 2018 at 03:31:57PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the
== Series Details ==
Series: drm/i915: Account for scale factor when calculating initial phase (rev2)
URL : https://patchwork.freedesktop.org/series/51696/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5049_full -> Patchwork_10630_full =
== Summary - WARNING ==
Minor
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51711/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dsc: Add
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51711/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
40a5992273a1 drm/i915/dsc: Add slice_row_per_frame in
== Series Details ==
Series: drm/i915/selftest: test aligned offsets for 64K
URL : https://patchwork.freedesktop.org/series/51707/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052 -> Patchwork_10636 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Mon, Oct 29, 2018 at 10:34:58PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the
According to BSpec this is not needed anymore:
"This workaround is no longer needed since NV12
support is dropped for the affected projects.
"
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 10 --
1 file changed, 10
CNL A stepping was the only affected there.
But also it is time to clean old pre-production
CNL Workarounds, so let's just remove and clean
this W/A.
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2
These were always useless since CNL A stepping needed many
more workarounds that were never introduced and also
we started Linux work on CNL B stepping anyways.
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c| 10 ++
Let's introduce HAS_NV12 to check for feature itself
than spread the platform checks everywhere.
Also let's introduce the WA number that is the
cause of having NV12 disabled on both SLK and BXT.
According to Spec:
WA 0870: "Display flickers with NV12 video playback in
Y tiling mode.
WA: Use
First of all I believe this WA as written here was wrong.
Because it is listed on BSpec only for SKL and BXT, exactly
the only 2 platforms skipped here.
But also it is written there that we don't need this WA
anymore:
"This workaround is no longer needed since NV12 support is
dropped for the
Ville Syrjala writes:
> From: Ville Syrjälä
>
> Add a function to check whether there is at least one plane that
> supports a specific format and modifier combination. Drivers can
> use this to reject unsupported formats/modifiers in .fb_create().
>
> v2: Accept anyformat if the driver doesn't
From: Animesh Manna
ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.
v2: (James Ausmus)
- Also handle ICL as GEN9_LP in i915_drm_suspend_late and
i915_drm_suspend_early
- Add DC9 to gen9_dc_mask for ICL
- Re-order GEN checks for newest
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode
== Series Details ==
Series: drm/i915/selftest: fix 64K alignment in igt_write_huge
URL : https://patchwork.freedesktop.org/series/51705/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5051 -> Patchwork_10635 =
== Summary - SUCCESS ==
No regressions found.
External
Quoting Bob Paauwe (2018-10-29 21:39:49)
> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
>
> Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing
DSC is supported on eDP starting GEN 10 display (on GLK) and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x0006F) to
read the decompression capabilities of the sink device.
This entire block of registers is
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v6:
* Take mode_clock and mode_hdisplay as
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define
Quoting Bob Paauwe (2018-10-29 21:39:51)
> The distincsion between aliasing, full, and 4 level ppgtt is primarily
No, it is not. The distinction is the HW capability of the platform. snb
would be doing full-ppgtt but can't handle a mm switch...
-Chris
From: Anusha Srivatsa
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
== Series Details ==
Series: drm/i915/selftest: fix 64K alignment in igt_write_huge
URL : https://patchwork.freedesktop.org/series/51705/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/selftest: fix 64K alignment in igt_write_huge
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
The distincsion between aliasing, full, and 4 level ppgtt is primarily
the size of the address range. Now that we have that specified for
each platform, having a separate enum that specifies the ppgtt type is
redundant. A platform either has support for ppgtt or it doesn't.
This means we can now
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that
== Series Details ==
Series: drm/i915/execlists: Poison the CSB after use
URL : https://patchwork.freedesktop.org/series/51703/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5051 -> Patchwork_10634 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode
On Mon, Oct 29, 2018 at 10:39:21PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:39PM -0700, Manasi Navare wrote:
> > DSC can be supported per DP connector. This patch adds a per connector
> > debugfs node to expose DSC support capability by the kernel.
> > The same node can be used
== Series Details ==
Series: drm/i915/selftests: Test vm isolation (rev3)
URL : https://patchwork.freedesktop.org/series/51689/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5047_full -> Patchwork_10629_full =
== Summary - SUCCESS ==
No regressions found.
== Known
Quoting Matthew Auld (2018-10-29 20:37:34)
> When using softpin it's not enough to just pad the vma size, we also
> need to ensure the vma offset is at the start of the pt boundary, if we
> plan to utilize 64K pages. Therefore to improve test coverage we should
> use both aligned and unaligned gtt
Older platforms require fence registers to perform blits, and so
userspace is expected to mark up the objects to request fences be
assigned.
Fixes: ff2db94acb53 ("igt/gem_tiled_fence_blits: Remove libdrm_intel
dependence")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108591
== Series Details ==
Series: series starting with [v4,1/2] drm: Add drm_any_plane_has_format()
URL : https://patchwork.freedesktop.org/series/51700/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5050 -> Patchwork_10633 =
== Summary - SUCCESS ==
No regressions found.
On Fri, 2018-10-05 at 12:03 -0700, Manasi Navare wrote:
> On Fri, Oct 05, 2018 at 11:56:43AM -0700, Dhinakaran Pandiyan wrote:
> > The bits weren't defined in descending order.
> > v2: Move definitions in a separate patch (Manasi)
> >
> > Cc: Manasi Navare
> > Signed-off-by: Dhinakaran Pandiyan
On Wed, Oct 24, 2018 at 03:28:39PM -0700, Manasi Navare wrote:
> DSC can be supported per DP connector. This patch adds a per connector
> debugfs node to expose DSC support capability by the kernel.
> The same node can be used from userspace to force DSC enable.
Why is the force_dsc thing split
When using softpin it's not enough to just pad the vma size, we also
need to ensure the vma offset is at the start of the pt boundary, if we
plan to utilize 64K pages. Therefore to improve test coverage we should
use both aligned and unaligned gtt offsets in igt_write_huge.
Suggested-by: Chris
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode
On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Record the scratch pte
URL : https://patchwork.freedesktop.org/series/51698/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5050 -> Patchwork_10632 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51558/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5050 -> Patchwork_10631 =
== Summary - SUCCESS ==
On Fri, 2018-10-26 at 12:38 -0700, Dhinakaran Pandiyan wrote:
> A framebuffer can comprise surfaces with distinct tiling formats,
> making checks against modifier alone insufficient. Make use of a
> function to identify a linear surface based on both modifier and
> color
> plane.
>
> v2: Typo fix
On Mon, 29 Oct 2018 at 19:40, Chris Wilson wrote:
>
> Quoting Matthew Auld (2018-10-29 19:36:37)
> > When using softpin it's not enough to just pad the vma size, we also
> > need to ensure the vma offset is at the start of the pt boundary, if we
> > plan to utilize 64K pages.
>
> For testing
On Mon, 2018-10-29 at 16:18 +0200, Ville Syrjälä wrote:
> On Fri, Oct 26, 2018 at 12:53:42PM -0700, Dhinakaran Pandiyan wrote:
> > intel_fb_pitch_limit() has the parameters pixel_format and
> > fb_modifier
> > switched in their positions. The parameters are however used
> > correctly,
> > but
Quoting Matthew Auld (2018-10-29 19:36:37)
> When using softpin it's not enough to just pad the vma size, we also
> need to ensure the vma offset is at the start of the pt boundary, if we
> plan to utilize 64K pages.
For testing purposes, we have to assume the worst as well as best cases.
Looks
When using softpin it's not enough to just pad the vma size, we also
need to ensure the vma offset is at the start of the pt boundary, if we
plan to utilize 64K pages.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 28 +
1
== Series Details ==
Series: drm/i915: Account for scale factor when calculating initial phase (rev2)
URL : https://patchwork.freedesktop.org/series/51696/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5049 -> Patchwork_10630 =
== Summary - WARNING ==
Minor unknown
After reading the event status from the CSB, write back 0 (an invalid
value) so we can detect if the HW should signal a new event without
writing the event in the future.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
On Mon, 2018-10-29 at 20:34 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the messy framebuffer format/modifier validation code
> with a single call to drm_any_plane_has_format(). The code was
> extremely annoying to maintain as you had to have a lot of platform
> checks for
On Thu, Oct 25, 2018 at 05:08:39PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:33PM -0700, Manasi Navare wrote:
> > Infoframes are used to send secondary data packets. This patch
> > adds support for DSC Picture parameter set secondary data packets
> > in the existing
On Mon, Oct 29, 2018 at 12:08:38PM +0200, Jani Nikula wrote:
> On Fri, 26 Oct 2018, Rodrigo Vivi wrote:
> > The specially case for SKL for not controlled sagv
> > is already taken care inside intel_enable_sagv, so there's
> > no need to duplicate the check here.
> >
> > v2: Go one step further
From: Ville Syrjälä
Add a function to check whether there is at least one plane that
supports a specific format and modifier combination. Drivers can
use this to reject unsupported formats/modifiers in .fb_create().
v2: Accept anyformat if the driver doesn't do planes (Eric)
From: Ville Syrjälä
Replace the messy framebuffer format/modifier validation code
with a single call to drm_any_plane_has_format(). The code was
extremely annoying to maintain as you had to have a lot of platform
checks for different formats. The new code requires zero maintenance.
v2: Nuke the
Record the scratch PTE encoding upon creation rather than recomputing
the bits everytime. This is important for the next patch where we forgo
having a valid scratch page with which we may compute the bits and so
require keeping the PTE value instead.
v2: Fix up scrub_64K to use scratch_pte as
If we can prevent stray writes from landing in the scratch page, we can
reuse the same page and same scratch PT for all contexts without fear of
information leaks and side-channels.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c
From: Ville Syrjälä
To get the initial phase correct we need to account for the scale
factor as well. I forgot this initially and was mostly looking at
heavily upscaled content where the minor difference between -0.5
and the proper initial phase was not readily apparent.
And let's toss in a
== Series Details ==
Series: drm/i915/selftests: Test vm isolation (rev3)
URL : https://patchwork.freedesktop.org/series/51689/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5047 -> Patchwork_10629 =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: drm/i915: Simplify has_sagv (rev3)
URL : https://patchwork.freedesktop.org/series/51266/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5045_full -> Patchwork_10627_full =
== Summary - WARNING ==
Minor unknown changes coming with
On Mon, Oct 29, 2018 at 12:19:37PM +0200, Jani Nikula wrote:
> On Tue, 23 Oct 2018, Rodrigo Vivi wrote:
> > RANGE makes it longer, but clear.
>
> IS_GEN_RANGE() was the first proposal, but in review this was changed to
> IS_GEN() following IS_REVID() and IS__REVID().
>
> IMO unnecessary change.
== Series Details ==
Series: drm/i915/selftests: Test vm isolation (rev3)
URL : https://patchwork.freedesktop.org/series/51689/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e9dcbb986f11 drm/i915/selftests: Test vm isolation
-:242: WARNING:LINE_SPACING: Missing a blank line
On Fri, Oct 26, 2018 at 07:53:34PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 25, 2018 at 05:56:36PM -0700, Rodrigo Vivi wrote:
> > While checking the opportunity to add a display_gen
> > check to allow glk and cnl to be on same bucket I noticed
> > these FIXME cases here.
> >
> > So I got the
On Sat, Oct 27, 2018 at 05:24:41AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Prefer IS_GEN check with
> bitmask.
> URL : https://patchwork.freedesktop.org/series/51622/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from
From: Ville Syrjälä
To get the initial phase correct we need to account for the scale
factor as well. I forgot this initially and was mostly looking at
heavily upscaled content where the minor difference between -0.5
and the proper initial phase was not readily apparent.
And let's toss in a
The vm of two contexts are supposed to be independent, such that a stray
write by one cannot be detected by another. Normally the GTT is filled
explicitly by userspace, but the space in between objects is filled with
a scratch page -- and that scratch page should not be able to form an
On Tue, 23 Oct 2018 17:14:34 +0800
Chris Chiu wrote:
> On Thu, Oct 11, 2018 at 2:04 AM Guang Bai wrote:
>
> > On Mon, 8 Oct 2018 08:56:20 -0700
> > Guang Bai wrote:
> >
> > > On Mon, 8 Oct 2018 22:35:34 +0800
> > > Chris Chiu wrote:
> > >
> > > > Thanks! I have no problem with this
== Series Details ==
Series: drm/i915/selftests: Test vm isolation (rev2)
URL : https://patchwork.freedesktop.org/series/51689/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5047 -> Patchwork_10628 =
== Summary - FAILURE ==
Serious unknown changes coming with
== Series Details ==
Series: HAX: poison the CSB after use (rev3)
URL : https://patchwork.freedesktop.org/series/51677/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5045_full -> Patchwork_10626_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues
== Series Details ==
Series: drm/i915/selftests: Test vm isolation (rev2)
URL : https://patchwork.freedesktop.org/series/51689/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb703a5b47b6 drm/i915/selftests: Test vm isolation
-:242: WARNING:LINE_SPACING: Missing a blank line
On Mon, 2018-10-29 at 15:24 +0100, Daniel Vetter wrote:
> On Fri, Oct 26, 2018 at 04:35:47PM -0400, Lyude Paul wrote:
> > There has been a TODO waiting for quite a long time in
> > drm_dp_mst_topology.c:
> >
> > /* We cannot rely on port->vcpi.num_slots to update
> > *
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